October / November 2009

• Misinterpretation of Data–An Architectural Problem?
• People in the News
• Max's Chips & Dips: The USPS uses Opal Kelly's FPGA USB 2.0 Modules in a Real-Time Process Control Application
• What EDA Needs to Do to Start Growing Again
• Verification as a Deterrent?
• Equation-Based DRC: Waste Not, Want Not
• Design Specification Requirements with Verification in Mind
• Freeform DOEs Extend Optical Lithography
• New Business Models Emerge
• 60-GHz Communication: A Total Makeover
• Ain’t No Mountain High Enough
• Teens and Tech: What’s Hot and What’s Not

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July / August 2009

• Reader Wants Print, not Links
• People in the News
• FPGA Vendors Throw Kitchen Sink at Power-Consumption Issues
• Max’s Chips and Dips: the Way Things Were
• Take a System-Level View of IP Integration
• Smaller, Faster and More Parasitic
• SystemVerilog and VMM Overcome WiMAX Verification Challenges
• SystemVerilog Comes of Age
• DSP-Core Evolution Powers Advancements in Communications and Multimedia Technologies
• High-Level Synthesis Improves Productivity without Sacrificing Area, Performance, or Power
• The Impact of 3D Packaging
• Accellera Technical Sub-Committee Enables VIP Interoperability and Reuse
• Women in Technology: Crashing the Silicon Ceiling
• Software Development Principles Should be Applied to IC Design
• Design Specification Requirements with Verification in Mind
• Custom IC Design: They Call This Progress?
• Making Quality A Top Priority in Next-Generation Designs

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April / May 2009

• Power Trump’s Time-to-Market as Main Driver
• People in the News
• Messing with Microcontrollers
• Low Power Designs Need High Power Verification Environment
• Experts at the Table: Platform-Based Design
• How Low Can You Go?
• Can MIPI and MDDI Co-Exist?
• The Three Rs and the Four Ps
• RTL Analysis Is Critical for 45-nm Design Tapeouts
• Too Much of a Good Thing?
• Model OCP Interfaces in SystemC
• Audio-Decode Application Is Realized on Open Virtual Platform
• Effectively Analyze PLL Noise And Jitter

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January / February 2009

• Engineers and Social Media – The Untold Story
• People in the News
• DesignCon Preview
• Chip Power Trends Murky
• Manage ASIC Variability through Back Biasing
• New Pain Points In System-Level Design
• Analog IP Integration Goes beyond a Single-Block Approach
• Industry Standards Should Facilitate Multicore Adoption
• ASIC Verification Is Now Ubiquitous
• PLL Crystal-Oscillator Clock Offers Advantages
• Diagnosis-Driven Yield Analysis Slashes Time to Root Cause of IC Failures

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October / November 2008

• So, You Want To Be a Chip Designer?
• [DFM-DFY] Advanced Scan Test and Diagnosis
• There's Finally an ESL Tool for Hardware Designers
• Drilling and Filling, but not in your Dentist's Chair
• [Chips] Intelligent Approaches Optimize EDA Tool Use
• [ESL] Bet on CleanC Standardization for Multi-Processor SoC Design
• [Programmable Logic] Troubleshoot User Components in a Wishbone-Based Soft Processor Platform
• Now Is the Time to Fix Coverage Metrics
• OVM Versus VMM: What’s Next?
• GSA Mixed-Signal/RF Subcommittee Is Facilitating an Analog Ecosystem
• Off-Axis Illumination Trends Impact Modern Lithography
• Exciting News from Tanner EDA
• People in the News
• Details Hold Key to ASIC-Prototyping Trends
• The End of Proprietary Virtual Platforms and Analog Designs
• New Standards Enhancing Interoperability and Innovation in the EDA Industry

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September / August 2008

• Reader’s Gain with New Technology Community!
• People in the News
• Evolution and Revolution Go Hand in Hand in Memories
• [Max's Chips and Dips] Accellera announces latest version of Verilog-AMS
• Object-Oriented Programming— Steep Learning Curve Ahead
• [Behind the Numbers] Are Solid-State Drives as Good as They Claim?
• Low-Risk, High-Speed Interface IP Meets Stricter Performance and Functional Requirements
• [Low Power Design] Low-Power Concerns Move to the Forefront of Memory Design
• [DFM-DFY] Quantifcation-Based Verification Checks Embedded-Systems Video Quality
• [ESL]Platform-Development Approach Simplifies Mobile-Device Design
• [IP Design] Automated CDC Checking Aids IP Reuse
• [DFM-DFY] OTP Bit-Cell Architecture Is Foundry-Friendly
• [ESL] Get Software into the Hardware Design Loop
• Vanguard Program Model Strengthens Verification Portion of ESL Design
• Simplifying Functional Verification through Partnering
• [No Respins] SystemC TLM-2.0 Becomes Virtual Reality for Software Developers

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July 2008

• [Top View] The Time Has Come for TLM in Verification
• eChip Debut Hints at Something New at Summer’s End
• Product and Services
• Events in the News
• [Top View] The Time Has Come for TLM in Verification
• Globalization -- The Other Side
• [Max's Chips and Dips] Sonics Smart On-Chip Interconnects
• WHAT ARE THE ENABLERS OF ESL?
• It’s Time to Make Noise about Co-design−Got Package?
• [Report] MemCon2008 Report
• [No Respins] The Augmented Role of Offshore Design Centers

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June 2008

• It's the End of the World as we know it!
• Product News From DAC
• DAC - A Conference for Change
• [MAX'S CHIPS & DIPS] RFID from Medical Supplies to Bananas
• [The Inside Pages] Excerpt from "Software Development for Embedded Multi-Core Systems, A Practical Guide Using Embedded Intel(R) Architecture"
• Virtual Platforms Rely on Models, Models and More Models
• Collaboration Models
• Coding Practices Adapt to a Low-Power World
• SystemVerilog Meets Emulation
• Minimizing the Effects of Manufacturing Variation During Physical Layout
• Cutting-Edge Application Demands Engineering Agility
• Integrated Thermal Analysis in the IC Design Flow
• Integrate and Verify SystemC Models in a Graphical ESL Testbench
• [No Respins] Is that an elephant in your flow?

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April/May 2008

• Burning Issues in TestBench Automation
• Keeping FPGAs on Time
• [Max's Chips & Dips] Silicon Canvas Blows My Socks Off
• [Editor's Note] Synopsys and the Power of Programmability
• [Focus Report] What makes chips different?
• [Top View] Performance and Cost Now Drive Emulation
• Make an Informed Build or Buy Decision for Memory-Controller Solutions
• Get Designs Right at 65-nm and Beyond
• Cellular Standards May Demand Alternatives to SDR
• [Dot.org] The Second Commandment for Effective Standards
• [No Respins] Compilation Can Play a Big Role in System Performance

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March 2008

• Editor's Note: EDA Industry Caught in the Middle
• Chip-Package-Board Co-Design: It's a Brave New World
• Nightmares in Functional Verification
• On-Chip Thermal Analysis Is Becoming Mandatory
• Competitive Options Exist for On-Chip Resistive Calibration
• Make Verification Work with Multiple Levels of Abstraction
• CMOS Source Resistance Causes Drop In Source-Follower Gain
• Motion-Control, Image-Sensor, and PoE ICs Simplify Intelligent Camera Design -- Part 1
• [DOT.ORG] Margin Myopia Blurs Chip Supply-Chain Future
• [No Respins] SDR Development Challenges Are Revealed
• Power Forward Initiative Publishes On-Line Guide to Low-Power Design with the Common Power Format

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January/February 2008

• EDA Is Stepping Up to Meet New DFM Demands
• Watermarking Your Chip Design
• Full-Circuit Performance Simulation Tackles Big Analog/RF Designs
• With ASIC Verification in Distress, FPGA-Based Prototyping Has Come to the Rescue
• TMDS Bridging Paves Way to Display Port
• Phase-Locked Loops Are Demystified
• Editor's Note: Technological Obsolesce vs the Public Domain
• Max's Chips and Dips: Cool News from Agilent EEsof
• [Behind the Numbers] Multicore Trends Continue to Drive the Embedded Market in 2007
• [Dot.org] Debug Grows Increasingly Critical
• [No Respins] Will Traditional Parallel Programming Meet Today’s Challenges?

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October/November 2007

• Max's Chips and Dips - MATLAB-to-C Flow Supports State-of-the-Art EDA Tool Development
• Get an Insurance Policy for Your Design
• Improved IP-Centric Post-Silicon Validation Solutions Create A New IP Opportunity
• Future Verification Appears Uncertain
• Simplify the Setup of Constrained- Random-Test Environments
• Improve PC-Board Reliability by Adding Power Analysis to the FPGA Design Flow
• [ Nevertheless ] Don't Get Critical IP from a Supermarket
• [ No Respins ] Engineers Design Platforms, Not Products
• Editor's note: IP Quality and Verification Remain Leading Issues
• [ Behind The Numbers ] MIPI IP Core Eases Camera- Phone Development
• [ Technology Book Review ] Metric-Driven Design Verification
• [ Head2Head ] Three Views on Verification Challenges
• [ Dot.Org ] Kick-Starting RTL Power-Aware Verification

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August/September 2007

• Max's Chips and Dips: Seeing Black-and-White Schematics in Color
• Mysteries of Reproducible Chip Design
• Global Approach Could Enable Low-Energy Software-Defined Radios
• New Look at an Old Standard: Current Conveyor in Today's Designs
• Perform Design-for-Test and Power Management at the RTL
• Wireless Sensor Networks Rely on Embedded OTP Nonvolatile Memory
• [ No Respins ] New Multicore Architectures Face Substantial Challenges
• [ Nevertheless ] Core Confusion: A Rose by Any Other Name
• Take Power-Aware Design from Concept and Verification to Physical Implementation
• Editor's note: Continuing EDA Consolidation Pushes VSIA to IEEE
• Technology Book Review: Low Power Done Right
• [ Behind The Numbers ] What's Beyond CMOS? The Answer Is CMOS.
• [ Dot.Org ] The Unified Power Format -- A Standard Done the Right Way

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June/July 2007

• Achieving Success in an Increasingly Complex Design Environment
• Max's Chips and Dips: A Fabulous Flurry of Activity
• Today's SoC Designs Demand a Customizable, Standalone Transistor-level Design Checker
• [ Nevertheless ] Hope and Fear: Doing Intellectual-Property Business in China
• SystemVerilog Assertions and Functional Coverage Support Advanced Verification
• DDR IP Integration: How to Avoid Landmines in this Quickly Changing Landscape
• Reliabililty-Simulation Environment Tackles LSI Design
• Soft IP Actually Does Exist for the Analog ASIC
• [ DAC Special ] Empowering the Next Generation of Electronics Designers
• Editor's note: Are EDA and Semiconductor Markets Cycling Back or Spiraling into the Future?
• [ Behind The Numbers ] Are FPGAs Usurping ASIC Design Investigations and Design Starts?
• Know the Key Aspects of IP Integration
• [ Dot.Org ] Integration and Power Highlight Latest Standards

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April/May 2007

• Multiple XDSL Flavors Challenge Chipmakers
• Max's Chips and Dips: Elliptic Curve Cryptography
• Collaboration is Key to Building Next-Generation Networks
• Platform-Based Environment Speeds Software Development
• A Novel Approach to the Parallel Processing of Layout Data
• ASIC Prototyping with FPGAs
• [ Nevertheless ] New Identity for an Old Gateway
• [ No Respins ] Unlock the AMS and RF Bottleneck
• Editor's note: Building Editorial on the Best Foundation
• [ Behind The Numbers ] Is the Core Meltdown Just a False Alarm?
• [ Dot.Org ] Power To The People

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February/March 2007

• Max's Chips and Dips: I Can See Clearly Now (with Clear Shape)
• Design for Lithography
• Semiconductor Industry Faces Structural Changes Around IP
• DFM and DFY: Old Solutions to New Problems
• Will Timing-Exception Verification Reach Its Full Potential?
• SystemVerilog Transmigrations Lead to Flexible and Interoperable Verification
• Editor's note: Consumers Forget the Real Cost of Commodified Technology
• [ Nevertheless ] The Imperative for a Yield-Modeling Ecosystem
• [ No Respins ] Yes, You Can Just Do It
• [ Behind The Numbers ] 45-nm Chips Are Arriving Sooner Than Expected
• [ Head2Head ] DFM Deathwatch? Or Does D Really Come Before M?
• [ Dot.Org ] EDA Standards: Have We Learned Our Lessons?

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December 2006/January 2007

• Transaction-Level Modeling Gains Further Momentum
• Max's Chips and Dips - Embedded Developers Should Be Ahead of the Curve . . . Not Behind It!
• Editor's note: Puzzling Predictions for 2007
• ESL Synthesis + Power Analysis = Optimal Micro-Architecture
• Foundry Support Is Critical to SoC Design and Implementation
• Building Blocks Simplify Multicore in FPGAs
• Proper Planning Assures SoC Power Integrity
• [ Nevertheless ] One Value Chain, Divisible But with Liberty and Justice for All
• [ No Respins ] Hybrid Simulation Comes to the Rescue
• [ Dot.Org ] In Search of the Holy Grail: Making Chips Cost Effective, Power Efficient, and Faster

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October/November 2006

• Max's Chips and Dips: Prisoner PCell Block A
• The Man With The Twisted IP [TWIS]
• Automotive Electronics Rise To Meet Consumer Demand
• GALS Technique Fells Massive Clock Trees
• Reconfigurable Array Processor Satisfies Multi-Core Platforms
• Lego Approach May Offer Salvation For IP Integrators
• Time To Market Drives SoC Design To Higher Levels Of Abstraction
• NEVERTHELESS: Learning From Joe: Where's The Strategy In Engineering?
• NO RESPINS: Verification Needs To Be Reigned In
• Editor's note: Oregon Can Still Have A High-Tech Future
• High-Performance PLDs Journey Where FPGAs and DSPs Don't Dare To Go

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August/September 2006

• Max's Chips and Dips: Embedding Security in your Designs
• Outsourcing Poses Unique Challenges for the U.S. Military-Electronics Community
• Link IP Cores with Smart Interconnects for Complex SoCs
• Military Seeks Systematic Approach to IC Design
• MEMS Design and Layout Tools: Key Considerations in a Crowded Market
• Create A CMOS Design Using Swept Optimization
• NEVERTHELESS: Improve Project Predictability
• NO RESPINS: ESL Isn't Just for RTL Anymore
• Editor's Note -- Foreign Fabs and Killer Apps
• Books And Reports: Analyst Looks At Design-Implementation Market
• Engineering In Education: Earthrace Uses Earth-Friendly Chips
• Head-To-Head: Does Analog or Digital Cause Bigger Problems in SoC Sign-off?

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June/July 2006

• Max's Chips and Dips: Wow! There's so much going on!
• IP Gains Quality Rating
• True DFM/DFY Solutions Require More Than OPC And DRC
• Debugging Analog Designs Goes Beyond Waveform Analysis
• Challenges Abound When Implementing DFM Tools in Nanometer Flows
• Legacy FPGA Designs Can Be Migrated to Achieve Better Performance
• Nevertheless -- New-Generation Semiconductor Fabrics Need New Tools Approach
• Editor's Note -- The Systems Da Vinci Code
• Head-to-Head Rematch on ESL: One Year Later
• DOT.ORG: SystemVerilog: The Front Wave of Success

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April/May 2006

• EDA Tools Shouldn't Cost More Than the Design Engineer
• FPGAs Hold the Aces in Chip-Level Encryption for Smart Cards
• The Death of the Structured ASIC
• Analog-RF IP Integration Challenges SoC Designers
• Flash Memory Moves from Niche to Mainstream
• Assertion-Based Verification Shortens Project Design Time
• DOT.ORG: Introducing CEDA: An Organization for the CAD Community
• Determine Foundry-Model Problems Without Touching a Wafer
• Jump-Start Software Validation in an ESL Environment
• EDITOR'S NOTE: E-Newsletters Invite Wireless Designers Online
• Book Review: In-Depth Book Set On EDA
• Engineering In Education: Synopsys Sees Future In Education
• Product News: Verification, IP, AMS, Power and Security Tools Make the News

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February/March 2006

• Compare Logic-Array To ASIC-Chip Cost per Good Die
• Easily Implement PLL Clock Switching for At-Speed Test
• There's No Prize for Taking the Long Road
• Security Plays Key Role in IP-based Design Growth
• Take Architecture Design Beyond the Spreadsheet
• Transactional-Level Modeling Benefits Memory Controller
• DOT.ORG:   Security: It's Not Just Encryption
• Does Engineering Have a Future in the U.S?
• Scientists and Engineers Look Forward to Career Makeover
• Behold The Future of Custom Silicon

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December 2005/January 2006

• Myths Yield to Reality in Study of ESL Methodologies
• Science Fiction: Is It technology's reporter or Muse?
• It's Been A Busy Year for EDA and Semicon Organizations
• Automate and Control the Functional-Verification Process
• ESL Strategies guarantee Successful SoC Design
• Bridge the gap between Design and Manufacturing
• Crossing the Chasm: Modeling Process Variability in the Design Flow
• One Year Later: Have I Met My Goals?
• Book Review: The Definitive Guide to How Computers Do Math by Clive
• What Is the Most Cost-Effective and Performance-Efficient Path to DFY?
• Engineering & Education

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October/November 2005

• Is there a Practical Approach to Reducing Silicon Debug Time?
• Latest Challenges & Trends in Chip Verification
• Build an Optimized Chip-Verification Environment for Hardware Simulation
• Viewpoint--Numerous Approaches Tackle Design for Debug
• Enhancements to RFIC Simulation Improve Circuit Verification
• Constrained Random Testing Causes Paradigm Shift
• Hardware Emulators Evolve to Meet ESL Demands

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Aug / Sept 2005

• Technological Innovation Requires More than Just Money
• Product News
• Intermediate Verification Model Bridges High and Low Levels of Abstraction
• Good Engineering Practices Minimize Design-Porting Effort
• Component Software Accelerates EDA-Tool Development
• What is the Best Way to Take Algorithmic Design to Implementation?
• Aggregation Drives Successful IP Reuse
• IC Economics 101
• Shape The Design of Wireless Chips

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June / July 2005

• The IEEE Embraces a Systems View for EDA Council
• Product News
• Navigating the Silicon Jungle: FPGA or ASIC?
• A Tale of Two Languages: SystemC and SystemVerilog
• Start at the Top to Reduce Re-Spins for Analog-Digital Chips
• Manage Complexity in Nanometer SoC Designs
• Advantages Abound for a Conversion-Free, Low-Cost Path to Volume Production
• Is Bigger Better? What Does the Future Hold for Small IP Providers?
• IP Reuse Gets a Reality Check
• In Search of an ESL Design Methodology

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April / May 2005

• EDA Could Learn a Lot from Systems Engineering
• Product News
• Why Hasn't Behavioral Synthesis Caught on Among Chip Designers?
• Analog Challenges the Digital Design Mosaic
• Guidelines to Maximize the Performance of Verilog-AMS/VHDL-AMS Behavioral Modeling
• On-Chip Nonvolatile Memory Proves Ideal for Consumer Applications
• Math Does Matter in Analog Chip Design
• Analog Issues Confront Digital Designers
• SPIRIT: Structure for Packaging, Integrating, and Re-Using IP within Tool Flows
• It's All about Dollars and Cents

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February / March 2005

• Of Systems, Chips, and the Internet
• News
• ESL: Why Is There No Convergence on a Definition?
• Take Designs from Algorithms to Artwork
• Speed SoC Software with Coprocessor Synthesis
• The Meaning of ESL Invites Confusion and Competition
• Design FPGA-Based DSPs for Performance and Power
• Use Co-Simulation for the Functional Verification of RTL Implementations
• ESL: More Languages Than the European Union

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December / January 2005

• Continuity Mingles with Change
• News
• Cinematic-Graphics Design Deluges Traditional Verification
• Take The Next Productivity Leap
• ESL Development Gets A Leg Up
• 3D SoC Design Makes Its Debut
• Microcontroller Design Gets Revamped
• Si2: Innovation Through Collaboration
• A True DFM Solution Offers The Perfect Scenario

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October/November 2004

• Good times, Bad times
• News
• Debugging IP-laden Designs
• Logically Flashing
• Design for Volume
• Mixed HDLs plus HVL: Part 2 of 2
• Embedded Test Improves Yield and Time to Market
• PCI-SIG: Several Years of Innovation
• Video Communications Design Needs a New Platform

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August/September 2004

• To Everything, There is a Season
• News
• Delay Testing for Nanometer Chips
• Designing with Real Intent's Verix
• Embedded Logic Analyzer Speeds SoPC Design
• Hot Chips? ... Not!
• FPGA Tools
• Mixed HDLs plus HVl: Part 1
• Design Automation to the Rescue!

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July/July 2004

• Editorial--Benchmarks
• News
• Caution: Clock Crossing
• Verification Tools
• FPGAs Go, Go, Go
• Analog PDK 101
• Structured ASICs: A Reality Check
• Head2Head--FPGA Pricing
• Dot.Org--The Metrics of Success
• Viewpoint--Get The Lead Out!

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April/May 2004

• Editorial--Cycles, Innovation, and Offshore Jobs
• News
• Navigating the Mixed-Signal Maze
• Focus Report: Electronic System-Level (ESL) Tools
• ESL Bridges Design and Verification
• Putting the e into Elegant Verification
• Easing Today's Verification Language Bedlam
• Head2Head--Hardware Verification: Custom or FPGA?
• Dot.Org--Open Core Protocol: The SystemC Models
• Addressing Design Yield Prior To Silicon

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February/March 2004

• Editorial--Celebrate!
• News
• FPGA helps a Battlebot Rock On
• Integrating Complex I/O in an SoC
• Roll Your Own Micro
• From IC to I See--The CMOS Imager Challenge
• A Hot DATE in Paris
• Dot.Org--Addressing the IP Quality Problem
• Viewpoint--Emerging Markets Create Demand for FPGAs

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December/January 2004

• Editorial--One Tumultuous Year to the Next
• News
• Analog Hard IP Made Portable
• Hardware Tools for Design
• Assertions Enter the Verification Arena
• C Models Speed Co-Design
• Enabling Signal Conditioning Circuitry
• C for Design?
• Dot.Org--A Fresh Look at the New Si2
• Viewpoint--What is Silicon Virtual Prototyping?

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October/November 2003

• Editorial--Hello EDA world
• News
• Power: A Costly and Critical Parameter
• Focus on Analysis Tools
• Design of Base I/O Libraries
• Flow Management Tool Tracks Files
• Under the Hood of Library IP
• Dot.Org--Quality IP [QIP]
• Chip Designers Need New Approach to be Successful

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