SystemVerilog in Japan

During the EDSF show held in Yokohama in late January, there were several meetings between members of JEITA and members of the IEEE

Design Automation Standards Committee (DASC).  These meetings were designed to bring the various organizations‘members up to speed on the other groups’ activities.  This is important, given that there are overlapping interests among the various groups, but time zone differences often make meeting together difficult.

First, an introduction to JEITA—the Japan Electronics and Information Technology Industries Association.  According to its website, JEITA’s purpose is:

The list of product areas covered by JEITA is wide ranging– from the component level (e.g., transducers and electronic tubes) to the full product

level (e.g., broadcasting equipment and computers)—and basically covers every corner of the world of electronics. Most relevant to this article, one of the topics that JEITA covers is software in the electronics space, including EDA software.

During the meeting, Satoshi Kojima, from NEC System Technologies and a JEITA Fellow, presented an introduction to the EDA Technical Committee (EDA-TC) of JEITA, which as figure 1 shows, falls in the JEITA hierarchy in the semiconductor area.  As shown in figure 2 below, the EDA-TC, which is lead by Yoshida-san of Renesas has three main areas of focus:

1. Acceleration of standardization
2. Solutions for technical challenges
3. Promotion of EDA technology

Focusing on the first topic area, EDA standardization, there are three topics of interest: SystemC, LSI-Package-Board Interoperable Design and SystemVerilog. 

The SystemC Working Group (WG), led by Hiroshi Imai of Toshiba, was very active in 2010, providing significant input to development of the IEEE P1666 SystemC standard.  This draft standard is now working its way through the latter stages of the IEEE process, and P1666-2011 is expected to be approved this year.  Given this, the JEITA SystemC Working Group will be winding down its work this year, while the SystemVerilog WG, to be lead by Kasumi Hamaguchi of Panasonic,  will be ramping up in anticipation of the P1800-2012 SystemVerilog effort currently being developed under the auspices of the IEEE DASC.

The first informational meeting held in Yokohama was between the entire DASC and JEITA.  In this meeting, the DASC WG chairs introduced the JEITA members to the details of the various working groups that the DASC sponsors.  Kojima-san then provided an update on the JEITA EDA-TC—the two slides I used above came from his presentation.

This meeting was followed by a second meeting during which the IEEE P1800 SystemVerilog WG’s plans were outlined by its chair (Karen Pieper of Tabula).  Karen outlined the organization of the P1800 group:

1. The Working Group management layer, where all changes to the SystemVerilog Language Reference Manual (LRM) are approved, and business aspects, e.g., hiring technical writers, are handled.
2. The champions—a group of SystemVerilog gurus, whose charter is to look at the work produced by the various technical committees, and ensure consistency across the language.
3. The technical committees that look at specific aspects of SystemVerilog and enhance, correct and clarify the language.

Figure 3 shows the organization of the P1800 WG.

Each of the chairs of the technical committees subsequently presented the areas they are investigating.  All are working towards producing a new draft SystemVerilog LRM by the end of 2011, with the vote on this draft and subsequent approval by the IEEE anticipated during 2012.

Finally, Tom Alsop of Intel, co-chair of the Accellera VIP Technical Subcommittee (VIP -TSC), informed the JEITA attendees of the work that has been done on the Universal Verification Methodology (UVM) standard that is expected to be approved early in 2011.  While the IEEE P1800 group is defining a newer version of the SystemVerilog language itself, Tom’s VIP-TSC group has developed a way of using the language to help “define standard technology and/or methods to realize a modular, scalable and reusable generic verification environment”, according to the group’s Accelelra.org web page.

One question that was raised concerned the potential for the IEEE P1800 “language-definition” work and the UVM “language-use” work getting out of sync.  After all, it was asked, if UVM is released in 2011 and a new version of SystemVerilog is released in 2012, is there not a danger that the UVM will quickly become out of date due to language changes?  This concern was addressed by Karen Pieper by noting that the 2012 version of SystemVerilog will be backwards compatible with the current version of the language.  Thus, as Tom Alsop noted, while the UVM might be updated later to take advantage of new features found in P1800-2012, it will remain compatible with both the current and future versions of SystemVerilog.

At the end of the joint meeting, the members of the JEITA SystemVerilog WG indicated that they had a good understanding both of the ongoing work of the IEEE SystemVerilog group, and of the more imminent UVM release.  They also indicated that they would be meeting to decide whether to directly participate in the IEEE WG activities, or to produce a set of requirements for the consideration of the P1800 group (or both).  In any case, users in an important region will have their voices heard in 2011 as SystemVerilog is developed, much as in 2010 the JEITA SystemC WG helped channel the voices of Japanese SystemC users during the development of the P1666-2011 standard.