DVCON & DATE 2011: A Rerospective
The last two months since my last post have been extremely busy for me—several weeks out of the office, and new responsibilities at work. In this post, I’d like to briefly look the two conferences, DVCon and DATE that I attended during this period.
By now everyone knows that DVCon (held in early March in San Jose, CA) was a success by any measure—an increased number of attendees, more papers submitted, a filled exhibition hall and so forth. As a member of the conference’s Steering Committee and an officer of Accellera, which sponsors it, I am doubly pleased with DVCon’s continuing success.
As usual, this conference had a “laid back” feel, unlike the frenetic DAC, which allowed time for insightful discussions with fellow attendees—the sort of discussions that would have been difficult to have at DAC where every minute seems be reserved for some pre-planned meeting or another. But there was another trend that I noticed at DVCon: the continued emergence of the “Design” portion of the “Design and Verification Conference”.
It is not all that much of a secret that “DVCon” in the past decade could have been dubbed “VCon” if just its technical content were assessed. This is not surprising, since functional verification and HDLs are in the genes of the conference: from “HDLCon” all the way back to its origin as the “VHDL International User’s Forum” (VIUF) and the “VHDL Users’ Group” (VUG), this conference has been largely functional verification-centric. This continues to be the case at least to some degree—many of the accepted papers focused on verification topics, and the UVM Workshop was by far the most attended tutorial in the history of the conference.
Yet, the “D” side of the house was unmistakably present. The North American SystemC User’s Group (NASCUG) held a well attended workshop on DVCon’s Monday morning that featured a keynote by Jim Hogan. This was followed by an equally well-attended tutorial in the afternoon on SystemC TLM 2.0 presented by OSCI. In between these two events was a joint UVM-SystemC “town hall meeting” that attracted around 300 people.
All of this was significant, but the more interesting phenomenon was what might be termed “session attendance patterns”. At this year’s DVCon, I observed significant cross fertilization of the verification and design communities. Specifically, I noticed a number of people I consider to be “SystemVerilog people” sitting in on the SystemC tutorial, and “SystemC people” attending the UVM Workshop. This is not surprising, since the boundary between design and verification languages has become somewhat blurred—witness the inclusion of TLM 2.0 in both SystemC and UVM, and the several calls for a UVM-SystemC at the aforementioned “town hall meeting”.
That said, I plan to seek a more concerted effort by DVCon Steering Committee to amplify this trend, and get more “Design” content, especially more “SystemC Design” content into DVCon 2012. One good starting point might be to promote DVCon’s call for papers through the world-wide network of SystemC Users’ Groups. In addition, perhaps NASCUG could be more integrated into the conference as opposed to being held “in conjunction” with it.
Increased representation from the SystemC Design community at DVCon will occur naturally, but that does not mean that the trend should not be nudged along. The result will be an even better and more diverse event.
Two weeks after DVCon, I found myself at DATE in Grenoble, France. Not having attended the conference in several years, and having heard rumors of DATE’s demise, I approached the conference with a mixture of nostalgia (I remember when DATE was the “European DAC” with all that entails), and trepidation. I had other business to do in Europe and DATE was not my main reason for being there, but I still wondered whether I would be underwhelmed by the DATE goings-on.
The answer is that I was not at all underwhelmed, but, rather, pleasantly surprised. DATE has, I believe/hope, successfully transformed itself from the European DAC into a get-together that more closely resembles ICCAD– a conference with a focus on technical paper and panel discussion sessions, and with a distinct academic flavor. Yes, there was an exhibition floor, but all three major EDA vendors were absent, and the “booths” were about the size of those at DVCon (mostly 10×10 popups).
I must admit that I was initially disappointed in all of this. Then it hit me that I had been to this conference before—it was DAC before it “grew up”, i.e., the DAC of the early 1980s. To mark the contrast, ask yourself when you last heard a group of people at DAC on the exhibition floor hotly discussing one of the papers that been presented in a recently concluded session? I cannot recall when I observed such a thing at DAC in the last decade(s), but it certainly happened multiple times at this year’s DATE. Indeed, I would say that for many of the attendees to whom I spoke, the glimpses of advanced technology that were given during the paper and panel sessions were at least as important as the display of presently-available technology being shown on the exhibition floor.
I have no idea about the future viability of DATE. However, I am pleased that I did get to experience it, even for a short period, this year. It brought me back to a simpler time as a freshly minted Ph.D. when I went to conferences to attend the paper sessions and debate technology trends with the authors and fellow attendees. It was a pleasant time to revisit, albeit all too briefly.