OSCI-Accellera: Cue Mr. Peabody’s WABAC Machine
As most of you will have seen by now, Accellera and OSCI have announced their intention to form a new EDA standards organization that will cover the design flow roughly from Gate-level up through the System-level. This may seem to be a natural move to most people, and one that could easily have happened years ago. If we flip back to what seems to be an very remote time, viz., 2000 when Accellera was created by the merger of Open Verilog International and VHDL International, there seems to have been no good reason why OSCI could not have been a third party to that merger. Or was there?
One interesting tidbit that has been lost in the temporal fog is that at an early Accellera meeting in 2000, a motion was made to urge OSCI to become part of Accellera. This meeting of the “Accellera C Standard Group” was no gathering of wannabes: the list of the attendees confirms that this was a gathering of the C-literate glitterati of the EDA world of the time (yours truly was not present, which just enforces this point). The minutes of the meeting are somewhat opaque, but it is clear that there was a desire on the part of many of the participants to have both OSCI and the OSCI-rival SpecC group join Accellera to help form an organization with a larger scope than the HDL-focused Accellera. It is noted in the minutes that Kevin Kranen, representing OSCI, and Dan Gajski, representing SpecC, would go back to their respective organizations and raise the possibility of joining forces with Accellera.
Clearly, neither OSCI nor SpecC joined Accellera in 2000, and I can find no other evidence that the matter was seriously broached in the next few years. It is interesting to speculate what would have happened had the SpecC group actually joined Accellera. I posit that OSCI would likely have quickly become very irrelevant given the level of corporate backing SpecC would have received from the members of Accellera. However, this did not happen, and SpecC more or less withered away. The question still remains, though, why OSCI did not join Accellera in those early days.
I would argue that there were at least two reasons that this did not happen. First, it is generally forgotten that in 2000 the “Open SystemC Initiative” was not particularly “open”. Rather, OSCI in 2000 was still a group led by Synopsys and CoWare to further the use of Synopsys’ SystemC language. In fact, it was only in 2001 that Synopsys opened up OSCI and gave up control of SystemC and OSCI became the OSCI of today.
Note that this is not an attempt to bash Synopsys—OSCI was a legitimate marketing gambit on their part, and they did in fact relinquish control of SystemC when it became clear that this was best for the industry. Rather, it is to point out that when Accellera was formed, and certainly at the time of the above referenced Accellera meeting, OSCI was not really the sort of open industry group that would have reasonably fit into Accellera.
Moreover, when Synopsys did give up ownership of SystemC at DAC of 2001, momentum quickly built behind OSCI: Cadence and Mentor both joined, along with heavyweights such as Sony, TI, Ericsson, Fujitsu, NEC and others. Indeed, this momentum was so great following the opening of OSCI in 2001 that a merger with Accellera became a non issue. Maybe it should have remaind an issue, but it did not.
Thus, there was sort of “procedural” reason the OSCI did not team with Accellera in the early 2000’s, but there was I believe a harder-to-verify, more “psychological” reason why OSCI and Accellera were an unlikely pair during this early period. To put it bluntly, RTL and System-level people just did not get along very well in the early 2000’s. As evidence, one need only revisit a memorable panel session in 2001 at the International HDL Conference, a predecessor of the current DVCon. This panel was very clearly divided—more accurately “ruptured”—between the Verilog and the SystemC camps, with Simon Davidman on the edge calling attention to what would become SystemVerilog. At the end of this raucous panel, John Cooley held up a cell phone to the audience and asked how many of the attendees planned to use a C-based language to design such a phone in their next project. The answer, of course, was very few—not a surprising result, given that this was a conference devoted to RTL/Gate level design in VHDL or Verilog. Nonetheless, this was taken by the Verilog faction as prima facie evidence of the non-viability of C-based languages going forward.
This panel was not an isolated event, and represented a schism between System-level designers and everyone else. “ESL was coming” and it dutifully showed up every year at DAC in Gary Smith’s forecasts, but most mainstream designers did not take it very seriously. There was a hardy band of designers and industry executives who bucked this trend of mainstream thought—OSCI’s subsequent growth and prospering during the 2000′s is their legacy. Nonetheless, the RTL and Gate-level users (on whom Accellera mostly focused) remained from Mars, while the System-level users, i.e., the OSCI focus group, lived on Venus.
This situation has, of course, radically changed since 2000/2001—planets have collided and the Martians and Venusians now inhabit the same planet. Mainstream design flows include tools and IP that are based on both OSCI and Accellera developed standards. The time has passed in which RTL and below designers can ignore those designing at higher levels of abstraction, just as those designing at higher levels can no longer consider themselves as being “above implementation”. As a direct consequence, now is the right time for the standards bodies covering the Gate through RTL through System-level design/verification flows to come together. This is why unifying Accellera and OSCI just feels—unlike 10 years ago– like such a “no-brainer”.
Hi Stan,
I was wondering if anyone was going to do a SystemC/Accellera retrospective at this inevitable juncture in time. Since my name is mentioned (and not in vain), I’d like to offer one additional rationale for bypassing Accellera at the time – In 1999-2000 Accellera wasn’t willing to standardize the open source reference implementation contributed by Synopsys and CoWare. The powers-that-be within Accellera at that time were only willing to take on the standard and andvance it in a LRM/documentation format. Of course, the only reference for SystemC at that time was the actual reference implemention code and a users guide that went with it via the online download.
In my mind, it’s hard to fault the decision to proceed outside Accellera then, or the decision to merge now. In the early days of OSCI, the single open source reference implementation was powerful unifying factor for tool and model implementation, as well as for innovation. OSCI achieved its goals of refining SystemC 2.0 and 2.1 while creating a true LRM, then taking that LRM forward into the IEEE (Thanks Stan !).
At this point in the time though, the system and RTL worlds are really beginning to blend and blur, with RTL designers thinking at the transaction level and SoC systems designers concerning themselves with how their validated architectures get “refined” into RTL that meets their performance and power goals. The next push really has to be focused on bringing these two worlds willingly together.
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Hi Stan, great reading.
What’s your take on OCP-IP, especially with regards to SystemC, TLM and IP-XACT?
Thanks
Hi Stan,
Good read, thanks. However, my take on the OSCI-Accellera merger is that it has not been a good thing. As you might have heard there are several rumours floating around that Accellera has plans to stop working on the reference simulator. The reason being that Accellera is in the business of defining/improving standards and not spending their limited resources on a free simulator (that is what I was told by a senior EDA employee). Obviously the big 3 EDA vendors are not going to argue against this since the lack of a free (and quite good) reference simulator can only result in more language licenses being sold.
I also like to thank Cadence for OVM-ML and I hope that Synopsys/Mentor will not “prevent” you from creating a UVM version!
I really hope this rumour is not correct and Accellera will continue to support and improve the reference simulator for the foreseeable future, perhaps you can comment on this?
Can I also take this opportunity to thank Cadence for denoting the SCV library, perhaps you could do it again with your current much improved version
Hans.
Good reading !
I hope this move will benefit ESL community. System level modeling/prototyping, UVM/TLM and SC synthesis can bring integrated ESL design and verification methodology.
of course, EDA vendors can provide commercial SC simulators, but that needn’t abandon free reference simulator.