I hope this move will benefit ESL community. System level modeling/prototyping, UVM/TLM and SC synthesis can bring integrated ESL design and verification methodology.

of course, EDA vendors can provide commercial SC simulators, but that needn’t abandon free reference simulator.

Gary

Ada had some neat concepts (e.g. templates), but the most useful such constructs were added to C++ before too long (although getting templates “right” has been a long struggle). On the other hand, the super-strong typing and syntax-intensive aspects of Ada were essentially rejected by the programming community (in large part probably because of the difficulty of keeping track of all those syntax and type conversion requirements while coding). The true remaining legacy of Ada, IMO, is the continuing argument between Verilog and VHDL programmers about which is superior, since VHDL tapped heavily from Ada typing and syntax (not surprising as it was a DOD standard).

Interestingly enough, even C/C++’s relatively relaxed typing requirements are now considered too heavy for many tasks such as web programming where we’ve seen the rising of languages such as perl, php, python, ruby (lightly or dynamically typed languages). But I wouldn’t recommend these for embedded programming

Good read, thanks. However, my take on the OSCI-Accellera merger is that it has not been a good thing. As you might have heard there are several rumours floating around that Accellera has plans to stop working on the reference simulator. The reason being that Accellera is in the business of defining/improving standards and not spending their limited resources on a free simulator (that is what I was told by a senior EDA employee). Obviously the big 3 EDA vendors are not going to argue against this since the lack of a free (and quite good) reference simulator can only result in more language licenses being sold.
I really hope this rumour is not correct and Accellera will continue to support and improve the reference simulator for the foreseeable future, perhaps you can comment on this?
Can I also take this opportunity to thank Cadence for denoting the SCV library, perhaps you could do it again with your current much improved version I also like to thank Cadence for OVM-ML and I hope that Synopsys/Mentor will not “prevent” you from creating a UVM version!

Hans.

I was wondering if anyone was going to do a SystemC/Accellera retrospective at this inevitable juncture in time. Since my name is mentioned (and not in vain), I’d like to offer one additional rationale for bypassing Accellera at the time – In 1999-2000 Accellera wasn’t willing to standardize the open source reference implementation contributed by Synopsys and CoWare. The powers-that-be within Accellera at that time were only willing to take on the standard and andvance it in a LRM/documentation format. Of course, the only reference for SystemC at that time was the actual reference implemention code and a users guide that went with it via the online download.

In my mind, it’s hard to fault the decision to proceed outside Accellera then, or the decision to merge now. In the early days of OSCI, the single open source reference implementation was powerful unifying factor for tool and model implementation, as well as for innovation. OSCI achieved its goals of refining SystemC 2.0 and 2.1 while creating a true LRM, then taking that LRM forward into the IEEE (Thanks Stan !).

At this point in the time though, the system and RTL worlds are really beginning to blend and blur, with RTL designers thinking at the transaction level and SoC systems designers concerning themselves with how their validated architectures get “refined” into RTL that meets their performance and power goals. The next push really has to be focused on bringing these two worlds willingly together.

TSCUG Chair, Alan Su