San Francisco—It’s no surprise that different sections of the electronics supply chain see the low power challenge from different perspectives. But the similarities and differences are changing as the low power problem becomes the driving force behind today’s mobile devices.

At the recent Globalpress event, Portable Design’s editor in chief John Donovan moderated a panel on low power: “Portable Power Management – Dodging Moore’s Law?”

Donovan said low-power design faced a turning point in 2008, thanks to three converging issues: The growth of portal devices, power consumption costs at data centers, and changes in process technology, which are the result of Moore’s Law. A 45nm chip contains more than 400 million transistors, which equals a lot of power generation and dissipation.

Wally Rhines, CEO of Mentor Graphics, talked about system-level power issues in a speech at the event. The focus of this panel was at the chip level, which has a 20% to 50% impact on the overall board-package lever power budget.

One Theme – Differing Views

The first question addressed by panelists involved emerging trends in low power designs.

Richard Zarr, chief Powerwise technologist at National Semiconductor, said a new generation of user interface technology combined with the consumer’s desire for higher bandwidth content will drive the need for increased local processing power in mobile devices.

User interface technology has come a long way since 1983, when Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone (see Figure 1). This phone boasted an alpha numeric LED screen that was a single row in length. Since that time, phones and other mobile devices have gotten smaller while the displays have gotten larger. The larger, higher resolution displays are needed, in part, to support the customer’s desire for multimedia data such as MP3 music and video streams.

“By 2014, Cisco forecasts that 64% of mobile traffic will be video,” said Zarr, adding that other high-bandwidth applications would include online gaming, where cloud computing will move most of the intensive processing tasks to the server while pushing video to the personal mobile devices. All of this will increase the need for local and remote low processing technology.

Figure 1: In 1983, Motorola introduced the DynaTAC 8000X – the first FCC approved mobile phone. (courtesy of Wikipedia)

Instead of the typical power-to-clock equation for chip power, Zarr used the energy dissipation equation to show how energy (power given a certain amount of delta time) is really a function of process and temperature variations, plus aging and the clock frequencies of the device. This lead-in was tailored to National’s Powerwise Adaptive Voltage Scaling (AVS) products, which addresses – you guessed it – process and temperature variation, plus frequency via voltage scaling. AVS touts energy efficiency by eliminating the need to pre-identify voltage levels via voltage lookup tables for various performances modes.

Next up was Bruno Kranzen, Ultra-Portable product line director for Fairchild Semiconductor. He built upon Rhines’ keynote comment that energy storage technology innovation was at a standstill. According to Kranzen, this means power innovation has to accomplish more while using the same power afforded by today’s batteries. That “more” includes 5.0 GBits/data rate support for USB 3.0 interfaces that are so common on today’s mobile devices. It also means support for 10 megapixel image sensors in today’s cameras, multicore processors, 3D MEMS sensors for touch-screen displays and 8 RF bands, to name only a few of the power consuming technology requirements.

All of these power-intensive features must be met with battery technology that has improved at a snail’s pace, as Rhines pointed out in his keynote presentation. He observed that innovation in lithium-ion battery capacity had essentially stalled, with capacity improvement increasing by less than 5% per year (Figure 2). So how can the electronics industry meet the demand for increased feature sets that use today’s battery technology?

Figure 2: Innovation in lithium-ion battery capacity has stalled. (courtesy of Mentor Graphics)

Kranzen answered that question by taking a system view. He explained that while Fairchild is a chip company, it is collaborating with partners in both the operating system and applications space. He emphasized that merely making energy-efficient chips is not enough. Instead, software designers must be engaged to meet the demands of low-power system. Fairchild’s Mobile Power Systems platform is one way to achieve this end, by utilizing power management hardware components that are tightly integrated with the operating systems and even applications that run on a mobile device.

The final panelist was Pravin Madhani, general manager of the Place and Route Division at Mentor Graphics, who represented the EDA side of the low power equation. Madhani spoke in unison with the other panelists in terms of the need for a systems view for the design of low-power devices. Specifically, Madhani defined the system process as starting with an architectural-level specification that takes into account PCB, package and component-level design. Each step in this process affords different opportunities to impact the overall power budget for a device.

Taken together, the total impact can be significant, with potential power reductions of more than 50%. Mentor’s low-power platform addresses each of these design stages, from optimal hardware architectural design through power integrity and predictability at the PCB level through the capture of the designer’s power intent at the component level via the Unified Power Format (UPF).

Devil is in the details

So what are the real-world applications of these ideas?

Mentor’s Madhani shared his experience with a recent multicore design project in which a graphics company couldn’t meet power and performance requirements for two graphic engines on one core. The solution required moving to a smaller process geometry, in this case 45nm, which afforded significant power savings but with slightly lower performance. The key in this design was clearly understanding the tradeoffs of each scenario, as well as being able to simulate and verify all of the hundreds of operation modes for the chip.

Fairchild’s Kranzen challenged the drive toward increasing number of cores. He said transistor leakage was the culprit, which drastically increased the level of static power drain for multicore designs at the low process nodes. Leakage current is the result of the small amount of current that continues to flow even when the transistor is off. This challenge must be address by device-level physicists and material ngineers.

Conversely, having just a single core is often impractical, since that core must run so fast to perform all of the processor-related tasks that it consumes unacceptable amounts of power. So designers must find the “sweet spot,” which is the optimal number of cores needed to balance the power-performance constraints of their design. One solution is to turn-off unneeded cores. Such an approach requires close operation between the cores and the systems operating system, explained Kranzen. Cores could be turned off by the software kernel, but that activity must be closely coordinated with the Real Time Operating System (RTOS).

National Semiconductor’s Zarr agreed that part of the low power problem must be solved at the transistor device level, probably with improvements with high K dielectric materials and designs. But the bigger challenge is to clearly understand the goal, the intention of a given design. He cautioned that just “throwing transistors at the problem,” as with multicore and/or lower process node technology, is not the best approach. Instead, a top-down architectural solution is needed. One outcome of such an approach would be to divide different blocks of system functionality into different voltage islands to better manage the power usage of the system.

So is the ESL-to-RTL design problem still the biggest challenge for low-power design teams? Madhani believes that most people have a better handle now on low power design, thanks to improved architectural power modeling and better tools to verify the numerous power modes for a given operational scenario.

Kranzen stressed the need to run software models, as well. These models would execute the drivers, OS and application-level code to provide a gauge of related power consumption. Running both hardware and software simulation or co-simulation would provide a system-level view of the overall system power usage.

Finally, Zarr believes the best way to address the top-to-bottom low power design is with an energy tax on the operating system, in other words, placing a real emphasis on energy management of the entire hardware-software system.

The bottom line: The power problem is too big for a point solution. Only a system-level approach that incorporates the co-simulation, co-design and co-verification of both hardware and software will be sufficient to meet the demands of lower-power electronics. This is hardly a revelation, but the growing consensus by EDA and semiconductor companies of the importance of software design in the hardware equation looks encouraging.

Tags: Fairchild Semiconductor, GlobalPress, Low-Power Design, Mentor Graphics, National Semiconductor

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