LPD: Is communication more open these days between the various parties involved in the design-to-manufacturing flow?

Quan: It’s improved greatly in the past couple years. Traditionally, for people doing digital designs, you needed the SPICE model. That has been available and there is no issue there, except that there is a lot more information than before when you go down to 45, 32 and 28 nanometers. And most of the digital designs will need to have access to the timing models for standard cells and memories. Those are pretty available. The challenge is when you go to a new process node, before the design can take advantage of that the infrastructure has to be available. We have to re-work with the IP vendors so companies can start building RAM—even though the process may change. We still need to go to pre-production so customers can start using it.  That’s the part that’s more challenging.  The actual mechanism of transferring data is not an issue anymore.

Kapusta: We’re on a process technology that’s somewhat unique, so we’re forced to co-develop the process with the foundry, which in our case is UMC. We’re working on 65nm embedded flash with UMC to give us the best technology for our FPGA families. We have our own process development engineers working with UMC, we’re doing test chips together and we’re tweaking the process together. By the time we finally tape out we’ve seen a couple runs of silicon, we understand what we’re doing, and we’re working together to get it right from the very beginning as opposed to waiting for a foundry to create a process node and jump onto that. We’re co-developing the process node.

Buric: That’s been a trend for several process nodes. Foundries are developing application-specific processes. With TSMC, when you go up to 65nm and 90nm, there is optimization for mixed-signal and ultra-low power processes, and even CIS (CMOS image sensor) processes. The idea of a general-purpose process serves a smaller and smaller market segment. More and more you will see applications that drive huge volumes will also be able to drive modifications to the process.

 

LPD: Are the foundries seeing that, as well?

Quan: Yes, that definitely is the trend. When you go down to 40, 32 and 22 nanometers, there will be mostly SoC designs. You have fewer of those, but the volume is larger and those customers have very specific requirements for their products to be competitive. Those will be more specialized processes. Last year we introduced the open innovation platform, which allows collaboration to go much deeper and much earlier in the process. One of the main features is design co-optimization so that each side can take full advantage of what’s available on the other side. We can trim 20% to 30% of leakage power even before tapeout. That was not possible before when everything was separate.

 

LPD: Is the concern low power or performance—or both?

Kapusta: For us it’s all about low power. Our customer base is not performance-driven. We’ve already surpassed all of their performance needs at the current node. When we go to the next node it’s all about getting more and more power out of the system, not making it go 10 times faster.

Quan: For the computer guys, it’s still all about performance.

 

LPD: That’s the plug-in computers, though, right? Not the notebooks?

Quan: Yes, the servers. Even for laptops, it’s hard to say you want less performance. Intel now has a 2GHz version of the Atom that only takes 1 watt. Communication and consumer are all about low power.

Buric: Atom is a good example. Even where there is a need for performance, those designs are built with low power in mind. If you just said run it at the highest performance possible with no concern for power, it would be in a ceramic package and require liquid nitrogen to cool it down. With everything we have seen at 40nm, they design for performance, but they also design for low power because it is cost-effective. With packaging costs and a huge number of transistors, you cannot afford to make those designs if they are not low power.

 

LPD: In some designs, the clock speeds on individual cores aren’t getting faster. Are we getting to the point where adoption of new nodes will slow down?

Kapusta: We’re not even talking about 32nm. We’re strategically behind the leading edge because we don’t need that performance and we can get the power we need one or two nodes back. We’re at 65nm now.

Quan: For mixed-signal RF and analog, most designs don’t go that fast. With the 65nm general-purpose process, you can push the 60GHz transceiver. That’s the probably the highest frequency we push in any market. But for computing and graphics, the trend is still there and going down. We had a lot of activity at 40nm and 28nm. Traditionally there were bell curves with adoption and maturation. It probably will get flatter, though, as time goes on. The highest revenue producer for us is the 90nm and 65nm nodes. More than 60% of our revenue is there. That’s the sweet spot, and it’s where most of the activity will occur for some time.

Kapusta: Even at 130nm when we came out with our ProASIC 3, it was low power but it wasn’t that low power. It was still higher performance. When we came out with the Igloo line on the same node, we pushed the equation further into the power side. That family is more popular than the ProASIC 3. It’s basically the same architecture but lower power vs. higher performance.

 

LPD: Will Igloo ever fit into embedded applications?

Kapusta: Right now you can embed an ARM soft core into the chip.

 

LPD: How about the other way around—embedding Igloo into other chips?

Kapusta: We have had a few conversations about that. Some customers are trying to figure out how to embed it into other processors, but so far, no.

 

LPD: On a different subject, is the trend toward stacked die?

Quan: Stacked die is a different term for 3D chips. It’s already there for the memory companies. Most of the connections are still through bonding, but one technology that is still in the works is through-silicon vias. You actually drill holes through the wafer and fill it with copper. There are still a lot of issues to solve, but the technology is there and the prototypes are done. Certainly timing has to be worked out, but the real issue is how to distribute the thermal crests of these die and how these conducting columns are supposed to be behave. The good news is that silicon is not a bad thermal dissipator. The challenge is when you stack things against each other—a processor next to RAM next to analog. You need to analyze what gets affected most.

 

LPD: Is it lower power when you stack a die, though?

Quan: If there’s any change, it’s the power dissipation in the interconnect. If you have four cores and it’s flat, the signal needs to travel across these connections on a narrower line versus a fat copper interconnect between die.

Buric: A big problem to solve is how to test for a good die before you start stacking things. Your yield changes when you add these interconnects. The problems multiply.

Kapusta: I think you can get lower power by stacking. If you look at two functions you can choose the lowest power process implementation for each of these two functions separately and stack them together versus making a compromise of integrating them on a less optimal process. If you’re looking at 65nm flash and want to stack it with some memory, you can choose a 40nm SRAM process and get the best of both worlds. If you want to implement it on a 65nm flash, you make compromises. You can make lower-power SIPs (systems in package) by taking the best of each element you’re trying to stack.

 

LPD: Is there a way of manufacturing these so the cores are not the same?

Kapusta: When you think of multicore, you’re thinking high performance. We have customers implementing multiple soft cores on a fabric. As we start embedding hard cores into our FPGA, people will have the opportunity to use hard cores and soft cores and build a system based on the processing chunks they need rather than being forced into some choice.

Quan: There are two trends. One is a more general-purpose platform where the cores will be different, but each one has the same purpose such as processing or graphics.  The other thing we see is where each core is custom. They’re all small, very low power, but there may be 500 or 1,000 of them. Those are for very specific purposes like simulation or processing of security applications. Instead of using a general-purpose application where you waste a lot of power, you make the cores very specific and very low power. Each of the cores is maybe 100^th of the size of a standard core in terms of size and power.