Power Analysis At A Different Step In The Design Chain
Pallab Chatterjee & Ed Sperling
A French startup has a new angle on power analysis, targeting the solution to the design task of energy in an electronic system as a systematic binding element rather than just a static parametric element.
The founders bring experience from the wireless, semiconductor and software arenas to the task of “energy management” for electronic design. This takes the form of both power and thermal design analysis and planning. Their methodology is based around a proprietary product they have created called ACEplorer, which is an Abstract Concept of Energy exploration tool.”
Basically, the flow requires the designer only to have a concept of the power state flow for their design (on state, off state, sleep state, power down state, video off state, etc.). They do not have to have any detailed RTL. Using a VCD interface, and a traditional XML data format, a designer can describe the models of the IP blocks of the system and the design functions for each of the power states and create an appropriate UPF model that incorporates all relevant energy information. This includes active power, passive power, thermal power and the power associated with the drivers connected to the external load/package/cable. The resulting compact models are then appropriately temperature modified and used in power simulations to determine the device level power performance and spectrum of the product.
For new devices, high-level XML-based traditional models are used and input, and the new UPF model are created. The methodology can be also used for characterization of existing devices as well as for migration and spec creation for derivative IP. For the derivative flows (typically on similar technologies such as a G process to an L process) the flow would be to create a detailed characterization model, run the power simulation (SPICE level), then modify the values to in the model to reach the new goal and create the spec for the new block RTL.
Unlike some of the other tools on the market, as the models are high level, and work up at the power state, it does not matter the if the blocks are digital, memory, I/O, analog, display, board level, power regulation or SIP. This method allows for the detection of thermal run-away, prior to it being a disruptive event in an incompatible set of state changes.
Started as a spinoff from the Grenoble ecosystem project, which has since evolved largely into an STMicro ecosystem, DOCEA founder and CEO Ghislain Kaiser said the real advantage is to be able to do power analysis that takes into account more parameters up front to make estimates more accurate.
“What these tools allow you to do is make estimates that are more accurate and explore an architecture that will be optimum,” said Ghislain. “That decreases the need for
additional margin.”
As it is a new paradigm, it will be interesting to watch and see the adoption cycle in the mainstream semiconductor industry. DOCEA rolled out the first version of its product at the end of last year and says it has several customers already and has received positive adoption of the methodology from several key clients in the portable design space.
Tags: DOCEA, Low-Power Design, power analysis