Variable Speed Processing
By Ed Sperling
If you can’t get the application software to run on multiple processors, then at least you can get multiple processors to run the software.
That’s the latest thinking in multicore design, and the potential for saving power is huge. Instead of running a processor core that’s either on or off, it allows different cores to work almost like a variable speed motor. When the power is needed, more cores can be turned on to help with the processing. When it’s not, those cores can sleep.
If this sounds familiar, it should. The reasons for doing it are different, but this is largely the same tack taken by companies like Intel back in the 1990s with the 387 and 487 co-processors. The difference was those co-processors were added to boost performance in mathematical functions rather than actually reduce power. The 387 and 487 were always on, and always drawing current.
Fast forward a couple decades and that same approach is being applied in the multicore world. It’s impossible to keep cranking up the processor clock speed without burning up the chip, so more cores are being added. The initial thinking was that the software developers would be able to get more applications running on multiple cores, and while that works for many commercial and scientific applications it doesn’t work in the consumer or personal computing world.
But the processing power can be extended without actually parsing the application across those cores. That helps explain Intel’s Turbo Mode boost, which will be released in the next major release of its architecture. And it helps explain how other companies are starting to address this problem.
Subramanyam Dronamraju, director of business development for software products in Freescale’s Networking & Multimedia Group, said the current approach is to match performance in a VPN router, for example, to whether an application is fully loaded and using more tunnels or whether it’s using a relatively light load.
“What we’re addressing with this approach is data path acceleration,” Dronamraju said. “We’re mixing and matching symmetrical and asymmetrical multiprocessing. It can run on one core, two cores or four cores. And that flexibility isn’t just in the processing. If you have multiple images instead of a single image, you need more memory. With asymmetrical flow management, you can direct the flow into cores.”
Those cores also can run at different frequencies, which increases the flexibility of the design and the potential for power savings even more. Freescale declined to comment on any new products, but sources familiar with the company’s road map said that if a core is underutilized at any point, the frequency will be lowered dynamically. Frequency cannot be scaled anymore, but adding more cores and scaling the power applied to those cores can allow developers to remain within a defined power budget.
End market mandates
This type of thinking is being driven as much from the end customer as at the system-level design. The emphasis in industries such as data centers, which currently consume about 2% of the nation’s power, for example, is on everything green. Fearing a crackdown by the government or utilities, many are working hard to develop much more efficient approaches to computing.
At every single layer of the analysis, the old paradigm used to be the cheapest, most mass-produced equipment,” said Anthony Wanger, president of i/o Data Centers in Phoenix. “For the first time, Intel and AMD are competing over who’s the most efficient. Hard drives also use a lot of electricity, but electrical energy tends to be more efficient than mechanical energy. This isn’t happening just at the data center layer. At the device layer people are competing on efficiency. If you take that kind of server and put it into a 2009 data center, your work per kilowatt increases dramatically because you’re attacking all of these things, not just one of them.”
In the consumer market, the key driver these days is battery life. Most of the new netbooks are being advertised based upon battery life first, with other features a distant second. The initial success of the netbook, in fact, is a sign of just how far down on the list performance has dropped compared to power.
But adding variable-speed processing, which is roughly the equivalent of accelerators in various states of on, sleep or deep sleep, could bridge these two worlds quite effectively. Intel, Freescale, Texas Instruments, ARM and others are exploring these kinds of tradeoffs. And in the future, this could provide some interesting workarounds to some thorny problems in multicore software programming without a power penalty.
Tags: ARM, Freescale, Intel, Texas Instruments
June 11th, 2009 at 3:58 pm
Hi Ed,
Nice article. There is definitely a trend in this direction as the industry moves into multicore solutions. But, there is an aspect of multicore design that your article overlooks.
That is, you mention that variations of clock frequency and power-on state across a multicore array are being used. But, your article, while not stating it precisely, seems to presume that all the processors are of the same type. On the other hand, in the world where energy consumption really matters (battery-powered consumer electronics devices, for example), even the specific architecture of the various processors are different – i.e. one (or two) for application-level processing (e.g. GUI’s, games, and the like), but then other specialized processors (generally known as ASIPs) for specific functions (e.g. audio, video, image processing, wireless communication, security, etc.) Just take a look at any SoC platform in this space (e.g. Snapdragon, OMAP, others), and you will see application-specific co-processors/accelerators throughout the design. While these have often been fixed function RTL, they are more and more being built as full processors in their own right. By adding special instructions and parallelism to the architecture of a processor, the computational throughput and power efficiency of an ASIP (for the algorithms of interest, that is) increases to a point where it is a viable alternative to the fixed-function approach. And, the fact that the resultant design is programmable enables a whole new design paradigm to address design complexity and moving requirements and standards.
If this is interesting, try googling “ASIPs in SoCs” to see more on this topic, or contact me directly to discuss.
cheers,
- stevec