Advanced Clock Gating Techniques In Catapult C Synthesis
This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design methodologies enable power consumption optimization opportunities unreachable for traditional RTL design methods. Learn how Catapult C Synthesis can help you deliver designs with minimum power dissipation using its several power optimization methods and power-aware architecture exploration capabilities. To download the paper, click here.
Tags: Catapult C, Clock Gating, Mentor Graphics, Synthesis







