By John Blyler

This week was a busy time in the low-power embedded space, as both ARM and Intel confirmed the importance of the market to their long-term technology strategies. Let’s start with the first announcement which came from Intel.

Intel Re-enters Market with High-End SoC

Intel recently disclosed more information about its next-generation Xeon® processors – codenamed “Jasper Forest.” Due out early next year, Jasper Forest is a SoC version of the Nehalem microarchitecture, including a 1, 2, or 4 core CPU plus an integrated PCI-e controller.

 This tightly integrated, lower power and smaller foot print chip will be well suited for specific applications in the embedded communications and storage markets – a market that Intel left when it sold the network portion of the xScale product line.

Intel’s embedded market strategy is compelling, with its Atom processors aimed at the netbook, in-vehicle infotainment and industrial automation applications while the Nehalem-based processor (codenamed “Jasper Forest”) will be aimed at high-end embedded and storage applications.

Performance does not appear to suffer much from the lower power consumption of Jasper Forest. In fact, Intel’s Nehalem-based microarchitecture – or the way a given instruction set architecture (ISA) is implementation on a specific processor – combined with the benefits of multiple cores makes the Jasper Forest a good candidate for traditional Digital Signal Processing (DSP) and data plane applications.

Both DSP and data plane – which controls how network data packets are forwarded – functions are critical elements in communication and storage markets. In the past, such functions as signal processing and network control could only be accomplished by high-end, dedicated chips – ASICs or ASSPs. Now, thanks to the power afforded by multiple cores on a single chip, these complex functions are within the reach of such processors as the Nehalem. As Stephen Price, director of marketing for Intel’s Performance Platform Division within the Embedded Communications Group (ECG), explains: “Customers are looking to take advantage of the number of cores and significant processing power per core to consolidate some of the workloads that used to run on DSPs or network processors back onto native Intel Architectures (IA) such as Jasper Forest.”

One specific area where lots of available processing MIPS make sense is in third and fourth generation (3G and 4G) telecommunication networks. Price notes that one scenario would be to move Layer 1 (PHY Layer) baseband processing and higher layer functions (Layer 2 MAC) of the telecommunications 3G Long Term Evolution (LTE) from traditional DSPs to the multicore Nehalem, while also running their control and some portion of the data plane functionality – all on the Jasper Forest platform.

In the past, FPGAs or DSPs have been used to handle the physical layer baseband processing, leaving the higher-level (Layer 2) functions to be handled by a more cost-effective general processor, which can also be used for “back haul” connectivity functions of the data plane. What Jasper Forest offers is to combine all these functions unto a single chip, for such specific applications as a Radio Network Controller (RNC), which must manage both air and ground channels.

Traditional DSP designers may balk at using a general-purpose processor – no matter how powerful – for handling data processing. Price agrees, but notes that many network customers are interested in used blade servers as common building blocks in their system. Blade server platforms are the market for which existing Nehalem-based Xeon chips hold a significant market share. “These customers would like to multipurpose their existing systems. How can they use one for a software router, then re-purpose it for an RNC?” Jasper Forest - the embedded version of server-grade Nehalem – may provide a scalable way to achieve that re-purposing.

ARM moves up in performance

ARM, meanwhile, introduced Osprey, a 2 GHz capable Cortex-A9 dual core processor implementation, which is targeted at low-power processing in the consumer and enterprise space. This technology will be implemented on two Cortex-A9 MPCore hard macros for the TSMC 40nm-G process. One hard macro implementation will be speed-optimzed for applications running at speeds greater than 2GHz. The other implementation if designed for the low power embedded market.

ARM is the dominant player in the processing world of all things mobile. According to Nandan Nayampally, director of CPU marketing, ARM shipped about 4 billion cores last year. Surprisingly, well over a quarter of those were cores for non-mobile applications, which means that ARM has made good strides into the higher-end, non-mobile marketplace that includes digital TVs, set-top boxes, digital home entertainment, enterprise printing and computing and base-station infrastructure.

That’s why the announcement of Osprey is seen by some as a challenger to Intel’s embedded Atom processor. Nandan confirms the perception that, “In the past, ARM cores have not generally been seen on same performance level as PowerPC, MIPS or some proprietary in-house processor architectures.”

But in the embedded space, performance must be balanced with other factors such as integration experience and supporting ecosystem. “The history of SoC integration for ARM cores goes back 20 years. That represents quite a learning curve of design experience,” explains Nandan. On the manufacturing side of the process, ARM has built chips with more than 200 different manufacturers.

Complementing this design and integration experience in the embedded market is the Osprey, which adds dual-core embedded processing into the equation. This leaves only Intel’s Atom as a single core player – for the moment, at any rate. For reference, the predecessor to the Cortex-A9 is the A8, which was introduced about 4 years ago and is found in products like the Palm Pre, Archos 5 Internet tablet and netbooks (demonstrated at CES with shipments starting soon).

The Osprey Cortex A9 implementation is based upon the latest generation of ARM instruction set. It supports a number of applications, including full web browsing, digital rights management programs, multimedia applications and acceleration for Java and .Net enhancements.

Because power is the critical parameter in most embedded applications, the power difference between these two core offerings is important. The power optimized hard macro requires 0.5 watts at 800 MHz, while the high-performance option requires 1.9 w at 2GHz (see Figure 2).

Figure 2: Comparison of Osprey’s two implementations – one for speed, the other for low power.

How does that stack up against the competition, in terms of performance? According to ARM, “the worst-case performance of the Cortex-A9 power optimized macro exceeds today’s netbooks with 5x less power consumption.” This is based upon results derived from running on various silicon platforms that have shown Coremark scales directly with core frequency.

ARM’s dual-core technology should extend the company’s reach upward into the high performance embedded market, a space dominated by Intel. And in the end, of course, the consumers should be the big winners.

Tags: ARM, Intel

This entry was posted on Thursday, September 17th, 2009 at 11:52 am and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.