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	<title>Comments on: Considerations For Choosing The Right Low-Power Tools</title>
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	<link>http://chipdesignmag.com/lpd/blog/2009/10/15/considerations-for-choosing-the-right-low-power-tools/</link>
	<description>Making Semiconductor Architectures More Efficient</description>
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		<title>By: Yonghao Chen</title>
		<link>http://chipdesignmag.com/lpd/blog/2009/10/15/considerations-for-choosing-the-right-low-power-tools/comment-page-1/#comment-322</link>
		<dc:creator>Yonghao Chen</dc:creator>
		<pubDate>Sun, 01 Nov 2009 00:09:44 +0000</pubDate>
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		<description>Thanks for hightligting the Cadence low power solution. However, you missed one important tool in the flow: the Incisive Simulator for low power verification. The Incisive Simulator has a range of natively built capabilities for simulating and debugging low power designs. These capabilities have enbaled numerous customers to successfully verify their low power designs with various design techniques, including power off, multi-voltage scaling, and etc.</description>
		<content:encoded><![CDATA[<p>Thanks for hightligting the Cadence low power solution. However, you missed one important tool in the flow: the Incisive Simulator for low power verification. The Incisive Simulator has a range of natively built capabilities for simulating and debugging low power designs. These capabilities have enbaled numerous customers to successfully verify their low power designs with various design techniques, including power off, multi-voltage scaling, and etc.</p>
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		<title>By: Yatin Trivedi</title>
		<link>http://chipdesignmag.com/lpd/blog/2009/10/15/considerations-for-choosing-the-right-low-power-tools/comment-page-1/#comment-294</link>
		<dc:creator>Yatin Trivedi</dc:creator>
		<pubDate>Tue, 20 Oct 2009 19:39:19 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/lpd/?p=917#comment-294</guid>
		<description>Cheryl, quite a comprehensive article with one significant omission reagrding information on standard for low power format. IEEE 1801 has been ratified by the IEEE Standards Association board since May 2009. This standard is based on Accellera&#039;s UPF low power standard. It included several enhancements and some corrections to make it appropraite for broad usage by design, verification and analysis engineers. The 1801 working group received PAR approval recently to continue further work. As a long time participant in this group, I hope many of your readers will join the working group and benefit from this effort.</description>
		<content:encoded><![CDATA[<p>Cheryl, quite a comprehensive article with one significant omission reagrding information on standard for low power format. IEEE 1801 has been ratified by the IEEE Standards Association board since May 2009. This standard is based on Accellera&#8217;s UPF low power standard. It included several enhancements and some corrections to make it appropraite for broad usage by design, verification and analysis engineers. The 1801 working group received PAR approval recently to continue further work. As a long time participant in this group, I hope many of your readers will join the working group and benefit from this effort.</p>
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		<title>By: Sudhakar Jilla</title>
		<link>http://chipdesignmag.com/lpd/blog/2009/10/15/considerations-for-choosing-the-right-low-power-tools/comment-page-1/#comment-283</link>
		<dc:creator>Sudhakar Jilla</dc:creator>
		<pubDate>Sat, 17 Oct 2009 00:41:21 +0000</pubDate>
		<guid isPermaLink="false">http://chipdesignmag.com/lpd/?p=917#comment-283</guid>
		<description>Good article. I know your list of design tool options isn&#039;t meant to be exhaustive, but you missed a major player! Mentor has a unique low-power IC implementation solution that targets advanced SoCs designed for the smallest and most power-efficient process technologies. The Olympus-SoC place and route solution is being used by some of the most advanced wireless chip design firms in the world. It has won multiple industry awards and is getting great reviews from designers who have saved substantial time on low-power tape-outs. We are in the UPF camp, fully supporting multi-voltage methodologies, and we are particularly proud of our unique multi-mode multi-corner CTS engine. Your readers should be aware that Mentor has solutions that address power at every stage in the design flow – from ESL through functional verification, physical implementation and verification and test. They can get more information at the Mentor Low Power Solution website at http://www.mentor.com/solutions/low-power/”</description>
		<content:encoded><![CDATA[<p>Good article. I know your list of design tool options isn&#8217;t meant to be exhaustive, but you missed a major player! Mentor has a unique low-power IC implementation solution that targets advanced SoCs designed for the smallest and most power-efficient process technologies. The Olympus-SoC place and route solution is being used by some of the most advanced wireless chip design firms in the world. It has won multiple industry awards and is getting great reviews from designers who have saved substantial time on low-power tape-outs. We are in the UPF camp, fully supporting multi-voltage methodologies, and we are particularly proud of our unique multi-mode multi-corner CTS engine. Your readers should be aware that Mentor has solutions that address power at every stage in the design flow – from ESL through functional verification, physical implementation and verification and test. They can get more information at the Mentor Low Power Solution website at <a href="http://www.mentor.com/solutions/low-power/”" rel="nofollow">http://www.mentor.com/solutions/low-power/”</a></p>
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