By Ed Sperling

It was a good week for the low-power world. Synopsys introduced low-power USB 2.0 PHY IP for 28nm processes, which uses 30% less area than previous incarnations. By the way, most foundries and chipmakers believe 32/28nm is a slam-dunk process node/half node. Some have even seen the green light at 22nm, but at 20nm all bets are off. And it looks like low power will be part of the equation at all future nodes.

Actel’s numbers showed the benefits of low power, as well. Q3 revenue was up 4.5% from the previous quarter to $47.2 million—probably the best gauge for digging out of the downturn—and net income rolled firmly into positive turf vs. the previous quarter (as well as the comparable quarter in 2008). These are the kinds of earnings reports everyone likes to see, with the arrow pointed up and to the right of the chart.

Cadence reported its Q3 numbers, which still showed a bottom-line loss, but a much, much smaller one. The loss in Q3 2008 was $171 million. That loss shrank to $14 million in 2009 even though revenues were down $16 million. The company is expecting another loss this quarter as it solidifies its product lineup and gets back on its feet.

Mentor Graphics introduced the latest version of its Open Verification Methodology (OVM) Cookbook for functional verification. Written by Mark Glasser, methodology architect at Mentor, it should at least warrant a response from the Verification Methodology Manual (VMM) crowd, whose last foray into this space was a book on VMM for Low Power. We know all the standards groups will attack us for even bringing up this stuff because there has been a lot of work on interoperability between the two environments, but don’t tell that to the verification engineers who firmly believe in one or the other.

Virage Logic teamed up with MIPS and Open-Silicon to create high-performance test chips at 65nm running at 1.1GHz. They’re also working on 40nm versions that can run at 2.5GHz. What’s interesting for us speed junkies is these also run at much lower power than previous versions of these kinds of chips.

Mentor was touting its analog/mixed signal simulators for verifying wireless hearing aid chips. We’re expecting to see more of these kinds of announcements as chip developers start putting more functionality onto a single chip at advanced process nodes. What else can you do with all that real estate? This is like a nano version of the Oklahoma land grab.

Synopsys recorded a couple of market wins, as well. Nvidia adopted Synopsys’ Yield Explorer technology, which is a significant pre-manufacturing win. Nvidia is calling it DFx, as in design for yield, manufacturability, test, or whatever else might fit in as the third word in that acronym. In addition, Juniper Networks signed a multi-year deal to expand its use of Synopsys tools.

Cadence and SMIC unveiled a 65nm low-power reference flow. The big question in the foundry business is when SMIC will get to 40nm. The company appears to have stalled at 65.

Tags: Actel, Cadence, Mentor Graphics, SMIC, Synopsys, Virage Logic

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