Blog Review: Nov. 4
By Ed Sperling
It was just a matter of time until power and heat became regular parts of the blogosphere. The discussion started at 90nm, became more serious at 65nm, and at 45nm and below it’s becoming chip engineer’s worst fear–sort of like Jason Goes To Hell meets a synthesis training video.
There are all sorts of tricks that can be done, although none without consequences. Synopsys’ Godwin Maben addresses how to use isolation cells. Unless you’re retiring next week, you might want to take a look at this.
Mentor’s John Wilson moves the discussion into a very warm place—and how to make it cooler. Heat is a problem in all chips these days, and the word he uses to describe it is advection, defined as the horizontal transfer of heat by air. That should get you thinking, considering the technology we’re hearing about most often these days is through-silicon vias, which are vertical.
Virage Logic’s Hezi Saar asks whether DisplayPort will become more popular than HDMI. That would certainly help the replacement TV market, which could use help in driving new sales now that everyone is converting their old CRTs to flat panels. But given the fact that this TV transition is still underway, it may take awhile. Still, it also might be a marketing edge for companies. TVs are now in a competitive war over the number of HDMI inputs, which is really weird when you consider that most consumers don’t even know what HDMI stands for.
Synopsys’ Frank Schirrmeister takes a look at the value of constraints in high-level synthesis—and where the proper middle ground is between engineer and tool. There is no simple answer here, but at least two factors that will affect this discussion are time and accuracy.
Mentor’s Colin Walls focused this week’s blog on a topic that is becoming harder to ignore at every process node: multicore chips and multiple operating systems. Apparently one of Mentor’s competitors told Walls he was overcomplicating the matter. We come down firmly in Walls’ camp. Each OS has its own behavior and nuances, and not all of them play nicely together in the same sandbox. And when it comes to real-time OSes, they’ve never been required to stick to any standardized rules (although it will be interesting to see what happens to Wind River’s RTOSes now that the company is owned by Intel).
eSilicon’s Jack Harding talks about the new economics of competition. What happens when someone can do your job for 5% less, on schedule, and guarantees the results? This may put a new spin on what constitutes a mid-life crisis.
Cadence’s Richard Goering reviews the greatest moments in EDA history. It’s an interesting compilation, and it’s the basis of why this sector increasingly is looking far less EDA-like and a lot more ESL-centric.
Synopsys’ Navraj Nandra looks into digital scaling trends for analog IP. It can be done, but certainly not with the same level of automation as it does in the digital world—or at least not yet.
And what exactly is an SoC? Gabe Moretti takes a look at Bill Schweber’s blog about the subject (which makes this a blog about a blog about a blog) and comes up with some idea about why this term is confusing. The conclusion: An SoC is really just a small PCB. Well, sort of.
What’s the difference between innovation and invention? Cadence’s Jack Erickson says they’re not the same thing. This is a good blog for someone who is looking at their next project rather than trying to get through their existing one. It’s definitely something worth thinking about.
Tags: Cadence, eSilicon, Mentor Graphics, Synopsys, Virage Logic