The Big Picture In Low Power
Power reduction in advanced chip implementations requires a comprehensive approach that supports a broad range of design techniques. The Synopsys EclypseTM Low Power Solution provides an end-to-end solution that enables designers to combine tools and IP within an automated, easy-to-use low power workflow. Design teams benefit from reduced iterations and improved productivity across verification and implementation flows, from architecture development, through design implementation and verification, to silicon signoff. Providing a truly comprehensive power reduction and optimization solution is only possible with the support of a strong ecosystem. Synopsys works with industry-leading partners to develop IP, methodology, modeling techniques, and foundry flows that support the Synopsys Eclypse Low Power Solution.
This white paper describes the key issues that designers face in reducing chip power dissipation, and outlines Synopsys’ approach to providing low power design solutions utilizing the open, industry-standard IEEE 1801TM “Standard for Design and Verification of Low Power Integrated Circuits.” To download this paper, click here.
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