Extraction Techniques For High-Performance, High-Capacity Simulation
Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2x to 4x with every new process generation as chip transistor counts double and new parasitic effects come into play. Designers of custom digital, analog/mixed-signal (AMS) and memory integrated circuits (ICs) must now manage an ever-increasing volume of post-layout data while meeting the razor-thin design margins and tight project cycle times. These conflicting challenges are driving the need for more accurate and efficient parasitic extraction and simulation solutions to accelerate verification and achieve first time right silicon. The Synopsys StarRCTM extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level designs while preserving signoff accuracy. This paper presents these innovative extraction techniques for high-performance and high-capacity simulation.
Tags: Synopsys