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Surface Models Focus Low-Power Parasitic Problems

By John Blyler
Low-Power Engineering sat down with Raj Nair, founder of Anasim Corp. and co-author of a recent book on power integrity. What follows are excerpts of that conversation.

LPE: How can parasitics like capacitors be used to create an electromagnetic lens and focus noise on the power grid of a chip. How does that work?
Nair: This tool is intended primarily as a teaching aid so people could get used to the idea that you can analyze power integrity (PI) as a surface effect rather than as trillions of individual transistor polygonical shapes. The tendency in both chip and board-level power designs is to place capacitors where you have space to help reduce noise. But if you don’t understand the wave nature of the noise propagation, then the capacitors can make the problem much worse. As our simulator shows, capacitors can be used to focus or concentrate noise in area that you least expect it, i.e., on the “non-noise” side of a bank of capacitors.

In this example, you’ll notice a radiating noise block at the bottom of the simulation. That noise interacts with an array of capacitors in the middle (rectangular shaped). As it plays out, the noise is actually being focused behind the array of capacitors (the big red spot is noise). The capacitors act as an electromagnetic lens. This is the same phenomenon that happens in the optical domain. We forget that light is nothing but an electromagnetic (EM) wave. What we observe in chips is no different than from light, except that it is at a very lower frequency from the light standpoint.

The EM spectrum is a continuum. Light is at the very far end of the spectrum in terms of frequency. At that frequency it becomes visible to our senses. Our eyes can see it. As you come down in frequency, you deal with EM frequency, the frequency that is in our chip – billions and trillions of hertz. It is a continuum. So whatever phenomenon we observe, we see, uses lens and light, and are phenomena that can be seen in electrical simulation such as these.

Today’s chips have come to a point where we can see optical-like interaction of noise with capacitance inside the chip. This is real. This is because the chip surface is being modeled in a true physical manner as opposed as simple IR drop. In the past, power integrity was constantly associated with the analysis of IR drop. But IR drops completely ignore the electromagnetic effects from capacitance and inductance.

The practical application of this simulation approach is that you can see the interaction of noise with various groups that have various amounts of caps. For example, capacitors are used to block noise. But here, caps focus the noise.

The tendency is to put in caps where ever you have space, to help reduce noise. But if you don’t understand the wave nature of the noise propagation, then the capacitors can make the problem must worse. Your assumption might be that noise “behind” the caps would be less and your IR simulations may not show anything.

The focusing action is very simple. It is basically the fact that an EM wave slows down when it encounters capacitance. The slow down is different because the shape of the caps are a lens shape. You could shape it to diverge it as well with a concave lens. This one in the example is a convex lens.

It’s a learning tool, which is why we are giving it away for free. On the full-up version, you can connect the board and package caps.

LPE: Let’s return to basics. How do you define power integrity?
Nair: Power integrity (PI) is a rather esoteric subject. Even experts in the field interpret it in different ways, often confusing power integrity with power optimization. In the simplest terms, PI refers to the variations from an ideal power source. For example, in chips, power integrity deals with variations in the power supply differential to the chip.

The variations are more pronounced at the nano-scale where you have lower voltages and higher currents. The reason for an increase in current is that overall chip-level power conception has not gone down, even though the scaling of chip geometrics reduces the power to individual transistors. However, overall power has remained roughly the same due to the ever-increasing demand for information and data processing, such as increased feature sets. This increase in current and the effect on circuit parasitics directly affects power integrity issues.

LPE: How does this affect low power designs?
Nair: Power is voltage multiplied by current (P=VI). The fundamental way to reduce power in chip is by reducing voltage. But in chip, power is proportional to the capacitance times the voltage squared times the frequency (CV2f). If you reduce the voltage, then you’ll have a quadratic reduction in power. Voltage is the critical controlling parameter for power reduction—whether it is achieved through clock gating or power gating. The challenge is that, if you bring down the power, you also decrease the power supply differential voltage, which increases your susceptibility to noise. This is why power integrity is more severe as you go to lower process geometries and lower power systems.

LPE: How does PI affect the larger integrated system, i.e. the chip-package and board?
Nair: From the standpoint of power integrity, integration is both a boon and a curse. Integration brings greater functionality and performance, but that translates into a much greater need for overall power. Integrated components still consume roughly the same amount of power. Plus, to achieve higher functionality, you are integrating more components that often operate at higher and higher frequencies.

Today’s tools are another challenge for the integrity of low power designs. A chip is an aggregation of different functional blocks. All of these block – really, the entire chip is interacting though the package and the board. All of the capacitors on the chip, package and board are affecting the power from the main global supply. Designers must observe the effects at the micro (chip) level but also analyze everything at the macro (board) level. Most of today’s tools focus on the chip, the package or the board.

Compounding this problem is the fact that most chip-level physical designs are done with polygons. All of the transistors are modeled as polygonal shapes. As you move down to finer dimensions you have trillions of polygons inside the chip. Extracting the electrical properties of trillions of polygons and analyzing them in SPICE becomes an almost impossible problem, requiring server farms that run simulation running for days or even weeks.

LPE: What’s the solution?
Nair: We solve it by going to high levels of abstraction and with physics-based simulations. Instead of the interactions of individual polygons inside the chip, we analyze the system as a surface. By treating the power delivery system within the chip as a surface we solve only for the surface equations – not trillions of individual polygons. This is no different from the way engineers try to model conductors. Like the power grid, conductors also have a non-uniform density of current flow. But instead of modeling the non-uniform current flow, engineers typically average out the variance by associating a fixed conductance value with the conductor. In the same way, we are averaging it out the voltage variations over the entire surface.

LPE: What does the future hold for small-geometry power integrity?
Nair: In the future, when we go to really deep nanoscale designs and 3D integration, such abstractions will become essential. Without such abstractions I don’t think analysis will really be very feasible using day-to-day computers. You can still revert back to detailed simulation as needed – as discovered by the broader simulation.

This simulation methodology is meant to be used as a front-end analysis, early analysis that allows people to optimize things – like your power line width, placement of caps, optimized placement of the blocks that generate noise. Keep in mind all the other constraints such as routing, signal degradations, timing, leakage constraint. Keep all these other constraints in view, and now you now have another dimension that you can optimize for, which is PI. It’s crucial for low power.

Power Integrity Analysis and Management for Integrated Circuits
By Raj Nair, Donald Bennett
Published May 7, 2010 by Prentice Hall.

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