Worst Case Power Varies With Geometrics
By John Blyler
When designing for low power operation, engineers are constrained by the worst case (highest power) ratings for the silicon. But the power distribution characteristics of silicon can vary significantly from wafer lot to lot for the latest, lowest process geometry. How can designers deal with the worst case power ratings in their low power, high volume FPGAs designs?
First, let’s consider the process. To establish the power distribution range for their products, FPGA vendors start with a target yield. This yield provides the initial cost structure and allows them to publish numbers based on characterization over a statistically meaningful number of wafer lots, notes Christian Plante, director of marketing for low-power and mixed-signal FPGAs at Actel. “We characterize our silicon over many lots. Thus, it can take us a little while to put worst-case numbers (for the latest geometrics) into our software modeling tools.” The reason for this delay is that the latest process geometric nodes are less tamed than the older, higher, established nodes.
Characterizing worst-case conditions at higher nodes like 130nm isn’t a big problem. The manufacturing processes at these geometrics are well known. Thus, the power distribution curves are much tighter with less variation.
It’s the lower geometrics, like Xilinx’s and Altera’s 28nm processes, where the power distribution between wafer lots will be the most variant. And while this variation will tighten-up as the process matures, that will take some time.
Process variations during manufacturing also can worsen the affects of static power leakage, notes Michael Kendrick, product planning manager for Lattice Semiconductor. “As we move forward with geometries the voltage threshold decreases, which in turn causes static power leakage to increase, relative to dynamic power.” This results in a wider distribution of static power consumption over time – increasing the worst-case power constraints for FPGA designers.
Engineers are not without options. There are several techniques to mitigate the effects of static power leakage. For example, designers can be more careful on the mix of high-speed transistors used, since these transistors have higher leakage, says Kendrick. There are also process improvements that reduce leakage at 28nm.
The uncertainties of exact worst-case low-power conditions at lower geometrics, like 28nm, may give FPGA vendors of higher node chips an advantage. After all, the power distribution at higher nodes is more fully understood. Less variation in the power distribution of well-known, higher node geometrics should translate to less variant in the worse case power ranges.
But Actel’s Plante adds a note of caution, explaining that if the power distribution strays too far outside of customer expectations then the FPGA vendors can’t sell those chips—except to a customer that will accept the additional power consumption.
Further, FPGA vendors at the lower process nodes, like Xilinx’s new 28nm Virtex 7 and Altera’s Stratix V product lines, offer the lower power that is inherent with the move to smaller process geometry. Also, Xilinx emphasizes the power benefits of scalability with their new 28nm offerings. Both their lower-end, higher-volume and high-end, higher-performance FPGA families are built on the same underlying architecture, which may help mitigate the effects of wafer power distribution variations at the newer node.
The move to new process geometrics always brings new challenges. Fully understanding the variation of power distributions within the silicon is but one of those challenges that FPGA designers must understand when designing to worst-case power conditions.
Tags: Actel, Altera, Lattice Semiconductor, Xilinx