Power has always been an integral part of consumer electronics, but increasingly we can do more things with a single device. That trend, above all others, has moved power consumption from an afterthought to a critical part of the architecture of the processor, the SoC and even the end device itself.

Much of this change has been very gradual—not that long ago, cell phone batteries lasted only an hour or two. Over time, however, the pace has increased along the Moore’s Law roadmap. At 45nm and beyond the need to save power is no longer optional. It is a requirement imposed by consumers on the device manufacturers, who in turn now look at rival semiconductor devices in terms of power consumption and time between battery charges.

For SoC architects and engineers at all levels of the design flow, the tradeoffs between area, power and performance are now unevenly weighted toward power. And while there are numerous tools on the designer’s belt to solve these problems, the burden each of those places on the verification side of the process has become overwhelming.
All of this can mount up very fast in terms of cost, both in non-recurring engineering hours and re-spins after initial tapeout, which at advanced nodes can easily run into the tens of millions of dollars. But even those costs pale in comparison to the cost of a missed market window.

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Tags: Synopsys

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