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Formal Verification Of Power-Aware Designs

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, through RTL implementation to physical design.

This white paper addresses the verification challenges posed by power-aware chip design, and how the JasperGold Low Power Verification App works with other JasperGold Apps to overcome those challenges. It covers:

  1. Power-aware verification challenges
  2. Power-aware verification requirements
  3. The limitations of traditional power-aware verification
  4. Meeting power-aware verification requirements with JasperGold Apps

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