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Has Power Trumped Performance?

By Hamilton Carter

About a year ago, John Blyler reported on several talks at the Ansys-Apache Design “Dimensions of Electronic Design” seminar. Those talks indicated that power-consumption design considerations were inexorably inching toward becoming the key concern at mobile SoC and IP design houses. It’s all fine and dandy that you can track your stock portfolio and video-record your kid’s ballet recital while catching up with Grandma—all on your smartphone. But it’s all for naught if the heat generated by the phone’s multi-tasking hardware burns your hand just before your battery dies.

I checked in with a few industry experts this month to see how things had progressed in the ensuing year. While the reduction of raw power consumption by physical means is both a concern and a valuable tool, this month’s roundtable participants—Lawrence Loh, VP of Applications Engineering from Jasper Design Automation, and Gary Smith of Gary Smith EDA—focused on how EDA tools are successfully dealing with power concerns at the functional level.

Power vs. Performance

Once upon a time, verification of low-power functionality was a low priority for many design teams. If all of the power features didn’t work on the first tapeout, it wasn’t the end of the world. Apparently, those days are long gone.

When asked if there were still design houses that did seat-of-their-pants power design and verification, Gary Smith’s initial response was a simple “No.” He then expanded on the situation: “No, power has become the number-one problem. All design targets are being constrained by power. If you don’t meet your power budget, you must either slow down your design (parallel computing) or restrict the size of your design. That’s after you use all of the design tricks to lower your power consumption (power gating, clock gating, etc.).”

Power considerations are even turning up in rather fundamental condensed-matter physics research. Researchers are working on new types of electron-spin-enabled memories. This field is still in its adolescence. At a colloquium earlier this month, the presenter indicated that one of the key motivators for the research had been to develop new versions of dense memories that consumed less power.

First, Do No Harm

Low-power verification has two key considerations. Of course, the first one is don’t let your end customers burn their hands, laps, or furniture or wind up with a 15-min. battery life. Second, while you’re taking care of the first consideration, make sure you don’t break any of the device’s functionality on which the customers depend. It’s a thankless job; your customers probably won’t swoon over the extra 5 min. of battery life you were able to squeeze in. But calls to the help lines will be fast and furious if they lose their contact list every time their smartphone goes into sleep mode.

When I asked Lawrence Loh if he knew of any engineering teams that were skimping on power verification, he couldn’t think of a single one. Instead, he pointed out that the indicators they’ve had point in the exact opposite direction. Jasper’s low-power verification app was one of its most inquired-about and most-used products. The app works with Jasper’s other formal checkers to ensure that power optimizations haven’t corrupted other functionality.

Low-Power Design in Stay-at-Home Products

While power consumption is certainly a prominent concern in mobile designs, it’s become an issue in stationary devices like set-top boxes and desktop PCs as well. With ever-increasing amounts of graphical and audio resolution available—as well as the itinerant ramp in available processing power—it’s natural that consumers should expect to reap benefits in the form of visually and stereophonically stunning output. You might think that we’ve just about hit the limit of human perception at our current resolutions. But keep in mind that developments like those made by Daniel Smalley of MIT earlier this year promise that bandwidth-hungry technologies like holographic projection are just around the corner. Power has become the fly in the ointment here as well. No matter the quality of a device’s video and audio output, the typical consumer—as well as all of the power-conscious certification boards (think polar bears)—still expect televisions to consume no more power than their resolution-hobbled (relatively speaking) predecessors from a few years ago.

Looking at the Bottom from the Top

Everyone agreed that plenty of good power-consumption modeling information is available from the fabs. Lawrence Loh pointed out that the data is so good that chip-level architects are leveraging it to decide which portions of their designs could benefit most from power optimizations based on the available power information available for each type of logic cell.

Tall and Touch It All or Divide and Conquer?

At the Design Automation Conference (DAC) in Austin this summer, more than one speaker pointed out that there’s a shortage of engineers with a rock-solid grasp of the entire SoC hierarchy from application code down through block-level register transfer level (RTL) and transistor-level power consumption. While a few of these folks have been identified—and they’re certainly a valuable addition to any team—most chip-design projects and the EDA industry at large are following the tried and true hierarchical methodology of divide and conquer.

Lawrence Loh mentioned that one engineer probably won’t have knowledge of the entire chip and its intended application. Yet each level of engineer (transistor, block, sub-block, SoC, RTOS…), when provided with a power budget, can rather easily ensure that their particular design portion meets requirements. This methodology has been used successfully for the last few decades in the functional verification of large chip-design projects. Crucial functionality is verified at a given level, and that level of the design is then passed to the next design team up. The higher-level design team depends on the lower-level verification to be both adequate and complete, as it focuses its efforts on verifying the functionality added by its own level. Loh said this technique is already being applied quite effectively to the verification of low-power functionality as well.

For his part, Gary Smith presented a vision of the future that included both hierarchical organization and automated tools. “Well, we sure need more tall, thin engineers. However, once we have all of the standards in place, we will have the tools needed for the HW and SW engineers to get the job done. The actual application programmers will be given necessary pass/fail types of tools (plus some analytical tools) to develop power-aware software.”

The hierarchical division of power management hasn’t percolated all the way to the top of the application stack in terms of standards yet. Gary pointed out that while we have good information on how much power devices consume, power standards currently only reach into the architectural area. Standards that reach all the way into the behavioral level would allow system architects to reap additional power savings.

“We have power standards that reach into the architectural area. We still need behavioral standards. The further up the flow you are in the design, the more the IP blocks become more application-specific until they come with their own software bundled into the package. So it’s not as much the information as it is the necessary standards and the tradeoff between accuracy and speed of execution that needs to be worked out for the process to work.”


Power and thermal constraints are at least as important as performance gains in mobile designs. The advent of WiFi-enabled wristwatches, for example, provides a whole new level of nightmarish scenarios when devices overheat. For the moment, though, it looks like the tried and true verification methodology of dividing the chip into hierarchical levels—combined with smart engineers and clever EDA tools—has once again turned a giant engineering problem into one that is at least tractable.

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