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Best Practices for Mixed Signal, RF and Microcontroller IoT

By John Blyler

The Low-Power Engineering (LPE) portal asked the experts for help in detailing the best practices to help digital designers incorporate analog, mixed signal and RF functionality into their System-on-Chips (SoC). What follows is a compendium of inputs from Diya Soubra, CPU Product Manager, Processor Division and Joseph Yiu, Embedded Technology Specialist at ARM; Qi Wang,Technical Marketing Group Director and Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems.

Blyler: What are the best practices for EDA chip-level IoT mixed signal and microcontroller designs?

Joseph Yiu:
- Use of power aware verification early and throughout in the project, e.g., power aware simulation with Si2 Common Power Format (CPF) (and/or IEEE-Accellera Unified Power Format (UPF)). Power aware verification is not just for low power simulations but also for various system level simulations.
- Use the right model for mixed signal simulation (trade off between accuracy and simulation speed)
- Power quality check. Verification of power constraints/budgets in the early stage of the design can help you to find corner cases in power management schemes.

Qi Wang:
- Analog and digital blocks co-design, like sharing floor plan, pin location/optimization and routing constraints between the analog and digital blocks
- Common design data base between analog and digital design teams to facilitate design data sharing
- Metric driven verification (a digital verification methodology) for analog and mixed-signal designs

Mladen Nizic:
- Abstract analog to higher level. This requires behavioral modeling. (Cadence offers model generation and validation tools as part of the Virtuoso platform).
- Mixed-signal simulation encompassing different levels of abstraction (RTL, gate, analog behavioral, transistor) using various languages (Verilog, Verilog-AMS/wreal, SV, SV-RNM (IEEE1800-2012), VHDL, VHDL-AMS, etc) is required since designs are too large for SPICE or even FastSPICE simulation. (Cadence offers high performance mixed-signal simulation in its Incisive and AMS-Designer product family.)
- Hardware-software co-verification is important for concurrent software development and chip design. That’s why Cadence VSP and Incisive Platforms support early software development and debugging using simulation of entire systems including analog.
- Due to the strong component of both analog and digital, an integrated mixed-signal physical implementation flow is required.

Figure: Integrated flow for embedded processor designs. (Courtesy of Cadence)

Blyler: As mixed signal and RF elements are integrated into the SoC, low power will be a key constraint. What tools and techniques are available to help in the architectural and low-level design of low power devices? What new challenges do IoT designs present that are unique from other spaces?

Soubra: Key technologies focus on power domains and clock gating techniques. Power domains are an architectural strategy in which different functional blocks are designed in different power zones. Each zone may be powered off without impacting the other one. For example, the processor will turn of power to the RF zone all the time, whereas the RF zone will be powered ONLY when a message is required to be transmitted or an answer is expected. This architectural approach dramatically reduces over all power consumption.

In clock gating techniques, the clock is stopped for certain peripherals even though they are powered on. No clock cycles mean no operations, which means no dynamic power consumption. The clocks are turned on when the peripheral is required. This technique gives a faster response time compared to completely powering down a whole zone.

Nizic: IoT devices have to operate on batteries for a very long time (years), ideally recharging by harvesting power from the environment. Therefore, low power cannot be an afterthought, and the system has to be designed, verified and implemented for low power. This is particularly challenging due to the mixed-signal nature of the design. The digital part of design is well automated for optimizing power through top-down leveraging of low power specification such as the Common Power Format (CPF).

As an example, a robust tool suite should allow you to enable:
- Capturing power intent for a custom block in CPF format to:
- Apply the static (formal) verification method on the custom circuit to find out missing level shifters, isolation or power connectivity errors much faster than using simulation
- Use the CPF for the custom block at the top level for static low power verification, to more thoroughly verify the full chip
- Use CPF specification for managing conversion at analog-digital signal crossings during power shutoff, and different power domains.

Yiu: IoT design present challenges that are unique from other spaces. Low power wireless interface is one key challenge. Many IoT devices will need low power connectivity but current WiFi and mobile network standards won’t work for many of these applications. For example, 6LoWPAN and Weightless are some of the new technologies aiming to provide low power wireless communication for IoT.

There are many tools and techniques that can help in the design of low power chips, from processor, memory and RF techniques to system- and power-level to design flows (see below).

The selection of processor core intellectual property (IP) is very important:
- Low power processors with high energy efficiency, fast interrupt response enable processing tasks to complete in short time, allowing the digital parts of the system to be in sleep modes for longer (Note: The power consumption of the memory system is often much larger than the processor, so by having processor in sleep mode for a longer period can save a lot of power).
- Low power features in the processor play a important role. While many processor IP support sleep modes, additional interface are needed to support some of the advance low power techniques. Many processors also have various levels of clock gating supports (standard clock gating in synthesis, additional block level clock gating to gate off whole block, etc).
- Code density of processor is another important aspect. High code density enables smaller flash memory to be used. This again saves power.
- In some cases, the processor can be optimized to reduce speculative fetches from the memory system and that can improve the energy efficiency.

System level design is also important:
- The system level design need to be optimized for low latency and low power. Traditionally some MCU achieve low power by reducing clock frequency for peripheral systems, but this can increase read/write latency and end up wasting more power in I/O intensive applications. Recent designs use clock gating extensively to reduce power without the need to run the internal buses at slow speed.
- Advanced clock frequency distribution control is getting common. Many low power microcontrollers now allows you to turn off clock signals to individual peripherals, and adjust the clock frequency for each part of the design for optimal power.
- Peripheral design needs to be designed for low power. For example, separate clocks for bus interface and peripheral operation might helps. Also, many new microcontroller designs has smart peripherals that can provide some functionality without waking up the processors from sleep modes.
- Selection of operation clock frequency for processor and peripherals is important for many RF designs. Often the digital parts (including peripheral) can generate switching noises and the harmonics can affect the sensitivity of the RF circuits. The analogue components being used might need to be customized to reduce some of the harmonics.

Low power memories:
- Various low power techniques are available to reduce power in memories. Lots of research are going on about next generation low power memories (FRAM, MRAM, ReRAM, etc). If these technologies will be successful, a microcontroller can have a unified memory (combining flash and RAM) to save power. There are also some enhancements in low power flash (e.g. Atmel has a flash sampling technique that allows their Cortex-M4 parts, SAM4L, to operate at under 100uA/MHz).
- Some small memory buffer logic can be used to reduce access to the flash memories.
- New memory compilers technologies enable lower power SRAM with higher density.

Low power processes:
- Use of Ultra Low Leakage (ULL) cell libraries are getting more common.
- New cell library technologies like Thick Gate Oxide (TGO) is starting to gain momentum.
- Near threshold/sub threshold techniques started to be used on commercial products
- Advanced techniques like State Retention Power Gating (SRPG) are being used in microcontroller devices like Freescale Kinetis. (Note: SRPG require special support in processor design, which is supported by ARM Cortex-M processors).

Design flow
- Recent year the use of power aware development flow is getting more popular.
- Mixed Vt (threshold voltage) design techniques are also used to reduce power in many designs.
- Many design tools (e.g. Cadence Encounter Power System) allows you to do power analysis

RF design:
- When mixing analog, digital and RF, be careful with power noise and floor planning of the chip. Typically you will have separate power domains, power rails.
- Although it is possible to integrate RF on the same CMOS silicon, as far as I know there isn’t design tools to allow the designs to be simulated together. So you still need to design the RF part separately, and then integrate the RF layout into the overall layout. Filters may be needed for signals interfacing between RF and digital domains.

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