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Digital vs. Analog and the verification of power: Inductors

I got a chance to speak with Aveek Sarkar, vice president of product engineering and support at ANSYS Apache this week.  Our conversation about power aware verification revolved around the di/dt voltage drop caused by on chip inductors also known as power delivery grids.  Although, I grew up as an analog engineer dallying with inductors and capacitors on a daily basis, as a functional verification engineer, I’ve considered inductors and capacitors… well… almost never.  Consequently I thought it might be kind of fun to run through a high level review of why inductors drop voltages.

Inductors, Calculus, and the Time Domain

While discussing verifying the power distribution grid, the expression, ‘LDIDT drop’, came up a lot.  Written down, it looks like this

and is translated as: the instantaneous voltage drop across an inductor is equal to its inductance times the rate that the current through the inductor is changing with time.  Why does it matter?  When a block of a chip is powered off and then powered back on, there is a quick change from zero current running down the supply bus to the total amount of current needed by the block.

The above picture is idealized, but it gets the point across.  The current running down the supply bus jumped from zero to Io in a very short time.  Consequently, the voltage drop across the inductor went from zero to a big number, (Io divided by a number approaching zero).  It is this voltage drop that can cause problems downstream on the power bus, especially if the power bus in question is attached to other blocks.

An analogy of Aveek’s that I paraphrase here is apt.  If you’ve ever rented an old cabin, or had the pleasure of living in college slums at school, you may have noticed that with all the lights on, and the washing machine running, when you turned on the microwave, the lights all over the house flickered.  That flickering was due to the L di/dt voltage drop caused by the microwave quickly slurping a gulp of current off the shared power line.  Flickering lights can be intriguing and even romantic in the right setting, but in digital circuits, flicker is just plain bad.

Inductors and the Frequency Domain

Thanks to Heaviside lots of us like to think of inductors in the frequency rather than the time domain.  In the frequency domain the expression for the above voltage drop is:

where j is the square root of negative one and omega is the frequency of the current running through the inductor.  In short, the inductor acts as a larger impedance to higher frequency signals.  How does this apply to our step function above?  Any time-based waveform like our step can be expressed as sum of sine waves via a Fourier series.  The picture below illustrates how sine waves of different frequencies can be added to create a square wave-like shape.

Note that to get closer to an actual square wave, more waves of higher frequency have to be added to the sum.  The additional sine waves of higher frequency see a higher impedance due to the inductor and therefore, a larger voltage drop.

A Musical Side note

The same process described above is why audiophiles will tell you that music sampled at 56 kHz simply isn’t crisp enough and that they prefer the ‘more realistic’ sound of 96, or even 160 kHz sampled music.  It’s all about having more available frequencies to more accurately reconstruct a waveform.


Fast changes in current can make circuit elements that once looked like wires behave like inductors.  The associated voltage drop downstream can wreak havoc with the rest of the circuit.  The equation that governs this voltage drop can be thought of in either time domain as it happens via a bit of calculus, or in the frequency domain as a consequence of the high frequency waveforms required to create fast current transitions.

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One Response to “Digital vs. Analog and the verification of power: Inductors”

  1. Low Power News: November 1, 2013 | Low-Power Engineering Says:

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