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Expert Interviews: Apache’s Aveek Sarkar: Low Power Design

By Hamilton Carter, Editor/Verification-Low Power

LPE got to sit down with ANSYS Apache’s Aveek Sarkar to discuss how design engineers sort out the variety of low power techniques that are available to them.

LPE:  Where do design engineers start when looking at different power efficiency design techniques?

Clock gating was one of the first things people started to look at for power optimization.  In clock gating you shut off parts of your clock network such as a the portion of the clock network driving a particular bank of registers that do not have any data activity – this way you can save dynamic power.  It’s still one of the first places to look for savings as dynamic power is a big component of overall power.  There’s a pitfall however.  A common mistake is not taking the design of the enable signals or their efficiency into account.  If 99% of the design is clock gated, it doesn’t mean that you have a low power design – it also depends on whether the enable signal is operating efficiently.  Often times, projects which have clock gated the entire design can still lose sight of the fact that the efficiency of clock gating is controlled by the enable signal. If the enable signal is not designed properly it can limit the amount of power reduction you can achieve. So it’s  important to simulate the design and perform rigorous power exploration, tracking various metrics including clock gating efficiency especially at the RTL level to isolate and fix such scenarios.

LPE: What about power gating?

Power gating is commonly used to control  leakage current or standby power.  Its use started to become prominent around 2005 by mobile IC design teams, especially starting with the 65 nm process nodes.  The leakage current was an increasing trend in those process nodes – to control that, they started adding power gating as a low power design technique.  Power gating effectively breaks up power supply into two paths: an external path and an internal path by putting NMOS or PMOS transistor in series with the power rails.  For example, if the video block of the device is not being accessed then the video processing section of the chip does not need to operate. By flipping off that particular switch on the power rail, it turns off or disconnects that block from the rest of the power supply.  As a result, the leakage current drops significantly, sometime as much as 10x to 15x. However, based on some of the metrics that are printed in the press, especially with the advent of finFET, leakage power seems to be getting more under control as compared to dynamic power.  So power gating is still being used but it’s not clear if it’s going to be a standard technique going forward.

When using power gating, you need to worry about few things. The first thing to consider is that when you turn off power, you need to make sure that the state of certain parts of the device needs to be retained.  So you need well designed retention logic to make sure that you don’t lose whatever the design was doing last even if you shut off the power to that block.  You want to make sure you can recover the last state and move onwards. The second thing to consider is the time it takes to bring the block back on after its power off state and the current and voltage levels during and after the power up process.

The current trend is to look at power gating the design from a macro level – that means to power gate bigger sections of the chip rather than looking at it in a finer grain. With power gating at the macro scale, there are a couple of things you need to worry about.  For example when you turn a block back on you need a lot of current.  If the size of the power gated block is significant, such as an entire CPU core, a lot of charge is required to turn it on. If you have to supply power all at once, the battery may not be able to supply it quickly enough.  When this current goes through the package, it gets impeded. Two things can happen.  First, if you don’t power up quickly you can end up seeing an hourglass on the device’s screen since that block takes much longer to power up or doesn’t power up to the right voltage level.

Second, and possibly worse, the block that is turning on may borrow charge from a neighboring block.  For example, if  you powered off one of the CPUs in a quad core architecture and shortly thereafter turn it back on. This power-on process will require a lot of charge and you may end up stealing from the neighboring CPU. But the neighboring CPU may be still running.  So, as you take charge from the neighboring CPU it can end up experiencing higher voltage drop or increased noise coupling, which can impact its performance or cause it to fail.  This kind is scenario is fairly common and has to be watched out for, ideally with the use of a full-chip level package-aware power noise analysis flow that can model such a scenario.

LPE: How do dynamic voltage and frequency scaling factor in?

Depending on the type of application that is running, the chip can become very hot and to control the heat, the chip will need to be slowed down to extend the its lifetime or improve its power performance. But this technique, like others has the same set of challenges since it can introduce unknown behavior that can crop up when the device goes from one mode to another, or from one activity to another.  To protect against unpredictable behavior, the design needs to be modeled at the full chip level with the package and the board to simulate the transient current changes that accompany these mode transitions.

LPE: What other power saving techniques might be of interest?

Forward and reverse biasing rate techniques are making a comeback.  We are seeing designs where these techniques are being used.  Another interesting technology that is becoming prevalent is the use of on-chip voltage regulators (LDO).  When people want to control voltage for mission critical devices in an automotive IC or say for a sensor inside a pacemaker or other devices where you consume very little power over time, on-chip regulators will become increasingly critical. For these devices, it is very important to model the operation of the LDO in context of the design it is supplying power to. This ensures that the LDO can operate reliably across the entire range of operation of the chip.

Aveek Sarkar joined Apache Design, Inc., a subsidiary of ANSYS, as a senior applications engineer in 2003. Since then he has taken on different roles and responsibilities. Prior to joining Apache, Mr. Sarkar worked for Sun Microsystems on several generations of UltraSparc processors. Prior to Sun, he held engineering positions at Cadence Design Systems and National Semiconductor. Mr. Sarkar holds a B. Tech from the Indian Institute of Technology, Kanpur, a MSEE from Oregon State University, and MBA from Santa Clara University.

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