By Ed Sperling
Microsemi announced plans to buy Actel for $20.88 per share, or roughly $430 million, expanding into the increasingly popular FPGA market with a particular advantage in the low-power area.

The deal adds another dimension to Microsemi’s lineup of high-reliability chips and high-performance analog/mixed signal products. Actel has played heavily in both of those markets, and actually has spanned both with its new SmartFusion FPGAs that add programmable analog onto an FPGA. In addition, Actel has the lowest-power lineup in the FPGA world. Power is now a checklist item for many companies building devices, with power now replacing performance as the most critical feature.

“We believe the addition of Actel will deliver compelling synergies to Microsemi,” said James J. Peterson, Microsemi president and CEO, in a statement. “Actel will bring the most widely-used mixed-signal, radiation tolerant FPGA products in the aerospace and defense markets today, and the company’s products will allow Microsemi to extend its growing system-level capabilities. As Microsemi continues to move up the value chain in offering its customers system solutions that are better, faster, and more-cost effective than they can build themselves, Actel’s highly-integrated solutions will be an integral component in enabling this growth.”

Microsemi, based in Irvine, has sales of about $600 million per year based on its current quarter projection. The company sells into a variety of markets ranging from medical to defense, notebook computers, LCD televisions and automotive applications.

The deal is expected to close by Jan. 2, 2011.

By Ann Steffora Mutschler

SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs?

Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-power applications is really the device, not any particular circuit implementation.”

“Power-aware design is very important. Design practices like power-aware clock domain management are critical to the management of power in battery operation handheld device applications, and use of flexible sleep modes that retain data and circuitry states can yield major advances in battery life,” he said, but he cautioned that flash-based FPGAs, for example, can deliver such radically lower power consumption compared to SRAM-based FPGA devices that the selection of the “theoretical best vs. absolute worst design practices for power consumption would yield nothing close to the differences between the underlying device technologies.”

Brogley said IEEE P1801 (UPF) “certainly brings a lot to the table—a standardized way of describing power across the design spectrum cannot be undervalued. The degree to which tools providers support the UPF language and methodology in the tools applicable to FPGA design will drive the relevance to IP in the FPGA world.

Looking at it from a higher level, Ken Brock, director of physical IP marketing at Virage Logic said the standards efforts “take care of the needs of the EDA vendors, which is a very important component of the recipe. [But] it doesn’t really address a lot of the other issues for IP vendors. It doesn’t address which voltages, which temperatures are across the line, and certainly doesn’t address any of the functionality issues.”

Vic Kulkarni, senior VP and GM of the RTL business unit at Apache Design Solutions, agrees with Brock. “There is more to it than just the CPF or UPF standards—that’s really the key,” and points out the importance of understanding the bigger drivers at play. It requires looking at the technology migrations and technology advancements to put things into perspective.

Starting with timing, signal integrity was the key, he noted, followed by static IR. Dynamic power issues took over at 65nm as interconnect-driven timing became more critical, which impacted the RC as opposed to the pure timer. Then reliability came into the picture at 45nm with intra-domain challenges to cross-domain challenges; a domain defined as creating an IP, putting the IP in the context of an SoC, with that SoC put into the context of a PCB and package. In terms of creation of IP, it could be digital IP or analog to digital, then the I/Os come in the picture. How do you manage these extremely high speed DDRs? DDRs are pretty much driving the apps we just talked about, he said.

“CPF or UPF is very critical as part of driving a low power intent, but that’s not good enough for sign-off and assuring that indeed your IP works in the context of SoC and package,” Kulkarni explained. He said Apache looks at this issue holistically in terms of creation of IP at the ESL world, the RTL world, the logic world and then the process world and bringing all of them together.

“If you look at what happens to power, if you target it early in the design, you have the highest probability of making an impact on the creation of low-power or low-noise-aware IP and SoCs. You have to target at the higher levels of abstraction but as you go down toward synthesis and post-place & route, the ability to impact power gets further and further reduced. However, by the same definition the implementation and signoff importance increases because they have to be more and more precise toward the silicon. So combining these two is critical in terms of IP creation and IP validation. Mitigating power integrity issues from power reduction techniques happens in the implementation phase,” Kulkarni said.

“UPF and CPF are about low power intent and that is required only for extremely high-level designers, but once you get down in the RTL what do you do with it? It keeps you ‘low-power correct’ in terms of specifying islands that are created but if those island start switching, what happens to my physical design? That they can’t tell you,” he added.

While UPF and CPF are a great start, it may be a few more years before it is truly possible to standardize IP in low power designs given the use cases it needs to be characterized for.

When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC’s circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs). Two subclasses of SEEs were of particular interest to the designers of RTAX-DSP:

Single-event upsets (SEUs): SEUs are probably the best understood class of SEEs. An SEU occurs when sufficient charge is collected in a static memory element (latch, register or SRAM cell) that the resulting voltage causes the static memory element to change state (flip its bit). These errors or upsets last until the next time new data is written to the memory element.

Single-event transients (SETs): When impacting ions induce voltage pulses on combinatorial circuitry in a device, these effects are known as SETs. If the induced voltage level exceeds that of the switching threshold and is of sufficient pulse-width, erroneous data values can be propagated through the circuit. As the name implies, these errors are temporary in nature, with pulse-widths on the order of 500 ps.
To read more, click here.

By John Blyler
When designing for low power operation, engineers are constrained by the worst case (highest power) ratings for the silicon. But the power distribution characteristics of silicon can vary significantly from wafer lot to lot for the latest, lowest process geometry. How can designers deal with the worst case power ratings in their low power, high volume FPGAs designs?

First, let’s consider the process. To establish the power distribution range for their products, FPGA vendors start with a target yield. This yield provides the initial cost structure and allows them to publish numbers based on characterization over a statistically meaningful number of wafer lots, notes Christian Plante, director of marketing for low-power and mixed-signal FPGAs at Actel. “We characterize our silicon over many lots. Thus, it can take us a little while to put worst-case numbers (for the latest geometrics) into our software modeling tools.” The reason for this delay is that the latest process geometric nodes are less tamed than the older, higher, established nodes.

Characterizing worst-case conditions at higher nodes like 130nm isn’t a big problem. The manufacturing processes at these geometrics are well known. Thus, the power distribution curves are much tighter with less variation.

It’s the lower geometrics, like Xilinx’s and Altera’s 28nm processes, where the power distribution between wafer lots will be the most variant. And while this variation will tighten-up as the process matures, that will take some time.

Process variations during manufacturing also can worsen the affects of static power leakage, notes Michael Kendrick, product planning manager for Lattice Semiconductor. “As we move forward with geometries the voltage threshold decreases, which in turn causes static power leakage to increase, relative to dynamic power.” This results in a wider distribution of static power consumption over time – increasing the worst-case power constraints for FPGA designers.

Engineers are not without options. There are several techniques to mitigate the effects of static power leakage. For example, designers can be more careful on the mix of high-speed transistors used, since these transistors have higher leakage, says Kendrick. There are also process improvements that reduce leakage at 28nm.

The uncertainties of exact worst-case low-power conditions at lower geometrics, like 28nm, may give FPGA vendors of higher node chips an advantage. After all, the power distribution at higher nodes is more fully understood. Less variation in the power distribution of well-known, higher node geometrics should translate to less variant in the worse case power ranges.

But Actel’s Plante adds a note of caution, explaining that if the power distribution strays too far outside of customer expectations then the FPGA vendors can’t sell those chips—except to a customer that will accept the additional power consumption.

Further, FPGA vendors at the lower process nodes, like Xilinx’s new 28nm Virtex 7 and Altera’s Stratix V product lines, offer the lower power that is inherent with the move to smaller process geometry. Also, Xilinx emphasizes the power benefits of scalability with their new 28nm offerings. Both their lower-end, higher-volume and high-end, higher-performance FPGA families are built on the same underlying architecture, which may help mitigate the effects of wafer power distribution variations at the newer node.

The move to new process geometrics always brings new challenges. Fully understanding the variation of power distributions within the silicon is but one of those challenges that FPGA designers must understand when designing to worst-case power conditions.

Actel’s logo incorporates the phrase Power Matters, and Actel’s emphasis on power savings is real. All of Actel’s flash-based FPGAs, including Actel’s new SmartFusion intelligent mixed signal FPGA, are intrinsically low power devices. Low device power consumption, low cooling requirements, efficient power management and system monitoring all contribute to the total efficiency of a system. With increasing emphasis on efficient use of limited energy supplies and natural resources, products with the smallest impact and most efficient use of energy deliver a real competitive advantage. Management of power at the system level is a challenge faced by all system designers who grapple with a daunting set of divides between digital and analog as well as software and circuitry when they consider the best tools, practices and methodologies. An innovative methodology developed by Actel addresses these challenges and eliminates barriers to delivering user-configurable mixed signal power management that spans software and hardware, analog and digital domains, all without the need to reprogram FPGA circuitry to implement functional changes.

Management of power-up sequencing, monitoring and trimming on-board power regulators, conditionally invoking partial or full system power-down, and managing power-down sequencing are functions often implemented using assemblies of discrete devices, but it is rare that standard devices precisely meet the exact specifications of a particular requirement due to fixed number of channels, limited voltage range and limited digital input/output (I/O) capabilities. Designers are reluctant at times to consider custom power management solutions because of added design cycle time, cost and the need to systematically validate such a solution. This risk aversion leads inevitably to compromise, such as downgrading of the feature set to match the capabilities of available devices, or selecting parts that exceed design requirements despite performance, board space, and price penalties. With the advent of mixed signal FPGA devices that integrate industry standard embedded microcontrollers, these compromises can be reduced, but new challenges arise.

To find out more, click here.

By Ed Sperling
ARM took a new tack in its war with Intel. The company is working on a Green Cloud Services project using the ARM architecture in conjunction with Nokia, IMEC, EPFL and the University of Cypress to create a 3D package with low-power processing. This is particularly interesting in light of gamers using Intel Atom-based servers.

Along the same power-saving lines, Actel introduced its power management solution for its SmartFusion mixed signal FPGA, complete with a reference design and a configurator for power sequencing and trimming. Given Actel’s focus on low power in its other chips, this isn’t all that surprising.

Also on the low-power front, Virage Logic introduced a big update of the open source GNU and Linux toolchains for its ARC processors, which will soon belong to Synopsys. That puts Synopsys firmly into the open source world, as well, with interesting implications.

Arteris joined forces with other EDA and IP vendors supporting TSMC Reference Flow 11, this time with network on chip interconnect IP. This is more like networking the industry on chip.

eSilicon will provide logistics services and production operations to Ember and Pixim. This is an interesting extension of supply chain expertise.

Mentor Graphics rolled out its commercial embedded Linux platform for Freescale, building on a strategic alliance the two had signed in April.

Mentor also won a couple deals with Mindtree for its Questa functional verification and with Autoliv for machine programming.

Both Synopsys and Cadence trumpeted successes with their products. Cadence global services enabled a 65nm TD-LTE baseband chip from Innofidei, a company with operations in Taiwan and Beijing. Synopsys, meanwhile, demonstrated interoperability between DesignWare IP for PCI Express 3.0. The company also awarded the Tenzing Norgay interoperability achievement award to IEEE-ISTO. We’re not sure what the famed Sherpa had to do with interoperability, but congrats.

By Ed Sperling
Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic.

Xilinx declined to comment, but a half-dozen independent industry sources familiar with its efforts have confirmed the 3D development is well under way. Rich Kapusta, Actel’s vice president of marketing, applications and business development confirmed his company has been approached by SoC makers to use the company’s non-volatile flash-based FPGA as a layer in their 3D SoCs. He declined to comment further.

Getting 3D chips this kind of work done is anything but guaranteed. It’s complicated and there are lots of pitfalls, such as accessing RAM or logic across multiple die. Nevertheless, the implications of these developments are enormous. Because of the very regular and controlled structure of an FPGA, it is extremely well suited to defining where components can be placed on a chip. That makes it much easier to predict hot spots caused by putting two or more chips together—a problem that becomes particularly thorny when chip layers are developed by multiple vendors without knowledge of the thermal characteristics and layout of the other components.

3D stacking makes it far easier to bump up performance at advanced nodes using shorter wires while reducing power because it takes less power to achieve that performance over shorter distances. But getting this accomplished with SoCs has been particularly difficult. As a result, sources say the need for FPGA prototypes may change FPGAs into the end game rather than an in-between step.

Moreover, both moves also are expected to open huge markets, finally, for advanced EDA tools to work on complex FPGA designs, as well as third-party IP, processor cores from companies like ARM, MIPS and Virage Logic, and interconnect fabrics such as network on chip. They also can open up 3D to mainstream development. While companies such as IBM, Freescale, Qualcomm and Texas Instruments have been working on 3D chips for years—IBM started its R&D in this area almost a decade ago—most of that work has been a closely held secret because it is considered a competitive advantage for performance and power. FPGAs can quickly turn that into a less expensive option that may have more overhead than bottom-to-top 3D ASIC designs, but far less than 2D ASICs.

Issues in 3D
FPGAs can solve one of the biggest problems in 3D stacking, namely standards for placement of components. Without those standardized approaches there will likely be some ugly finger-pointing when two chips are put together.

“One of the problems that we see coming is who’s going to pay for a bad part,” said Andrew Yang, chairman and CEO of Apache Design Systems. “Testing may show that memory and logic are all good and that the die works, but when you put it together with another chip it may turn into a bad part. So you can say it’s good, and all your testing and verification may show that it is, but when it doesn’t work who pays?”

Yang said there is a need for far more analysis of the stacked die, measuring everything from heat and power to electrostatic discharge and signal integrity.

“We also need to understand what are the killer applications and what applications are not good for 3D,” he said. “The compelling value of 3D is shorter distance, which is the TSV promise. The challenge is in coupling chips together. In 2D you could shield high-speed signal transmissions. You get a cross-coupling effect with a TSV, so there is promise but there are also challenges.”

One of the big draws for 3D in general is the ability to re-use IP, which may come in the form of entire chips. That doesn’t work too well, however, when those chips were created for the best utilization of real estate on a 2D structure, where heat dissipation is relatively simple. In 3D, putting chips together can sandwich heat between die with no way to get it out of the chip.

“When you stack die you concentrate the heat,” said Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. “That affects chip reliability, either short-term or long-term because they’re operating at temperatures they’re not expected to operate at. Circuits perform differently at 100C or 125C or 130C. At 130C it may affect the core, the timing, the signal integrity.”

While the overall heat of a chip hasn’t changed much, the more tightly everything is packed together the more difficult it is to cool. “When you stack them, you concentrate that heat even more,” Robertson said. “Potentially, when you move the wires closer together you can reduce resistance and IR drop. There would be a decrease in power and heat, but we have not seen enough of that yet to draw that conclusion.”

Under the covers, there are two technical ways to make this all possible, according to an ARM insider. “The first is for TSVs at similar pitch to solder bumps (about 50nm). This expands the capability of FPGAs and creates what amounts to multi-FPGA chips, as well as allowing for better-integrated flash, DRAM, and high-performance logic. The limited inter-chip bandwidth and power delivery, along with thermal issues, keep this as more of a cost dynamic – an extension to existing SiP approaches,” said the source. “The second answer is for high-density future TSVs, at a pitch of less than 5nm. These increase inter-chip bandwidth by a factor of 100 over the first solution and allow for some game-changing capability, including wide word high-speed off-chip memory access, combined FPGA/logic solutions, multi-die FPGA (greatly increased gate count) and so on. The reconfigurable aspect of FPGAs may also help solve the test and fault tolerance issues that are a very significant impediment to making tight pitch TSVs viable. Neither of these eliminates the crossover argument on power and performance, but they both have the potential to move it.”

Programming the future

Whether this effort ultimately succeeds is anyone’s guess. What is known is that a lot of resources are being marshaled into 3D stacking and a lot of hopes are being pinned on the back of efforts such as those from Xilinx and Actel’s partners.

Tom Quan, deputy director of design methodology at TSMC, said the great advantage of FPGAs is that they are very regular. “You can predict the thermal profile much better than with a mixed-signal SoC. Analog can be all over the map. But while the base array may be regular, in another corner of the chip you might have a USB so the outside of the chip might be hotter than the inside.”

Still, there was a lot of hype behind multi-chip modules in the 1990s and so far they have failed to materialize as a popular solution, largely because of cost. That could change as double patterning becomes the norm at 22/20nm and standard production costs rise, but visibility remains limited at that node.

At the very least, the moves by FPGA players are worth tracking, and a lot of companies are predicting major changes if these scenarios work. There are reasons FPGAs may hold more promise than multi-vendor or multi-generational SoCs. But there are still a lot of challenges to resolve before the total cost of development is known

By Ed Sperling
Not everyone is moving quickly to the latest process node these days. In fact, the number of companies following Moore’s Law is dwindling at each new node, and it is expected to drop off further at 22nm and beyond.

While this has been anticipated for some time, the new wrinkle is the amount of work being done these days at older process nodes—particularly in the area of power.

“We’re seeing a resurgence of power management even at the 180nm node with an ultra-low-leakage process that TSMC offers,” said Lisa Minwell, technical marketing director at Virage Logic. “This is where there are microcontrollers and consumer products that need low leakage. We’re seeing a renewed interest in our low-power products that we’ve had on the shelf since 180nm.”

That is not an indication that there is not lucrative activity for EDA players at the most advanced nodes. Virage Logic, for one, sells IP at both ends of the spectrum and most of the large semiconductor companies would much prefer to buy commercially available tools and IP to help them solve their technology problems ranging from power modeling on the front end to verifying multiple power domains on the back end.

But end customers are far less concerned these days about process nodes or even chip technology than cost and whether a chip meets their specific needs. “Customers don’t care about the process curve,” said Christian Plante, director of marketing at Actel. “It’s all about cost of ownership, which is why many companies that used to build ASICs are now using FPGAs. The number of ASIC starts is extremely low.”

He said that if a company is building a router with lots and lots of gates, they’ll probably opt for a Xilinx Virtex 6. If they want a chip with a very small footprint and lower power, they’ll choose an Actel chip.

“Cell phone companies and Sony with its playstation have to go to the next process node,” Plante said. “But infrastructure companies like Lucent and Cisco rarely start ASIC designs any more.”

Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications. In addition, FPGAs’ generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms.

For such applications, FPGAs need to achieve a high level of tamper resistance in order to preserve confidential information and ensure system integrity. Systems that utilize FPGAs for cryptography may also need to comply with tamper-resistance security standards, including applicable Common Criteria protection profiles as well as the upcoming U.S. government FIPS 140-3 standard.

Non-invasive attacks, including both simple and differential power analysis (SPA and DPA), must be addressed by all FPGA-based systems that require any significant degree of tamper resistance. Power analysis attacks can be carried out by attackers with modest skill and resources, since power measurements can be collected and analyzed easily. If a design is not adequately protected, secrets such as sensitive data, IP, trade-secrets and cryptographic keys can be extracted, and adversaries could make unauthorized modifications to the device configuration.

This whitepaper introduces SPA and DPA, discusses how these vulnerabilities apply to FPGAs, and provides guidance about the types of countermeasures that can be implemented to protect FPGAs against these attacks. To download this paper, click here.

By Ed Sperling
Mentor Graphics added multicore solutions for symmetric and asymmetric multiprocessing to its Nucleus real-time operating system, building in support for the multicore communications application programming interface, aka MCAPI, for communications between processors. The standard was established by the Multicore Association.

Synopsys added support for Actel’s SmartFusion FPGAs, which add programmable analog on top of an FPGA. The Synplify Pro tools have been enhanced for timing optimization of the flash-based Actel architecture.
Synopsys also introduced its next-gen rapid prototyping system, the HAPS-60 series, for hardware-software co-verification.

Cadence contributed extensions for the Verilog-AMS standard to Accellera to improve accuracy and offer more plug-and-play in mixed-signal environments. That includes most SoCs these days.

Virage Logic qualified its AEON non-volatile memory EEPROM IP for 1 million cycles at 105 degrees Celsius. In event of severe global warming, you can be sure this will still work. In fact, it may be the only thing left working.