The hardware platform management layer of the PICMG AdvancedTCA, MicroTCA and AdvancedMCTM frameworks (collectively, xTCA) has been a key factor in the widespread adoption of these open modular architectures in communications and other applications. This mandatory layer does “close to hardware” management: tracking the thermal, power and interconnect aspects of xTCA boards, modules and shelves (or chassis), among other functions.

This paper introduces the hardware platform management layer of xTCA, with a focus on the local management controllers that are required to be part of each board and module. Further, the paper discusses using intelligent mixed signal FPGAs, such as Actel’s new SmartFusionTM family, as the core of those controllers. An intelligent mixed signal FPGA can integrate a wide range of local management controller functions into a single chip, including monitoring voltages, currents and temperatures, executing the xTCA compliant management firmware and notifying upper management layers of any locally detected exception conditions. That single chip can incorporate additional blocks of IP to further optimize it for management applications and even integrate board-specific logic that would otherwise require a separate PLD on the board. The xTCA specifications allow the above functions to be implemented in a standardized fashion, enabling fully interoperable systems to be built from independently implemented board, module and shelf components. Pigeon Point management solutions, which are used as examples in this paper, are incorporated widely in xTCA board, module and shelf products.

To download this paper, click here.

Arteris, which makes network on chip technology, announced it is working with ARM to provide interoperability with ARM’s AMBA 4 bus specification. This is an interesting deal. On one hand, it expands ARM’s options with a faster and easier interconnect strategy. On the other, it moves Arteris deep inside ARM’s ecosystem, which includes 750 companies at last count. Many of those companies are on the short list for handheld devices such as smart phones—so far the leaders in low-power design—which now have to support more I/O options and communications protocols in a very narrow power budget. And not to be forgotten, until now most outsiders viewed these two companies as competitors.

Virage Logic rolled out new D-PHY and controllers for the 40nm low-power process across a number of standard interfaces such as the mobile industry processor interface (MIPI) and the camera serial interface receiver (CSI Rx). The company says power is down 80% and area is down 70%.

Mentor Graphics’ Calibre DFM is now qualified for TSMC’s 28nm processes. For anyone who thought the Roaring ’20s was something out of history, wait until you see the sounds coming out of the semiconductor design world over the next couple of nodes.

IAR Systems, which makes middleware for microcontrollers, threw its support behind Actel’s new SmartFusion chip. While this is a good deal for IAR—SmartFusion is the first chip to combine a programmable analog subsystem with an FPGA on a single low-power chip—it also gives Actel access to the industrial, medical and communications markets.

Synopsys completed its acquisition of CoWare. It now owns a company in which rival Cadence once invested, not to mention the vast majority of the commercial software prototyping market.

Cadence, meanwhile, acquired Taray, which makes tools to put FPGAs onto printed circuit boards. This is an interesting move for a couple reasons. First, it’s something of an acceptance that there are plenty of tools around for designing FPGAs and the most successful ones are those made by the FPGA vendors themselves. The reason? They’re cheap. Second, it moves Cadence out of the fray of whether FPGAs actually need more advanced tools made by Mentor and Synopsys and addresses a very real problem, namely putting the chips on a board. The main competition in this space will likely be Mentor Graphics.

Is this considered an adjacent market or a sharp left turn? TSMC broke ground on an LED lighting R&D center. The focus is LEDs and solar power, according to TSMC Chairman Morris Chang.

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”

The whole point of an FPGA is flexibility. We could also mention integration and say instead that the whole point of an FPGA is flexibility and integration. But then there is cost savings. So the whole point of an FPGA is flexibility, integration and cost savings. Yet there is also power reduction. And then there’s security…

All these advantages (and others besides) have made FPGAs very popular over the years. Engineers like the flexibility, space and power reduction and integration that FPGAs provide. So it stands to reason that adding more flexibility, more integration and more cost and space savings would be a good thing.

Actel’s new family of SmartFusion chips takes all the traditional advantages of FPGAs and combines them with equally flexible analog circuitry and the world’s most popular embedded processor. It’s all rolled up in one package, and all under your control. It’s a single “super chip” that could very probably be the only chip in your system. How’s that for space, time, power and cost savings?

To download this article, click here.

Actel set the FGPA market ablaze with its new SmartFusion device, which combines programmable analog with a complete microcontroller subsystem and an integrated programming environment, including tools. This is an interesting move, and it will be equally interesting to see how long it takes Actel’s top rivals to respond. Actel insiders, most of whom came from Xilinx and Altera, say the catch up period may be quite lengthy. They may have a bone to pick, but the low-power angle is definitely interesting. This also should grab some attention from the companies that have been developing multichip solutions because they don’t want to deal with integrating analog and digital.

Mentor Graphics announced its fiscal Q4 financials for the full year ending Jan. 31. Revenue was $802.7 million, up 2% from fiscal 2009. Non-GAAP earnings per share more than doubled to $0.47 per share, while the GAAP loss was $0.23 per share. That’s a lot better than a loss of $0.99 per share. For the fiscal Q4 Mentor revenues of $237.1 million, non-GAAP earnings per share of $.30, and GAAP earnings per share of $.39. As Mentor chairman and CEO Wally Rhines pointed out, “the electronics industry recovery seems to be well underway.” Break out the champagne—but don’t spend more than $8 a bottle or the corporate accounting department won’t approve it.

Synopsys bolstered the capabilities of its System Studio C/C++ analysis and simulation environment. The product now includes support for matrix and vector data types, which the company says significantly reduces coding and debugging efforts.

The Taiwanese earthquake earlier this week registered 6.4 and cost about 1.5 days in wafer movement from TSMC’s fabs in Tainan. This was a big earthquake, but the impact was slightly less near the Tainan fabs.

You have to wonder about Wall Street. Marvell beats estimates by $500,000 and the stock tumbles. According to analysts, the company didn’t beat estimates by enough. Isn’t the whole point to meet estimates?

Intel added the Atom processor to the networked small office/home office storage market. What’s interesting about this announcement isn’t Intel’s push into this market. It’s that there is now a dual-core version of Atom available. This should make for a nifty ultra-low power solution.

Actel’s Fusion® FPGA family enables the creation of powerful, highly integrated power management solutions. Power management today must deliver high levels of system power control with minimal impact to power consumption and board space. Actel offers an intelligent digital power management (IDPM) solution that provides high-level power management in a low-power, configurable, single-chip design.

The IDPM solution embeds a capable 32-bit ARM® CortexTM-M1 microprocessor, flash memory, SRAM, analog functions, oscillator, a host of peripherals and a generous amount of user logic space into a single chip. The platform is modular and scalable, accommodating a base solution that can be easily expanded to control up to 32 digital point-of-load (DPOL) power supplies. Actel’s FPGA toolset makes hardware and software modifications simple, resulting in quick integration and fast time-to-market.

The IDPM solution is ideal for telecom line-card applications, and industrial, consumer and aerospace applications. To download this paper, click here.

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation.

LPE: Is a more complex supply chain causing reliability issues?
Sanguinetti: That does happen as a result of disaggregation. There’s third-party IP and the associated issues of putting it all together. The most common problem is when you buy a piece of third-party IP and you want it to do something just a little bit different. You make a change—or a third party makes a change and it isn’t fully tested. That’s the way bugs get introduced.
Buric: This touches the gray area between quality and reliability. That’s why people have standards. TSMC is developing TSMC 9000, which is just one measure of an ISO standard. When you build a complex device that’s how you make sure all sub-components conform to quality standards. That’s part of the equation. If you can’t establish quality standards you cannot manage a design these days.
O’Neill: Quality standards would mean things like toggle coverage and code coverage for validation and test programs?
Buric: Yes. Whatever you may need.

LPE: How disaggregated is the supply chain?
O’Neill: It’s becoming more disaggregated. Years ago when I started with Actel we designed the entire chip. We designed the I/Os, the logic, the routing and the programmable interconnect. Today, because of the complexity of our current and future generations of FPGAs, we’re sourcing pieces of IP from outside of our own company. There’s a supply chain issue there. We have to choose our suppliers wisely, as well as the products we purchase from them, and ensure that we’re consistent with our own verification and validation techniques. Going forward, we will do more and more sourcing of our IP as our products become more complicated.

LPE: As the foundries impose restrictive design rules at future process nodes, how will that affect reliability?
Buric: Restrictive design rules have always been there. They have not always been so obvious, though. They help reliability. If you don’t use them, then you have a fundamental failure in yield. Reliability is a marginal case of yield. They are establishing rules to minimize freedom of implementation on silicon, which will result in higher reliability. As the process matures, some of those rules may be waived. They can learn enough to see it is not impacting anything.
Sanguinetti: Over time, our coding requirements have gotten more strict. They don’t have the effect of design rules, though.

LPE: But isn’t this complexity hitting every part of the flow?
Sanguinetti: Yes, it is, and we’ve had to modify our product over time to put out RTL that is more regular and follows different rules. That has been a maturation process. But it’s on the order of 10s or 100s of rules, not thousands.
O’Neill: We see some movement in the end-user community and among their customers to impose coding standards, as well. If you’re doing a design for an industrial process at a petrochemical plant or something that’s safety critical you may be working to a certain specification imposed by intended operator of the plant. They will impose coding standards. Similarly, for commercial aircraft we’re seeing the certifying authorities imposing standards on the contractors, who in turn are purchasing FPGAs or ASICS to implement critical digital logic.
Buric: The European Community has been doing that with their contracts for the past 20 years. Companies have had to follow their codec style or they would not get the contract.
Smith: The challenge for the restrictive design rules is that if the foundries are too restrictive, people will not move to the next node. It will be too restrictive, too expensive, and far less attractive. We have a lot of customers designing at 40nm, but a lot of design is still being done at 180nm. There are reasons to go to 40nm—density and power—but there’s not free lunch. It costs more to do designs for all the reasons we’re talking about: verification, reliability and everything else.

LPE: Are the economics of reliability changing? Does it become more expensive to guarantee reliability at future process nodes?
O’Neill: Absolutely.
Smith: The number of rules and the number of cases you need to check for goes up, so it’s more expensive.
Buric: Reliability is becoming a liability. You have to design with that in mind and it costs you money. I have seen people doing it for alpha particles where it’s two-bit detection, one-bit correction. I’m now seeing algorithms with 8-bit detection. People need it or they wouldn’t do it. It costs silicon and it costs in the design.

LPE: Is reliability now part of the cost equation in developing a chip?
Buric: Yes.
Smith: For the fabs, definitely. They’re staking their reputation on being able to deliver a product that meets certain standards. Being able to test that and then being able to somehow abstract that and do a bunch of rules so folks like us can take those rules and make sure everyone follows them is a tough job.
O’Neill: From an FPGA standpoint, we’re not designing for a single application. We’re designing for a whole range of applications. We go from consumer electronics applications, which have a lifespan of two years, to military and aerospace systems that have to survive 20 years. We don’t have the luxury of just designing an FPGA that just survives two years. We have to design for the maximum lifetime. That really causes us to look very carefully at the tradeoffs between density, reliability, power and performance.
Sanguinetti: What would you do differently if you could design products just for the consumer electronics market?
O’Neill: Let the parts run hotter so the power density would be higher. There’s a tradeoff there, too, because you need low power to conserve battery.
Buric: You could save on the package, too.

LPE: Is reliability considered essential all the time?
Buric: It is company-specific. It’s hard to see a trend. In the consumer market, cost is critical. In that market, failure is measured against cost of replacement.
Sanguinetti: If you have a TV set that drops frames every 30 seconds or you get a blocky picture, you get a bad reputation and no one buys your products.
Smith: It depends on the application. In military and aerospace, it’s vital to be reliable. On the other extreme, if you go into the Hallmark store and pick up a card with a synthesizer attached to a battery, it has to last through the shelf life, but design for reliability is minimal.

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high-reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation.

LPE: As we push to the next process nodes, do all of the tricks of power islands and multiple voltages become more common in designs?
Buric: No, because people will look at the cost of implementation. We have customers looking at simulating and figuring out what are the power savings of switching something off and turning it back on. That costs power. They are doing fairly complicated analyses and staying away from these techniques if they don’t have to use them.

LPE: If you implement all of these techniques, though, is a device more reliable or less reliable?
Buric: In my opinion, it becomes more difficult to make it reliable. But it’s all comes back to your capabilities. If you know how to do it and you’ve done it before, it’s more difficult but you can still do it.
Smith: I don’t think it’s de facto less reliable. But it makes it a heck of lot more difficult to maintain reliability. That requires a lot of work. The other side of this is that low power used to be just battery-powered devices. Now it’s part of the overall Green movement. Everybody is searching for ways to cut power. About 1.5% of all the power generated goes into servers, server farms, and the cooling associated with it. We have a lot of wireless customers. Power is a huge deal. Reliability is a huge deal, too. If you have a phone that dies all the time, the manufacturer is going to go out of business. But we’re starting to see more of a focus on low power for things people plug into the grid, and the government is starting to mandate that. Reducing power without giving up the reliability is very hard.
Sanguinetti: That’s true even in this industry. Quite a number of companies have verification server farms. You run your regression tests with 10,000 processors. That has a power bill of about $1 million a year. That’s a lot of electricity.
Buric: We have 1,000-plus processors just to do fairly straightforward tests. One of the things that is responsible for what’s going on here at the lower technology nodes is that IP memory and logic design and EDA tools help solve reliability problems that may be caused by calculation errors from migration that overload certain parts of the design. It’s much more critical on the current nodes than before. You have to properly characterize IP and use synthesis, high-level synthesis and place-and-route tools to avoid any potential reliability problems in operating conditions.
O’Neill: We’re all coming at this from a variety of different directions, but in our world we see an intersection between low power and reliability. This is from a system-level for high-reliability and outer-space systems. The motivation for achieving low power in the consumer space is battery life and the greater good of the planet. In military and aerospace, battery life can be important in handheld radio systems, but there’s much more interest in reliability. Power becomes a reliability issue for a different reason. There are a lot of very high-performance systems where they can’t have forced cooling. The cooling fan itself is a factor in reliability. Fans can fail and they can increase the risk of foreign debris, which can cause short circuits and add other reliability risks.

LPE: So it’s imperative to lower the power in the parts?
O’Neill: Yes, because as you increase the performance of these systems, more power is being generated. That means more heat, and heat equals reliability risk. There are very few failure mechanisms that decelerate with temperature. Most of them accelerate with temperature, and some of them accelerate exponentially. So minimizing the heat dissipation inside enclosures that have very complex systems running inside them becomes a primary issue. People often come to us seeking low-power FPGAs because there’s some other power-hogging device inside the enclosure generating a lot of heat. They need to minimize that. They can’t afford another heat-generating device.

LPE: Do devices that use lower power last longer?
O’Neill: Given the same process node, if you run at lower power you’re probably going to have better reliability because your junction temperature is lower. That’s going to result in prolonged life.
Buric: If you look at what people are doing with end of life now, they’re saying lower temperature will extend the life. It’s very clear that if you go to overheated conditions where a lot of parts become unpredictably fast then you have a very high chance of a device completely malfunctioning.

LPE: Where does this get designed in?
Sanguinetti: We don’t have any visibility into this.
Smith: Neither do we. It’s something our customers have to deal with. Our job is to get them from concept to manufacturing. Their job is to figure out the application and the expected lifespan. In some applications, a year is fine. If it’s going into the engine controller of an automobile, a year is not fine. That would be more like 15 or 20 years at a minimum.
Buric: End of life is primarily a process function, and for that reason it is analyzed and characterized at the device level. A lot of people simulate end of life, and those models are typically provided by the process side. These are similar to any other SPICE model.
O’Neill: When we design a chip, we design with a package that comes from the foundry. That package will include things like the design rules, which are decided by tradeoffs between reliability, power, functionality and sheer utilization. You want to cram as much logic into as small a space as possible, but you’d better not exceed the electromigration rules or whatever other rules are in there for reliability.

LPE: In the synthesis world, what’s the biggest reliability issue?
Sanguinetti: Logic errors. It’s getting the design right. The issues that our customers have, aside from the spec being wrong, is interfaces between blocks or sections of the design that are done with high-level synthesis and those sections that are done with legacy RTL or manually. That’s where the opportunity for errors is the greatest. When you’re within the confines of high-level synthesis, the opportunity for error gets reduced and the verification problem is reduced. But at those interfaces there’s a lot of potential for miscommunication.

LPE: As the industry becomes more disaggregated, does it become more difficult to pinpoint the source of reliability problems?
Buric: No. Problems are well defined and everyone has to take responsibility. If you go back to our discussion about radiation and alpha particles, you design to eliminate that problem. That design can be in the memory space or error correction. You know what the problem is and you solve the problem. If the problem is end of life and the technology provider gives you all the guidelines, then you design with those in mind. If you own the design, you own the problem. It’s in designers’ hands and it’s a well-defined boundary.
Smith: It’s a gray area. In the ideal world, we get a set of rules from the foundry. There are thousands of them, and if you do this and this then they’ll stand behind the process in the design. For a big part of the population, that’s the way it works. But the people with the deeper pockets will go back to the foundry and say, ‘Let’s talk about where these margins really are because we need to do something special for this product line.’ They’ll get the data, analyze it, and they may design outside of those guidelines. The rules are the rules except when you break them to get an advantage, and then you’d better have the time and the money to go analyze everything to make sure you don’t end up with a product that fails or doesn’t yield.
Buric: You actually don’t break rules. You define a new set of rules that are mutually agreed upon. If you set those rules unilaterally, you’re shooting yourself in the foot. Memory cells have violated every rule, but they’re so predictable in manufacturing that they can violate the rules. All of those are mutually agreed upon, though.

In the short span of three decades, electronics have not only proliferated in our world, but have also gotten smaller and more portable. The march of Moore’s Law has brought portability to the consumer, industrial, military, medical and other markets.

As this demand within end markets has exploded, so too has the pressure for low-power subsystems and ICs to power them. And, as the world is getting more excited about the increasing opportunity that electronics integration and mobility brings, so is the feverish demand for new products and new features to appear on store shelves “now.” This has radically altered electronics design choices and decisions upstream. Expensive ASICs or custom ICs simply do not work in markets where cost is a factor, but the ability to hit tight market windows and adapt to changing technology standards is paramount.

This paradigm shift puts the design imperative on Actel’s flash-based FPGAs, which offer both low-power capability and system-design flexibility to meet time-to-market demands and changing user requirements and standards. To read more, click here.

By Ed Sperling

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation.

LPE: Do chips become less reliable as we start adding power islands, multiple voltages into the mix with smaller line widths and multiple cores?
O’Neill: As we go down the process curve, one of the effects we have observed is that radiation effects are no longer the domain of designers just working on aerospace systems. We’ve seen radiation effects start to become dominant from a reliability standpoint in commercial ground-level systems. These are background neutrons in the atmosphere. That can cause memory cells to have single-bit upsets, and the consequences can be severe. For most applications, you don’t care about a single bit. In consumer electronics, it may be a pixel changing color. But if you have system-critical data in a server or a router it could mean enterprise-class equipment having field failures.
Buric: All of those effects started showing up at 90nm when people started doing a serious analysis of the radiation space. It’s not getting better. It’s getting worse each node. There are two aspects of dealing with this. One is how the system is designed. The other is how system designers can further ensure that nothing has happened.

LPE: Does it show up on the design side?
Sanguinetti: We don’t see it directly, but our customers are putting tighter requirements on the style of RTL that we produce. Most of it includes locally produced rules. Those rules have been developed to ensure a smooth transition through the back-end flow. Now they’re starting to add rules it will produce better results. That’s about our only exposure to the physical side. The other piece of reliability is whether you’ve got the logic right, and that’s just verification.
Smith: On the implementation side, reliability is more around design rules. Presumably some of these effects are covered by those rules. What’s most important in our world are the low-power effects—multiple voltage domains, turning blocks on and off, dynamic voltage frequency scaling. The question is how you model that design so it will be reliable under a bunch of different operating conditions. It’s now multi-load, multi-corner and multicore. We’ve seen designs that have up to 100 different models. That affects reliability.

LPE: From the standpoint of all the multiple everything, does it become less reliable as you keep dropping the voltage?
Buric: You’re talking about a badly implemented design. We have customers today that, because of technology scaling, have thousands of memory instances on the same design. This is a nightmare by itself. There is also a lot of process variation. You need to make sure that the same device in place ‘A’ has the same performance on place ‘B.’ You have to consider all of that. If you do it wrong, you don’t get proper yield. But you also might have a chip that escapes detection in the test but which has problems in the field. We have customers making hearing aids. They are trying to drop the voltage as low as you can get, and they are really hitting the limit at low voltages for both how to maintain content in memory and how to operate. Then the design misbehaves because they are pushing the lower corners of performance. On advanced nodes you also have a phenomenon of low voltage combined with other low voltages behaves much worse than a typical array. That creates additional reliability problems.

LPE: Finding all the corners and verifying all the various pieces is getting harder. What’s the impact on reliability with that?
Smith: The amount of time that’s being spent on verification, particularly on small geometry and very complex chips, is rising. Implementation and place and route is still a huge job. But the verification is taking more time. Most of the verification flows are 15 years old. Variability on chip is a huge effect. At 180nm we didn’t have to worry about that very much. At 40nm and 28nm, it’s a big concern. Verification takes a lot more time and more compute power. It now takes a CPU farm. The industry is ripe for big change there. In terms of reliability, it depends on whether you’re going to do a marginal design or a really good design. To do a good design you have to do a lot of verification and you have a lot of operating conditions. And if you’re doing a low-power design and using all these techniques, there are likely to be a lot of operating environments. Then you have to consider all the corners in the process. When you multiply those out you have hundreds of different scenarios.
Sanguinetti: These issues are less important for some products than others. But the line between what we think of as consumer products and other products is blurry. Is an industrial printer a consumer product? If something goes wrong there, you may get degraded quality. But what if it’s a prototype of a device that prints 3D models. A failure there, or an intermittent failure, can result in something a good deal worse. Is a hearing aid a consumer device?
Smith: Or a pacemaker?
Sanguinetti: Reliability also is a bigger issue if you have to reboot something. Do you really want to reboot your television or your hearing aid.
Buric: But when you talk about power islands and multiple voltages, those techniques are much less used than you might expect. It’s extremely difficult to use them in a reliable fashion. We see people staying away from using them, especially in consumer devices. It’s extremely expensive. If there was an easy way to verify them, that would eliminate some of the problems we face now. But right now, there’s much more noise than reality.

LPE: Is it the same in the verification world?
O’Neill: There are two aspects to that. There’s the verification we as a company do. And then there’s the verification our customers do on their designs when they’re getting ready to program the design into a part. From the customer perspective, the changes we’ve seen are scaling linearly with the fact that they are doing bigger and faster designs. But it’s not an exponential increase in the amount of verification and validation of those designs. A lot of the deep submicron effects are somewhat shielded from the customers by the fact that there’s a level of silicon design and we just give them a tool to place logic into this part. The onus is on us to design our FPGA with as much competence as possible to mitigate the deep submicron effects. From the point of view of the design teams at Actel, they are spending more time using more complex tools to do verification and validation of their designs. In addition to implementing programmable gates and routing structures we’re adding hard IP into our parts. That includes multiply/accumulate blocks, increasingly sophisticated I/Os, different flavors of SRAM cells and various forms of non-volatile memory. All of those things represent different types of what is effectively ASIC design, and it’s now being done by the Actel design team. We, on the other hand, have experienced an exponential increase in validation and verification.