By John Blyler
Lattice Semiconductor’s proposed acquisition of FPGA start-up SiliconBlue Technologies for $62 million in cash is the latest signal that the smart-phone market may be showing signs of overcrowding.

While researchers are quick to point out the growth rates of smart phones sales versus computers, there also are an unprecedented number of companies vying for a stake of that market. Lattice’s push into adjacent markets is a hedge against that overcrowding.

Lattice until now has focused on the high end of the smart phone market. Silicon Blue targets mid-range players such as watch companies.

Doug Hunter, vice president of marketing at Lattice, said both companies occupy complementary spaces in the mobile consumer market. Silicon Blue offers a reduced feature set at lower power and with a one-time programmable (OTP) memory technology that it licensed exclusively from Kilopass. “This will allow us to go into customers with both a simpler and smaller or bigger and more fully featured suite of products,” explained Hunter.

By far the larger company, Lattice has more than $250 million in cash on the balance sheet with a good quality track record, said Hunter. The company also has a much wider distribution and sales network than start-up Silicon Blue, which should help win sales from customers that are reluctant to deal with a start-up company.

Still, Lattice has had its share of challenges in recent times, including numerous CEOs over the last six years and loss of market share to giants such as Xilinx and Altera. Hunter acknowledge these challenges, but highlight the company’s current strategy of finding niche to “differentiate, duck, bob and weave” against the two industry giants.

The acquisition of Silicon Blue fits that strategy. In addition to its mid-range handset sales, Silicon Blue recently won a design in an unusual ultra-lower power niche market. Watchmaker giant Citizen Watch selected SiliconBlue’s extremely low-power FPGA device for use in its new Eco-Drive Satellite Wave watch. Citizen claims that this is the world’s first solar-powered GPS-synchronized watch.

One key element in this selection by Citizen was the ultra low power of the company’s 8,000 FPGA logic cells, based on TSMCs 65nm low-power standard CMOS process. The other key factor was the tiny 4×5 mm footprint of the wafer-level chip package, where the ball-grid array (BGA) is placed directly on the wafer. This ensures a very thin package, essentially the same size as the dye.

Silicon Blue optimizes its designs for ultra-low power by using transistors with very fast switching speeds in critical areas of the design like clock trees. Additionally, their design makes use of the default “off” state inherent in FPGAs. “The network is only switched on when it is being used,” explained a company spokesman.

This move by Citizen to incorporate greater electronic functionality in its watches represents an interesting convergence between the worlds of traditionally mechanical-digital systems and fully electronic systems. Citizen’s Eco-Watch is a traditionally high-end timepiece that incorporates modern GPS technology. On the other side of the convergence are fully electronic systems like Apple’s Nano, a multimedia player with Wi-Fi connectivity that now incorporates a digital watch display.

By John Blyler
When designing for low power operation, engineers are constrained by the worst case (highest power) ratings for the silicon. But the power distribution characteristics of silicon can vary significantly from wafer lot to lot for the latest, lowest process geometry. How can designers deal with the worst case power ratings in their low power, high volume FPGAs designs?

First, let’s consider the process. To establish the power distribution range for their products, FPGA vendors start with a target yield. This yield provides the initial cost structure and allows them to publish numbers based on characterization over a statistically meaningful number of wafer lots, notes Christian Plante, director of marketing for low-power and mixed-signal FPGAs at Actel. “We characterize our silicon over many lots. Thus, it can take us a little while to put worst-case numbers (for the latest geometrics) into our software modeling tools.” The reason for this delay is that the latest process geometric nodes are less tamed than the older, higher, established nodes.

Characterizing worst-case conditions at higher nodes like 130nm isn’t a big problem. The manufacturing processes at these geometrics are well known. Thus, the power distribution curves are much tighter with less variation.

It’s the lower geometrics, like Xilinx’s and Altera’s 28nm processes, where the power distribution between wafer lots will be the most variant. And while this variation will tighten-up as the process matures, that will take some time.

Process variations during manufacturing also can worsen the affects of static power leakage, notes Michael Kendrick, product planning manager for Lattice Semiconductor. “As we move forward with geometries the voltage threshold decreases, which in turn causes static power leakage to increase, relative to dynamic power.” This results in a wider distribution of static power consumption over time – increasing the worst-case power constraints for FPGA designers.

Engineers are not without options. There are several techniques to mitigate the effects of static power leakage. For example, designers can be more careful on the mix of high-speed transistors used, since these transistors have higher leakage, says Kendrick. There are also process improvements that reduce leakage at 28nm.

The uncertainties of exact worst-case low-power conditions at lower geometrics, like 28nm, may give FPGA vendors of higher node chips an advantage. After all, the power distribution at higher nodes is more fully understood. Less variation in the power distribution of well-known, higher node geometrics should translate to less variant in the worse case power ranges.

But Actel’s Plante adds a note of caution, explaining that if the power distribution strays too far outside of customer expectations then the FPGA vendors can’t sell those chips—except to a customer that will accept the additional power consumption.

Further, FPGA vendors at the lower process nodes, like Xilinx’s new 28nm Virtex 7 and Altera’s Stratix V product lines, offer the lower power that is inherent with the move to smaller process geometry. Also, Xilinx emphasizes the power benefits of scalability with their new 28nm offerings. Both their lower-end, higher-volume and high-end, higher-performance FPGA families are built on the same underlying architecture, which may help mitigate the effects of wafer power distribution variations at the newer node.

The move to new process geometrics always brings new challenges. Fully understanding the variation of power distributions within the silicon is but one of those challenges that FPGA designers must understand when designing to worst-case power conditions.

Actel set the FGPA market ablaze with its new SmartFusion device, which combines programmable analog with a complete microcontroller subsystem and an integrated programming environment, including tools. This is an interesting move, and it will be equally interesting to see how long it takes Actel’s top rivals to respond. Actel insiders, most of whom came from Xilinx and Altera, say the catch up period may be quite lengthy. They may have a bone to pick, but the low-power angle is definitely interesting. This also should grab some attention from the companies that have been developing multichip solutions because they don’t want to deal with integrating analog and digital.

Mentor Graphics announced its fiscal Q4 financials for the full year ending Jan. 31. Revenue was $802.7 million, up 2% from fiscal 2009. Non-GAAP earnings per share more than doubled to $0.47 per share, while the GAAP loss was $0.23 per share. That’s a lot better than a loss of $0.99 per share. For the fiscal Q4 Mentor revenues of $237.1 million, non-GAAP earnings per share of $.30, and GAAP earnings per share of $.39. As Mentor chairman and CEO Wally Rhines pointed out, “the electronics industry recovery seems to be well underway.” Break out the champagne—but don’t spend more than $8 a bottle or the corporate accounting department won’t approve it.

Synopsys bolstered the capabilities of its System Studio C/C++ analysis and simulation environment. The product now includes support for matrix and vector data types, which the company says significantly reduces coding and debugging efforts.

The Taiwanese earthquake earlier this week registered 6.4 and cost about 1.5 days in wafer movement from TSMC’s fabs in Tainan. This was a big earthquake, but the impact was slightly less near the Tainan fabs.

You have to wonder about Wall Street. Marvell beats estimates by $500,000 and the stock tumbles. According to analysts, the company didn’t beat estimates by enough. Isn’t the whole point to meet estimates?

Intel added the Atom processor to the networked small office/home office storage market. What’s interesting about this announcement isn’t Intel’s push into this market. It’s that there is now a dual-core version of Atom available. This should make for a nifty ultra-low power solution.

By Brian Fuller

In the storied history of semiconductors, each era finds vendors generally attaching their strategy to a trendy application segment to differentiate themselves. For years, IC vendors were “computer companies.” Then they were in the “communications” business and more recently they were all about “consumer.”

But the evolution of technology has forced a re-assessment not only of technology but of positioning – to the point where most vendors are attaching themselves to low-power, which spans application segments. Nowhere is this truer than in the programmable logic industry, which for years was seen as a power-hogging alternative to ASICs. In recent years, however, market pressures and product churn have prompted FPGA vendors not only to deliver more features and functionality but lower power, as power-consumption issues bedevil not only consumer applications but take on more global significance as the world worries about dwindling energy resources.

For FPGA vendors, the battle is now joined all the way from their R&D departments and foundry partners to their marketing armies. The available market for low-power programmable logic devices (targeting, for example, battery-based or power-sensitive designs) is estimated to be $670 million next year, rising to $855 million in 2012 or roughly 18% of the total programmable logic market, according to Rich Wawrzyniak, market analyst at Semico Research.

“There is a tremendous amount of interest in low-power FPGAs,” Wawrzyniak says. “The low-power phenomenon is something people are going to embrace, assuming they have the right price point and the right performance.”

Different approaches, same message

While the technology positioning may differ in vast and subtle ways, the approach among vendors really doesn’t: Just throw the kitchen sink at power consumption and find any way to sand down power, cork leakage and optimize architectures.

Three of the smaller FPGA vendors make an overt show of their low-power strategy: Actel, Silicon Blue, and Abound Technology (formerly M2000).

Silicon Blue, which unveiled its low-power iCE technology a year ago at Computex in Taiwan, focuses on the consumer market where low power and small form factor are paramount design considerations. Its non-volatile CMOS-based SRAM FPGA families claim to draw as little as 3 micro amps in sleep current and 3 milliamps of dynamic current. The iCE Mobile FPGA family, built in 65nm CMOS, also claims not to scrimp on size to achieve power goals with versions ranging from 100,000 to 800,000 FPGA system gates.

Silicon Blue compares its family to Altera’s Cyclone or Xilinx’s Spartan devices “except we’re optimized for power,” said Denny Steele, director of marketing and applications at Silicon Blue.

Because Silicon Blue is a startup, “Every time we have a design choice to make, we could optimize for low power. We didn’t have any legacy to consider” as older FPGA vendors do, he added.

At Actel, the differentiation comes at the technology level. Its flash-based FPGAs differ from SRAM-based alternatives from Silicon Blue, Altera and Xilinx. SRAM-based devices experience power spikes at boot-up, which can drain batteries. Flash-based devices do not require an external configuration device to support device programming, Actel notes. That can cut system power by as much as 70%, according to Christian Plante, director of product marketing at Actel.

“You use one chip, not two chips,” Plante says. An architectural feature Actel calls Flash Freeze can drop standby draw to as little as 2 microwatts, he says.

For an increasing number of battery-powered electronics applications, this can be a key differentiator as the flash technology helps reduce leakage at standby.

The low-power challenge is a bit more complicated at the larger, older FPGA vendors, Altera and Xilinx, which spent their early years bulking up on performance and functionality while attacking each other’s market share and nibbling away at the low-end of the ASIC market. The relatively new low-power mandate has forced them to attack the problem in myriad ways.

Xilinx began really attacking the power problem five years ago this month when it introduced its triple oxide process for the Virtex 4 family, says Matt Klein, a member of Xilinx’s technical marketing team who has focused on low-power issues for several years. Thin oxides are key to higher performance, but as they shrink to a dozen angstroms or so in thickness, electrons tunnel away and leakage soars. Xilinx and UMC offered three different thicknesses of the insulating gate oxide layers to lower both static and dynamic power by as much as 50%. Designers could trade off thickness in places where they had to have high performance transistors and places where they needed to optimize and lower leakage.

Since then, the company has taken a holistic view toward static, dynamic and i/o power issues. These includes offering four different transistors at 40nm (low leakage to high performance) for designer tradeoffs; more direct metal connections to cut capacitance and draw less dynamic power; adding mid-level clock gating to allow users to toggle clock trees on an off to manage power draw; making termination for memory interfaces dynamically switchable to select high performance or low power.

These and other steps—including process shrinks— have helped reduce power consumption significantly depending on product, sometimes up to 70%.

Altera first began to attack the problem through software, specifically its Quartus design environment. It implemented programmable power technology that allowed Quartus to bunch up high-speed paths together into logic array blocks (LAB).

“Then what Quartus is free to do is put some LABs into the normal high speed mode, some in low power mode and some can be turned off, so there’s no static power consumption,” notes Umar Mughal, manager for low-cost products at Altera.

In addition, the company has adopted similar tactics to rival Xilinx by focusing on power-hungry memory interfaces, which are getting wider and faster. The company has implemented resistors required for termination onto the chip itself, eliminating the need for extra circuitry. It can save power by as much as 20%, Mughal says.

Power’s future

The advances FPGA vendors have made in recent years have helped them expand into markets their former power-hogging ways once would have found closed. John Birkner, an FPGA industry veteran who is now vice president of strategic marketing for Silicon Blue, says net PCs are one hot application for low-power FPGAs because the electronics architecture and some standards are still evolving.

Few vendors are willing to tip their power-optimization strategies at this point. Leakage issues will only increase in ultra-deep submicron nodes where process variability will soar. Some surprisingly long-life, low-cost, small form factor battery technology could emerge to save the day, but don’t bet on it. FPGA vendors aren’t.

In preparing for the 32nm manufacturing node, Xilinx has assembled a cross-functional team from IC design to technical marketing to manufacturing which has identified no fewer than 30 concepts for reducing power at that future node.

“We’re pushing these ideas into the IC design group, and a number of them have already been accepted,” Klein says.

For Actel, “the keyword is integration,” says Plante. “Another way to put it is system partitioning will be one knob we’ll give to the end user to decide how to solve their power problems.”