Data Center Strategies
One of the most lucrative markets for processors is at the data center level. While improving efficiency in mobile devices is a competitive advantage because it affects time between battery charges, inside the data center it is measured in dollars. It costs some companies millions of dollars each year to power servers and to cool them.

That accounts for the rush to add virtualization into data centers, and the rising fortunes of both VMware and Citrix. It also feeds into the private cloud fortunes of companies such as IBM, and the massive reorganization underway inside of Hewlett-Packard. But at the bottom of the stack, powering all of this, there still has to be a processor. And it is the density of processors, coupled with inefficient use of them, which has caused this scramble inside corporate data centers for a way to cut costs.

Water cooling has returned as one way of dealing with excess heat—IBM re-introduced plumbing a couple years ago. A second approach has been to raise the temperature ratings for servers, which Dell instituted last year. But a third approach has been to reduce the overall amount of heat being generated in the first place by adding more efficiency into the data center on a macro scale.

AMD’s acquisition of SeaMicro gives a hint of what’s to come. SeaMicro has created a supercompute-fabric technology—the basis of a mesh network that can pull resources as needed. Virtualization companies such as VMware are heading in this direction, as well, with data-center load balancing. But a mesh network takes that approach one step further, dynamically adding more resources when necessary. This is the goal of cloud computing, and these are the latest pieces to make it work.

So can more energy be saved with that approach than trying to improve the individual pieces. The reality is that everything helps, and everything saves money. But it will take time to sort out exactly how much efficiency is gained by each part, and which investment will pay the biggest dividends. For more information, Mentor Graphics’ Barry Pangrle has taken a deep look at this subject.

For now, the good news is that work is underway to improve efficiency on all fronts. But don’t be surprised when the numbers start rolling in to find a series of rapid acquisitions as companies look to strengthen their competitiveness through combinations of more efficient technology.

Hidden Costs In Advertising
Most people are annoyed when they get cold-called for marketing their cell phones because they’re paying by the minute. But what is less obvious is the amount of power being consumed by the advertisements in free mobile applications. A team of researchers at Purdue and Microsoft found that up to 75% of the energy consumed by the applications is caused by ads.

Of particular interest is the number of “wakelock” and “energy” bugs. Just as there’s no free lunch, there’s no such thing as a free app—unless, of course, it’s open-source and monitored by an independent group with high-minded aspirations. The free apps available for smart phones generally don’t fall into that camp.

A white paper on the subject was published by Microsoft and details the energy consumption of popular games such as Angry Birds, Free Chess, as well as popular information sites such as the New York Times and MapQuest.

This is interesting research, partly because it shows how to detect software power issues, and partly because it shows how users can affect their own battery life even using the best-designed systems.

–Ed Sperling

By Mike Demler
Minimizing on-chip power consumption continues to be one of the greatest challenges facing SoC designers. Everyone who owns a cell phone has undoubtedly seen the effect on limited battery life firsthand, but the impact on the unseen compute servers in “the cloud” is even more severe, making total electrical operating costs greater than the hardware expense, according to AMD Fellow Stephen Kosonocky.

In his presentation at the recent Hot Chips Conference, Kosonocky shared the experiences of the AMD Llano APU (accelerated processing unit) design team and how they addressed these challenges. By integrating a quad-core CPU architecture with a GPU in Llano, AMD was able to eliminate the power that would have been consumed by chip-to-chip I/O, and increase the bandwidth between the CPU and memory by 3X. To achieve this integration, the team implemented a complex power management scheme that required power gating (PG) and dynamic voltage/frequency scaling (DVFS) throughout the chip, and the combination of hardware policies with operating system (OS) software interaction.

While advances in circuit design and process scaling have enabled higher levels of integration in multi-core SoCs, Kosonocky showed that another limiting factor must now be considered—device packaging. The Llano APU requires six separate power supplies, including two high-current supplies. Designers can’t just add more supplies, he said, because multi-layer packaging is typically limited to only four power planes of thick high-current metal.

Aside from the cost impediment of adding more layers, package and chip designers simply run out of space. Each power layer requires its own decoupling capacitors to suppress supply noise. These chip capacitors are mounted on the package during manufacturing, and they consume available space with surrounding keep-out areas. Also, whenever another VDD is added the impact is multiplied by the increased share of package resources that must be dedicated to the VSS return path.

With packaging constraints now limiting power delivery to the number of cores that can be supported in an SoC, designers are looking to circumvent the problem by bringing external voltage regulators on-chip. Voltage regulators fall into two classes—switching circuits that use capacitors or inductors to boost and scale voltages, and linear regulators. Switching converters are generally preferred for their higher efficiency, but they require large amounts of capacitive or inductive energy storage. New solutions for power management will require more sophisticated analog circuit designs, possibly combined with additional process steps to build higher capacity passive components that are compatible with nanometer scale CMOS.

Intel, meanwhile, is investigating the use of inductive “buck converters” for on-chip voltage regulation, according to Donald Gardner, principal engineer at Intel Labs. Inductors are commonly integrated into RF ICs for wireless applications, but the current carrying capacity and inductive density of such structures is inadequate for power circuits. By adding magnetic materials to a standard CMOS process, engineers can increase the inductance of copper interconnect that is typically used in power busses. On-chip integration of a switching voltage regulator enables the use of circuit techniques to increase frequencies by more than 100 times over off-chip devices, which reduces the total inductance required by a factor of 1,000. This makes a single-chip solution feasible, and also offers the benefit of providing much finer resolution for dynamic frequency-voltage scaling, because the output of a buck converter is a function of its duty cycle.

The magnetic materials that Intel is evaluating include CoZrTa (cobalt, zirconium, tantalum) and NiFe (nickel-iron). Gardner said that regardless of the material, physics limits the gain in inductance that can be achieved by coupling a single layer of magnetic material to a wire to only two times, which is insufficient. Building structures that completely wrap wires in two magnetic layers, as his team is doing, is more complex but yields inductance gain that is much higher—theoretically up to the increase in the added material’s permeability.

Figure 1 - Researchers at Intel Labs have added magnetic materials to a 90nm CMOS process to build integrated switched-inductor voltage regulators. (source: “Integrated Inductors with Magnetic Materials for On-Chip Power Conversion”, 2011 Hot Chips Conference)

Striped inductors (rather than spirals) are the “Holy Grail” of voltage converters, said Gardner, because the application of a magnetic field during the deposition process inevitably creates orthogonal “hard” and “easy” axes. The hard axis has the property of saturating too quickly, but laying an elongated stripe in the easy direction takes full advantage of the increase in inductance. By wrapping a thick copper wire with two layers of CoZrTa, and sealing the sides with magnetic vias to prevent flux leakage, Intel has seen inductance increases of more than 30 times compared to air-core inductors. Intel’s research has progressed to the prototype stage, with a 48-core test chip containing 8 on-chip voltage regulators that the company has distributed to researchers for further investigation of new power management techniques.

It is unclear how much additional cost would be incurred by adding magnetic materials to a fabrication process, but capacitors are an intrinsic component of CMOS transistors and are commonly used for analog/mixed-signal circuits and on-chip power supply decoupling. Elad Alon, of the University of California’s Berkeley Wireless Research Center, has explored this alternative.

In SC (switched-capacitor) DC-DC converters, Alon noted that efficiency is limited by conductance density, or the amount of current (or power) delivered to a load for a given voltage. A DC-DC converter could be built as a replacement in the same area as a typical decoupling capacitor, which he estimated to occupy about 10% of a chip, so that no additional cost would be incurred if the regulators delivered at least 10 times the power density that their loads consumed. A typical processor was estimated to consume about 1 watt per square millimeter, but the payoff would be even higher in a lower power mobile device, which typically has 10 times lower power density. The Berkeley Wireless Research team implemented a 32nm CMOS SOI (silicon-on-insulator) test chip to test their concepts, achieving about 80% efficiency at 86 watts per square millimeter—close to the goal of 1 watt per square millimeter for a processor SoC.

Figure 2 - Researchers at UC Berkeley's Wireless Research Center have proposed incorporating switched-capacitor DC-DC converters in a 3D IC configuration, to supply power over tha area of a processor SoC. (source: “Fully Integrated Switched-Capacitor DC-DC Conversion”, 2011 Hot Chips Conference)

Higher capacitance per area yields higher efficiency in SC converters, and losses in the bottom plate parasitic set the maximum efficiency that can be achieved. The use of dense trench capacitors, such as in DRAMs, has been shown to offer the potential of about 90% SC regulator efficiency. Alon proposed that SC voltage regulators could be integrated into about 10% of the area of a DRAM die, and used to supply the power in a processor-memory 3D IC package. Alternatively, because the power regulator circuits can be built in older, less-expensive process technologies, a dedicated converter chip could be stacked and connected through TSVs (through-silicon vias) to distribute power over the entire area of a processor die.

By Ed Sperling

Going Vertical
Now that everyone has gotten the energy-efficiency message down pretty well, the next step is to apply that to specific markets. That’s beginning to happen, too.

A leaked product roadmap from AMD shows machines with all-day battery life and a focus on everything from ultra-mobile notebooks to tablets.

Intel is refining its own message to go after specific markets, as well. The company has created a small-business cloud platform on a pay-as-you-go basis. Given the amount of energy consumed by underutilized servers, this is a huge efficiency play—as well as a way of Intel sidestepping the PC OEM for its share of the profits. 98

Companies such as Tensilica, meanwhile, have been focused heavily on low-power communications, most recently in the LTE and LTE Advanced space. And ARM and MIPS have been divvying up targeting a variety of specific markets. ARM has been focused on mobile devices and a slew of vertical applications ranging from medical devices to other consumer electronics is well documented. Likewise, MIPS has focused on set-top boxes and Android-based devices.

Lowering Carbon Dioxide
The International Energy Agency issued a report today that carbon dioxide emissions must be eliminated from electricity generation to limit the rise of global temperature to 2 degrees Celsius.

The report noted that total output of electricity and heat grew 55% between 1990 and 2008, but corresponding CO2 emissions grew 64.5% in the same period. The report recommends greater efficiency in lighting, heating, cooling and information technology, and powering with renewable sources of energy, nuclear, and carbon capture and storage.

This is good news for the electronics industry, in general, and the low-power engineering portion in particular.

By Ed Sperling
AMD jumped into the low-power market with a new version of its Fusion chip for the tablet market, which the company claims can reduce energy consumption by 40%. That puts AMD squarely in competition with Intel’s Atom, ARM’s Cortex A9 and A15, a swath of MIPS chips aimed at Android, Apple’s A4 and probably some others that sources say will be produced for localized markets. AMD also rolled out an updated parallel processing development kit, which is absolutely essential for performance.

The U.S. Air Force is developing a new ultra low-power RF transceiver to preserve battery life in military sensors, including radar and infrared cameras. The less power drawn and the lighter these devices can be made, the smaller they can be designed and the longer they can be in the air.

Toumaz, a U.K.-based developer of low-power telemetry technologies, introduced an ultra low energy radio for wireless sensor networks. The company says the device can run at 1 volt using a single button-sized cell battery and consume less than 3mV of continuous power. That should make for some interesting application possibilities.

By Ed Sperling
Microsoft is looking for 16-core servers for future data centers using Intel’s Atom and AMD’s upcoming Bobcat processor lines in order to lower power consumption in data centers. The announcement, made at the Linley Data Center Conference in San Jose this week poses an interesting dilemma for Intel and AMD—as well as challenges for ARM and even Microsoft.

On the Intel and AMD front, the big question is how such a shift would impact revenues, given the fact that both companies have used the power-saving lite versions of their processors in much lower-cost devices such as netbooks. While some data centers are experimenting with Atom-based arrays for servers, the real savings have come from virtualization to improve server utilization, and cloud-based strategies to quickly ramp up and ramp down compute capacity as needed.

Virtualization has been extremely successful. Most large companies have adopted it to some extent because it costs money to power and to cool a server, whether it’s utilized at an optimal 60% to 85% or whether it’s running at 5% to 15% utilization, which was the industry average prior to virtualization. The problem for Microsoft was that the virtualization was done using VMware and Citrix software, not Microsoft software.

Without virtualization, it’s not entirely certain whether many applications will be able to natively take advantage of 16 cores, considering most currently don’t use more than one or two. In fact, the main applications that can be effectively parallelized are databases, graphically-oriented applications such as Adobe Photoshop, and highly computational scientific applications, where the biggest threat to Microsoft and Intel is Nvidia.

Microsoft’s approach will likely be a more effective management of virtualized applications across those cores so that cores can be turned on and off as needed, but it’s certainly not the only company that sees that opportunity. Virtualization currently uses all the cores indiscriminately, but much more intelligence is being added into the virtualization and middleware layer to cut energy consumption.

For ARM, that means even greater engagement with both Intel and AMD, where it will have to push lower power while defending its performance and the competitiveness of Linux. Given ARM’s grassroots type of ecosystem marketing, it remains to be seen whether it can rise up to the din of the marketing machines of its new competitors. Lower power consumption is a good story, but in the enterprise so are performance and deep relationships.

The old adage that no one ever got fired for buying IBM can now be applied to Microsoft, Intel, AMD and to a lesser extent VIA. Most IT departments have no history with ARM, except in handheld devices, and IT is one of the most conservative purchasing groups on the planet because the stakes of making a bad decision can be monumental. Breaking into the mobile market takes months. Breaking into the IT world can take years, and sometimes even decades. This isn’t a battle fought on technological merits. It’s like a medieval siege. And while ARM may meet the technology challenge, it remains to be seen whether it can meet the long-term marketing challenge.

In this part of the market, the adage about IBM is still true. IBM’s mainframe sales are up, in part because mainframes are still the most secure and effective virtualization environment. IBM invented virtualization in the 1960s, incidentally. And on its newest machines it’s offering water cooling once—which can further cut power consumption because it costs less to cool.

By Ann Steffora Mutschler
Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon germanium, gallium nitride, and aluminum nitride.

Most promising is SOI, already in use by IBM and AMD, which uses a layered silicon-insulator-silicon substrate instead of conventional silicon substrates to reduce parasitic effects and improve performance. Specifically, SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide, offering improved performance and diminished short channel effects in microelectronics devices. SOI can be implemented in two forms: partially depleted and fully depleted.

Jamil Kawa, group director of R&D in Synopsys’ implementation group, emphasized that SOI is not new. “It has been with us for a long, long time. It has a lot of proven benefits, yet it never became mainstream.”

He explained that SOI could be compared to bulk CMOS by a rule of thumb: you can buy either a node in power for the same speed, or a node in performance for the same power. For example, comparing 90nm SOI to 90nm bulk, if they are running at the same clock frequency, the 90nm SOI will have the lower leakage characteristics of the 120nm bulk. Another way of looking at it is if the SOI is operating at 90nm with the same power budget that a bulk is allowed to consume, then it can give the performance that the next-generation (65nm bulk, in this example) will provide.

While it appears to be a simple formula that is carried from node to node to node, SOI didn’t it catch fire as everybody thought it would mainly because of cost. “Given the lack of wide-scale adoption, the cost of initial wafers was more expensive and cost is extremely sensitive in our industry,” he explained.

SOI chip. Source: IBM

A second obstacle to SOI adoption has been the history effect inherent in the technology. There is no substrate with SOI. It is oxide. Therefore, charge accumulates and has nowhere to go, and this alters the behavior of the device over time. Guardbanding is used to get around the history effect. “If you want to go conservative by guardbanding 15%, all the advantages in speed that you got by going SOI you’ve given up by going conservative. There are techniques to alleviate that, but bulk has remained the easy way out, a proven technology, cheaper, with a lot of momentum in terms of history of use,” Kawa noted.

SOI is gaining renewed interest, however. At 20nm and 15nm, CMOS leakage is a big problem.

FinFETs are being looked at, sometimes in combination with SOI, as well. “At 15nm, you don’t have too many choices. Bulk is more or less dead. If you insist on going with planar, you go the SOI way. Or you go the FinFET way. There is also a third variation, which will most likely gain hold, which is FinFET on SOI. Nothing is ruled in or out yet, but the excessive variability of bulk at extremely advanced nodes is giving a second life to SOI. The verdict is still out so I’m not advocating one course or the other, but the move toward FinFETs on bulk or FinFET on SOI is clearly the way to go in terms of leakage control,” Kawa added.

Material effects on tools
While it might not seem obvious, the choice of process can affect EDA tool development to some extent. Michael White, product marketing manager in the design to silicon division at Mentor Graphics, said that as the International Semiconductor Development Alliance (ISDA) was introducing SOI, there were some unique physical verification activities/checks that needed to be done from a physical verification-DRC perspective that drove the need for parasitic extraction.

“We just want to make sure that the foundries have solutions for Mentor regardless of the process technologies they’re offering to the end fab-lite or fabless customers, so we work very hard to make sure they have decks DRC, LVS and so on. Our tools need to support any functionality required for those alternate flows so that the foundries have complete flexibility to offer whatever process technology they want. We are process-technology agnostic. We just want to make sure that there’s a solution out there if someone thinks it’s appropriate and interesting to use some new process,” he stressed.

White noted that materials and their characteristics have always been a concern. That automatically flows up into the design side from the IDM or foundry as they define the physical verification checks needed to ensure manufacturability. “That’s always been part of the discussion,” he said. “The complexity of the processes due to advanced materials and lithography is going up, and more of that is being captured as physical verification checks and that is driving the complexity of the DRC/LVS checks that folks have to go through now. And because Calibre is the golden signoff tool used by the foundries, we actually get to see that growth in complexity—and it is exploding.”

Specifically, the number of checks was going up 20% to 25% node over node. At 28nm the number is going up faster. Since 28nm was introduced, the industry added about another thousand DRC checks, driven in part by increased complexity in the process. “It’s not just a materials science thing,” said White. “It’s also lithography and other effects that are driving this explosion.

In terms of CMOS vs. SOI, he said the DRC decks seem to be more complex for SOI, and there are more checks in the DRC decks for bulk CMOS.

But moving from CMOS to SOI isn’t so simple, said Matthew Hogan, technical marketing engineer for LVS in Mentor’s design to silicon division.

“If your foundry doesn’t offer SOI then it’s a daunting task of, ‘Do I really want to switch foundries?’ One of the things we are finding from a physical verification perspective, in terms of exploding design rules, is more attention being paid to using some more elaborate checking mechanisms that can actually go in and have a look at the context of the design, Now, instead of having two or three voltage domains, we might have 30, 50 or 100. We are trying to have a look at given the circuit that’s being designed. If I power off, or put a region of the circuit into a standby mode, do I have all of the flip-flops and transistors configured so that it can maintain its state while it’s in this low-power mode? And do I have the correct spacing that I need for the different parts of the design? The verification has definitely become more complicated and the attention to detail has increased greatly for eking out the most power/performance from this technology,” he said.

At this point in time, it’s really about working closely with foundry partners until the time is unavoidable to make the leap to a new semiconductor manufacturing material.

By Ed Sperling
Microsoft will develop its next version of Windows for AMD, Microsoft and ARM SoCs. The emphasis is on SoCs, and the focus of SoCs has been on two things: power and the reusability of existing and commercially developed IP.

This is an interesting challenge for Microsoft, as well as for Intel, AMD, and ARM’s slew of partners. A general-purpose OS takes a lot more code to create—and it takes a lot more power to use—than a real-time operating system or an embedded version. The result is greatly reduced battery life and more time with a plug in the wall. Even open-source Linux has the same problem, which is why companies such as Mentor Graphics offer a slimmed down embedded version.

The big question for architects of these SoCs will be one of priorities. What takes precedence? Is it processing power? Is it performance? Or is it segregation of more efficient code for individual cores.

Microsoft’s announcement doesn’t address these kinds of issues. Intel has said next to nothing other than a canned statement from Douglas Davis, VP and GM of the tablet group: “…what is so exciting is how our two companies will be able to match a tailored, low-powered operating system with future generations of our popular Intel Atom processors…”

And comments from ARM, and ARM customers Nvidia, Qualcomm and TI have been no more enlightening. This isn’t a simple problem to solve while maintaining backward compatibility with bloated applications developed when power efficiency were far less critical than ease of use and connectivity. And it’s not one that anyone is likely to be talking about for at least a year or more. But when they finally do start talking, it will be very interesting to hear how these companies will position Windows and its very large code base.

By Ed Sperling
The processor wars have started again, but with a completely different focus this time. It’s no longer all about performance. The real differentiator is power.

ARM, which has always been about lower power, began showing off a way to dramatically reduce power in its chips with a cache coherency layer. This is a big step forward in how software interfaces with the hardware because it can slash the number of calls made to the processor to check things. Think of this as a sophisticated scheduler for one or more cores as well as a bridge between the CPU and GPU.

ARM’s approach will certainly work well in its core market of mobile devices and set-top boxes, but it also is beginning to gain traction in the data center where lower power—particularly for Linux-based applications—are worth millions of dollars in power each year.

MIPS has a similar strategy with its own chips, not to mention its own coherent processing system for multiprocessing. Expect the two companies to compete in the same markets with roughly the same approaches, with wins trumpeted on both sides–particularly in the set-top, mobile and automotive worlds.

In the x86 world, AMD this week began showing off its next-generation low-power chips. The new Fusion Accelerated Processing Units combine the CPU and GPU onto the same die, which can significantly reduce the amount of power needed to drive signals off chip. With some slick caching technology, that also greatly reduces the overall power draw while also boosting performance.

Intel will respond early next year with its own lower power chips, which are code-named Oak Trail and expected to deliver up to eight hours of battery life.

By Pallab Chatterjee
Most microprocessors have shifted to new small geometry processes in order to be the most efficient at power and high performance. However there is always a trade-off between power, performance and area (PPA) for semiconductors, and this is especially relevant for processors. In the current design space, processors are created as general-purpose products, but they are generally put into user applications that need to be optimized for either power or performance.

The main CPU processors, such as Intel’s iX series, AMD’s Phenom II series, and Nvidia’s video GPU products are routinely not operated at their standard performance specifications. They are either over-clocked or operated at alternate cores voltages in the end-user applications to increase performance and data throughput. Because the processors are operated in a non-standard condition, the design requirements have to include acceptable limits for these additional modes of operation. The chip cores can either be run at a higher voltage—up to 50% more than the standard voltage. The main clock rate for the chips, the core master clock, may be as high as 50% faster than the nominal clock frequency. To support all of the other functions such as thermal management, I/O and memory interface, and the standard bus handshake, the chips have to have additional control logic to support operation at different performance specifications.

Nvidia’s GPUs support additional power supplies modes and connections as standard. The nominal core voltage is 1.2V, and can be increased up to 1.4V. This configuration alone does not maximize the performance. Additional adjustment of the over-clocking of key portions of the chip need to be performed both with and without the voltage adjustment. This over-clocking needed to be balanced for which portions of the chip get the performance increase so the design does not overrun the local memory or the bus interface and introduce wait states. When these performance changes are made, they are a static change thath affects the overall configuration of the graphics board and fan.

Parameters that can be adjusted include: the FSB, memory bus, AGP bus, PCI-E bus, GPU core clock, GPU memory bus, memory timing registers, and hardware-specific performance tuning registers. As these changes affect the dynamic power of the board, fan and cooling controls are included to help keep the design at the nominal die operating temperature. The higher-performance operation can increase the die temperature by as much as 20C if upgraded cooling is not applied. Due to the complexity of the performance enhancement, the voltage scaling and clock scaling are no longer done by just putting in a different regulator and a different crystal.

To control these changes and make sure that the chip still operates in a safe design area, Nvidia has produced a control software program nTune for end user to adjust these parameters.

General purpose CPU processors have a few more data dependencies than GPUs, but have the same customer performance issues. Since CPUs were introduced people have been pushing the performance aspect of the PPA tradeoff. Just like GPUs, you can adjust the core voltage, and also over-clock portions of the chip. Unlike the GPU, the setting are not static and do not produce the same results under all data conditions. For this reason, the higher performance processors now have automated algorithms for performance improvement based on the data set.

For the Intel processors this is part of the “Turbo Mode,” which does an automatic over-clocking for the duration of the processor operations that need the higher performance. The power envelope for the processor design, including the thermal management, has to take into account these dynamic over-clock modes in addition to traditional systematic over-clocking. Unlike most SOCs, processor designs and most multi-core embedded designs have data-dependent timing and performance characteristics as well as user adjustable applications ranges.

By Ed Sperling
Intel rolled out an ultra-low power Atom processor for smart phones and tablets. The company claims it can cut power consumption during idle by more than 50 times over previous versions to as little as 100 microwatts, but mileage will vary. In some cases it will vary greatly. For example, it will only offer about 4 to 5 hours of browsing, and the numbers go down from there depending upon how much graphics-intensive computing is involved. The bottom line: This chip sleeps well and it wakes up with a roar, but beware of what you feed it.

By way of comparison—and competition—ARM’s Cortex M0 processor idles at 85 microwatts, but the software stack is significantly thinner. Legacy has its advantages–namely its ability to run everything under the sun–and its disadvantages, which are namely the same as the advantages.

AMD is pushing into the low-power space, too, although it’s not exactly clear where the company’s embedded chips will play. At the very least, it will be more power hungry than a smart phone. The new chips will have power envelopes as low as 8 watts, which isn’t something you want to stick in your pocket. It may be something you want to include in a tablet computer, however.

Apple bought Austin-based Intrinsity, which makes design tools for turning up the clock on processors without increasing the power. Industry insiders say the real reason was the engineering talent. Speculation is rampant about which companies Apple will displace as it continues developing its SoCs—and why. Incidentally, Apple’s Web site has no mention of the deal.