By Ed Sperling

Jan. 14, 2010—The current raft of companies emphasizing low power is growing. What’s changing is it’s no longer just limited to the portable market, where battery life is critical, or even the corporate data center, where reducing power on thousands of servers can save big bucks.

Via Technologies this week rolled out a compact server for the home office and small business market that utilizes its own 64-bit low-power processors and chipsets, which normally are used in laptops.

AMD’s ATI video card unit also unveiled a new GPU that draws significantly less power than previous versions. In idle mode, it draws only 15 watts, and at maximum power it runs only 64 watts. Given the fact that this is a high-definition graphics engine attached to a plug, this is a major step forward—particularly in the PC gaming world where power carries the same bragging rights as horsepower on a sports car.

Media Excel and Texas Instruments, meanwhile, are collaborating on low-power versions of network-based transcoding electronics for HD, scalable video. This deal is aimed at the MobileTV, WebTV and IPTV world, which has steadily been gaining adherents even if it hasn’t replaced regular television. Most of these units rely on a plug, although they have slipped under the radar screen of regulators looking to cut power consumption in large-screen TVs.

By Pallab Chatterjee
Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology.

There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions from Nvidia, Samsung SLSI, Imagination Technology, NetlogicMicro, Broadcom, and Qualcomm. To address the usability specs required by e-readers, mobile Internet devices and other mobile information products, a new compute architecture was needed that did not just rely on “function disabling” as a power reduction technique. All of these companies introduced designs that are focused on multicore architectures, where there is complete functionality available at all times even though the process has been optimized for low power.

This low power optimization has to do with custom library design creation, modification of internal clocking schemes, datapath and buffer optimization, memory segmentation and placement, and most importantly dynamic control of the design’s power use and speed based on the data content of the information being processed on a per-packet basis. This re-architecture of products was the key enhancement with the new dual Cortex Nvidia Tegra, which is targeted to e-readers and tablet PCs, as well as the high-performance Alchemy multicore and multithreaded processors for automotive and navigation applications, and the many new video and communications appliances from Broadcom and Qualcomm.

The basis for most of these systems are ARM processors cores (A8 or A9 primarily) or MIPS cores. This shift has allowed both a performance increase in the end systems as well as a nearly doubling of the operating battery life.

The second prevalent low-power methodology is the segmentation of design to a CPU and a GPU rather than a single compute engine. While the initial impression is, this takes more power, the GPU is actually more power-efficient on graphics and some video data than the CPU, and on general use functions, the CPU is more power-efficient than the GPU. For most of the smart phones and media processing chips, this approach has replaced bigger single-processor cores with clock-gating and multi-voltage device process solutions.

These architectural changes were implemented to address both the data dependence of the power use and the yield-process variability of sub-wavelength manufacturing. As most of the applications have a very thin and small form factor, they are bound by a fixed or diminishing power envelope. To address the longer term of operation the components can lower the operating voltage, but this does not take into account the associated reduction in performance in the power envelope that is associated with it. In order to address this aspect of design, the mobile handset and mobile computing requirements have driven to the smallest geometry process flows available.

The utilization of these processes (45nm and 40nm, currently) requires restricted design rules, restricted topologies and limited device size diversity to yield well. These designs are optimized with new RTL and physical libraries, new floor plans, and power routing to highlight the data path symmetry that is required by the data sets being processed. Examples of this are new 3dmedia processor in 40nm by Samsung for mobile phones that utilize the IMG Tech 3D video and graphics engine and a high-performance ultra low power ARM CPU.

The distributed multicore approach also has been utilized in high performance for lower power products. AMD/ATI introduced the 5970 Radeon graphics card at the Consumer Electronics Show. The card has two GPUs and is a Direct X11 product with more than 4.6TFlops of peak performance. The restructuring of the device/cell library, its reliance on proven 40nm bulk CMOS processing and the use of GDDR5 memory allows the product to operate with a peak power of about 300 watts but only requires 51 watts for nominal operation. The design was optimized for power and a data control flow to support the 3200 parallel stream processors and the 160 texture units. Dynamic power is managed based on how many streams and texture units are needed at any time based on the contents of the data that being processed on any given cycle.

Most of these new systems are targeting use of Samsung’s low-power DDR3 memory, which operates at 1.3v vs. 1.5 volts and offers higher densities than DDR2. These higher-density, low power solutions can provide in excess of 35% overall power footprint reduction for the design, if used with 32nm low-power flash memories in SSD applications rather than rotating media.

The takeaway from CES this year is that architectural engineering and new firmware control methods are now seen as essential to address the functional requirements of the new mobile communication and processing platforms. This is an intelligent shift from recent years, when only feature size reduction and blind tool-based selection of power gating and power routing were in vogue.

By Cheryl Ajluni
Much to the dismay of anyone who recently splurged on a new Blu-ray disk player or flat-panel HDTV, 3D stereoscopic content has become the talk of the town or, in this case, the 2010 Consumer Electronics Show.

Sure, we’ve been down this road before. After all, 3D is nothing new. But it now appears ready to explode into the home in the form of 3D television (Figure 1). Bolstered by what some have termed the “Avatar effect,” many in the electronics industry are hoping the technology will spur some much needed market growth. As Eisuke Tsuyuzaki, chief technology officer at Panasonic explains, “We need top-line growth right now, we need something to kick us out of where we are today, and the thing that’s going to get us there is 3D.”

Figure 1. The Panasonic 152-inch Full HD 3D plasma display features a new plasma display panel (PDP), developed with quadruple luminous efficiency technology to help deliver an immersive experience to viewers. It creates a true Full HD 3D world by faithfully reproducing 3D content such as Hollywood 3D movie titles.

Unfortunately there are many challenges that lie ahead for 3D stereoscopic content—whether it’s intended for a television display, Blu-ray disks, games, live broadcast channels, or any range of handheld devices. 3D production can be very expensive and complex. Additionally, creating 3D content requires a tremendous amount of computing power and that, according to Paul Otellini, president and CEO of Intel, means that powerful microprocessors must play a central role in the transition to 3D content creation. But does the increase in 3D content and computing power also translate into increasingly power-hungry devices?

If 3D HDTV’s draw more power will consumers be as inclined to jump on the 3D bandwagon? Will they really be willing to trade the benefits of the 3D experience for the price of a new television and the accompanying higher electricity bill that will follow each month? What if the 3D content is embedded in a battery-operated handheld device? Would consumers welcome the 3D experience at the price of shorter battery life? Somehow this just doesn’t seem like the kind of tradeoff economy-weary consumers are going to make. So, energy efficiency remains a big selling point, but where will it come from?

Otellini thinks the answer may lie with the creation of more efficient microprocessors—something his company just so happens to have worked on in its attempt to aid in the transition of computing from the computer and into the world at large. As he pointed out in his recent CES 2010 keynote speech, “Computing is no longer confined to your computer—it’s everywhere. Advances in connectivity, intuitive user interfaces, immersive content and computer chip performance have allowed computing to move into new areas. Computing moving into all manner of devices and experiences all around us improves our personal productivity and enjoyment.” The recent advances in 3-D stereoscopic content are just one example of how this vision is being realized today.

Building a Low-Power Foundation
Powering this vision will be a slew of efficient low-power processors, like the ones Intel created and recently introduced at CES. Here it announced more than 25 Intel Core processors (the Intel Core i3, Intel Core i5 and Intel Core i7 processors) for laptops, desktop PCs and embedded devices (Figure 2).

Figure 2. The new Intel Core i3, Intel Core i5 and Intel Core i7 processors range from dual-core to quad-core models and run at frequencies between 1.06 GHz to 3.46 GHz.

The 2010 Intel Core processors are all based on 32nm, second-generation high-k metal gate technology and feature Intel Turbo Boost technology, which can automatically boost a PC’s processing power to adapt to a heavier workload (e.g., for demanding HD and 3D video creation). Most of the new processors have the graphics processor integrated right on the CPU package, along with an integrated memory controller, thereby eliminating the need for a separate graphics and memory chip connected to the main processor. The result is a dramatic space savings, lower power consumption and better cooling for the integrated chips, along with enhanced overall performance.

Intel’s new processors are also energy efficient. The Intel Core i3-330M processor consumes just 25W of power, while the Intel Core i5-520UM mobile processor uses a mere 18W. Additionally, some the company’s new embedded processors use as little as 35W of power.

Last month, AppliedMicro also introduced energy-conscious processors—actually versions of its Power Architecture 405EX, 405EXr, 460EX, 460EXr and 460GT microprocessors that had been optimized for low-power consumption (Figure 3). Nevertheless, the effect is dramatic—a 40% decrease in power consumption and an improvement of 20% in typical power consumption for embedded systems without having to sacrifice performance. This allows system designers to reduce their energy consumption and meet environmentally-conscious goals, while still being able to deal with the increasing performance demands on embedded systems caused by things like the exploding use of video-based applications.

Figure 3. AppliedMicro’s Power Architecture 405EX now offers up to 40% less power consumption for embedded systems.

While compute power is critical, the role of the graphics processor cannot be overlooked when it comes to 3D. In Intel’s case, it chose to integrate the graphics processor directly on the CPU package. AMD has opted for another approach, launching a series of next-generation ATI Radeon graphics cards with Microsoft DirectX 11 gaming support for stereoscopic 3D and HD gaming on notebook computers.

Figure 4. By breaking the teraFLOPS barrier, the ATI Mobility Radeon HD 5870 is the world’s fastest mobile graphics processor. Processors like this, coupled with advances like the Blu-ray Disc Association’s Blu-ray stereoscopic 3D standard, will one day soon allow consumers to enjoy high-fidelity 3D entertainment that was once reserved only for theaters.

According to AMD, the new ATI Mobility Radeon HD 5800/HD 5700/HD 5600 and HD 5400 Series graphics processors are among the most technologically advanced and feature-rich mobile GPUs it has ever created (Figure 4). They not only give notebook users full DirectX 11 support, but also deliver ATI Eyefinity multi-display technology, HD multimedia capabilities, and feature ATI Stream technology designed to help optimize Windows 7 notebook performance. ATI Eyefinity multi-display technology enables super-high-resolution panoramic computing for notebooks, enabling mobile users to harness up to six monitors for improved gaming, productivity and entertainment.

A key feature of the new AMD graphics processors is energy efficiency. Thanks to an improved processor design and new 40nm process, they feature four times the performance-per-watt efficiency over the last two generations of ATI Mobility Radeon Premium graphics. Next-generation Vari-Bright technology (used for optimizing notebook display brightness) delivers up to 50% power savings over the previous generation’s software based approach. Additionally, the processors experience lower idle power and have platform-independent graphics switching technology which helps to save power while offering efficient switching options.

Advancing 3D Entertainment
With compute power and energy efficiency in check, attention quickly turns to standardization. For 3D to really take off, interoperability of products will be essential. That’s where standards like the Blu-ray Disc Association’s Blu-ray 3D video standard comes in. Finalized at the end of last year, it employs an amended H.264 codec called Multiview Video Coding (MVC) to deliver stereoscopic 3D images. Surprisingly, it uses only about 50% more data than equivalent 2D media. This is a certainly a good step toward increasing demand for the technology, as are the recent announcements of 3D television testing in Finland and DirecTV’s plan to launch its first 3D channel for the United States in early 2010.

But, whether or not this means that “older” technologies like Blu-ray and HDTV will one day become obsolete still remains to be seen. One thing is for sure, the real excitement will be in seeing how the combination of energy-efficient computing power and 3D stereoscopic content comes together to inspire new applications in everything from notebooks, smart phones and gaming to cameras or whatever other handheld device can be envisioned in the future.

By Ed Sperling

Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together.

The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take advantage of all that extra real estate. But more functionality layered onto a die also increases the demand for power—or makes the development of the chip much more complicated.

One way to deal with all of this is to drop the operating voltage across the chip. But decreasing the supply voltage has its problems.

“If you decrease the supply voltage too much, then circuits don’t work anymore,” said Mark Bohr, an Intel senior fellow and director of process architecture and integration. “There isn’t enough signal-to-noise ratio to make it work. But there’s also no silver bullet for this. One of our ongoing challenges is to scale transistors and operating voltage.”

How to do that is a rather difficult task, however, and engineers and scientists working on the most advanced chips on the planet say it will remain extremely challenging at all future nodes.

“There is a minimum voltage any ‘charge-based device’ can work on,” said Jan Rabaey, professor of electrical engineering and computer sciences at the University of California at Berkeley. “It equals 2 (kT/q) ln(n+1), where n is the subthreshold slope factor of the device. At room temperature and a normal device (n=1.4 – 1.6), this translates to approximately 50 mV. Given the fact that there is margin needed for reliable operation, a practical minimum voltage would be around 100 mV. There are some ways to lower this. High k is not one of them, as the main purpose of that is to reduce gate leakage. More effective is to reduce n (which is 1 for an ideal bipolar device).”

Power modeling, power islands
One solution is power modeling, which is almost required as more power islands are added to a system on chip. The advantage is clear—if the majority of functions on a device can be powered down or even off when they’re not in use—then the amount of power consumed by the chip can be dramatically reduced.

But complexity increases with the addition of power modeling. It’s harder to design, to route traffic and prioritize that traffic.

“Even at the architectural level people are reluctant to use multiple power domains in their design because they don’t want to complicate their system,” said Prasad Subramaniam, vice president of design technology at eSilicon.
”They don’t want to have multiple voltage regulators. A chip already requires two voltages, one for the I/O and one for the core. They don’t want to go beyond that.”

Verification adds another level complication. It’s much, much harder to verify the chip because that verification has to be done utilizing every state of every different function and in every different possible sequence.

“This is major problem,” said Srikanth Jadcherla, Synopsys’ group director for R&D for low-power verification. “But it isn’t a tools problem. The tools for verification are there. It’s a methodology and mindset shift. Engineers are not used to doing regression and debugging in this way. You have to change the whole thing under you.”

This is easier said than done. Tools can be swapped out, and even when there is more training involved that can be a relatively painless step. But changing a methodology is radically different.

“If there are six power domains and on/off nodes, then you have 64 possible combinations (more if there are more states than just on and off). You have to make sure the chip still functions in each state and that you can get out of one state and into the next,” said Jadcherla. “RTL engineers never bothered about system states before. Now they have to know the major states. A smart phone has a phone mode and an e-mail mode and a camera mode, so you now need to do mode-based testing. This is not something we see in the design community yet. Low-power verification must be done in the context of the system.”

New materials, methodologies and technologies—and challenges
At least some of the problems will be dealt with using new materials. While Intel added restrictive design methodologies at 45nm, IBM and AMD changed substrate material from bulk CMOS to partially depleted silicon on insulator (SOI). At 28nm and 22nm, IBM and its ecosystem—which includes AMD—are looking at restrictive design rules and Intel is exploring the possibility of adding fully depleted SOI.

Intel looked into partially depleted SOI technology about the time that IBM did and ruled it out because the cost was too high and the performance benefit based upon that cost was limited. But Bohr said the company is now looking into fully depleted SOI technology. There is no determination whether Intel will use that technology at future nodes, but it remains a possibility.

The difference between partially depleted and fully depleted is that in a fully depleted model the source and drain in a transistor are depleted down to the oxide. The channel is subsequently deeper, which in turn provides better insulation. With SOI, chipmakers typically can get a boost in either performance or power. But with performance now far less of an issue in most applications than power, the bulk, the focus is on SOI to save power.

“SOI technologies have a slope factor of approximately 1.2-1.3,” said Rabaey. “There is currently a lot of research on the development of devices with an ‘n’ smaller than 1 (such as Tunnel-FETs or TFETs, and other hetero-devices). This would allow for lower voltages. Right now this is purely experimental though.”

Conclusion
There is no simple answer to how power issues need to be addressed. The clear implication, however, is that design will become more complicated in some areas even as it becomes simpler in others. Restrictive design rules will limit what design engineers can do, but they will open up all sorts of possibilities for power modeling and engineering that never existed—or needed to exist before.

As IBM’s top engineers have said repeatedly, each new node requires some group to feel the pain. In the past, much of that pain was absorbed in the manufacturing and foundry process. The next phase will hit the design engineer and the verification methodology. After that, it’s anyone’s guess.

By Ann Steffora Mutschler

For budgetary and ‘green’ motives, enterprise IT customers are demanding higher energy efficiency from their servers. This ultimately rests on the shoulders of the processor designer as the MPU is a significant source of power usage.

Interestingly, the hidden and ugly truth is that for most data center managers, the cost of electricity for that data center is never put in their budget. As a result, they usually don’t get credit for saving electricity, said Carl Claunch, vice president and distinguished analyst at Gartner. “Typically, the building budget handles the electricity for the entire building and the data center is just swept in there.”

What that means for the data center manager is there may not be a direct incentive for energy efficiency. “Typically, it’s that you’ve reached some wall—you’ve hit a barrier where now you’re going to have to upgrade the electrical service because the total energy you’re using maxes out the wiring you’ve put in place or cooling,” he said.

Often, heat is more of an issue. “Even if you have the total capacity to remove the heat, if you get above a certain amount of energy per rack of servers, you start getting poor reliability because of hot spots. Even though in total you could remove the heat, you’re not doing it efficiently enough across the entire room to not have some machines roasting or melting, dripping slag on the floor – so you have to do something. And typically solutions to those spot problems escalate rapidly as you put in specialized things and now that really does affect your budget, Claunch said.

“These kinds of tactical situations that crop up where you can avoid expense or avoid having to build a new data center through getting more efficiency—that’s a good thing. I think, in general, people would like to do the right thing, even though it’s at a lower priority in terms of affecting your buying behavior. But there is this attitude that says, ‘if everything else is pretty much equal, why don’t I get the thing that uses less energy?’ There is an interest in that, but it doesn’t have a huge effect on people’s selections unless they hit these tactical issues.”

Demand for efficiency

The demand then comes from the engineering part of the server vendors back to the processor designers.

Arvind Narayanan, product marketing manager for Mentor Graphics’ place and route tools, said the costs of electricity and cooling are two key factors that are limiting server farm growth. “Data center energy consumption is escalating each year, and power and cooling cost have increased exponentially in the last decade.”

However, he said, energy costs are not the only reason low power design is critical for the data center. “Power consumption for traditional microprocessor architectures is increasing faster than performance, making it near impossible to keep CPUs from burning themselves up. Consequently, the race for faster clocks has reached a point of diminishing returns, and microprocessor makers have been forced to employ multicore architectures, which are inherently more power-efficient than increased clock speeds, to increase computing throughput.”

In the thick of the processor design, Advanced Micro Devices just announced this week three new members of its six-core Opteron processor family that are meant to address rising demand for balanced systems with increased performance and greater power-efficiency for cloud computing and web serving environments.

John Fruehe, director of business development for AMD servers and workstations, said high efficiency (HE) processors comprise 20% to 25% of the company’s server business. “The energy efficiency angle for our processors has gone from being a small part of the business to a much larger part of the business so much so that we are finding now that we are sub splitting the low power into the mainstream power (HE) and then a very highly efficient product that has an even lower [power consumption].”

“Power consumption and heat go hand in hand. The more you can reduce the power consumption, the more you can reduce the heat that is put out. Also, AMD has done things specifically inside the processor to reduce heat and power, called Cool Core technology which can turn off parts of the processor that are not being used. In current systems today, there is one floating point unit (FPU) for each core. Not a lot of apps are utilizing that FPU very often, so the ability to shut that down if there are no FP instructions coming through saves a lot of power,” he explained.

The need for power efficiency also drove AMD to develop the ability for extremely customized power usage in its processors with the ability to independently throttle each core. “In some other people’s processor, they might be able to turn all the cores down all at the same time to lower clock speeds when utilization drops, or might do it in pairs, but we can have each individual core running at the different clock speed,” he explained. To do this, AMD architected each core to run on its own power plane.

The EDA perspective on power

Sriram Sitaraman, a director in Synopsys’ IT department, said power consumption in a data center is typically in relationship to the number of compute and the amount of storage. The total power consumption in a data center can be reduced by adopting lower power devices – even though issues come with it, such as turnaround time and throughput – so if the datacenter is a highly dynamic environment, the key is to optimize existing equipment and not buy equipment that is going to lie idle, he said.

Further, “a typical software company is not going to do a lot of investment in lower power devices because it directly affects their turnaround time, however, it makes a lot of sense for companies that have seasonal traffic or are working with metered power,” Sitaraman continued and observed that the typical trend in the software industry is to try to optimize the existing resources without additional investment.

Added Synopsys’ Rich Goldman, vice president of corporate marketing and strategic alliances: “We are seeing a huge increase in verification on the designs because they are getting so much larger and the physics effects are so much more related. In order to provide all that verification, [customers] are building very large datacenters, which have huge power issues.”

To tame dynamic power consumption, processor designers use innovative techniques, such as clock gating, special reduced power states, multiple voltage domains, and voltage and frequency scaling, Narayanan noted. “Below 45-nm, leakage power also becomes very significant, sometimes surpassing dynamic power as a percentage of total power consumed. Designers are addressing leakage both with new architectural tricks, such as power gating, as well as new process technologies like low threshold voltage and Hi-K metal gate transistors, which have inherently less leakage.”

Goldman expects to see automation of these techniques to make them easier to use, bolstering the adoption of them. “Instead of trying to find new ones, we’ll apply what we’ve already learned and automate that,” he added.

Overall, AMD’s Fruehe expects to see more focus on lower power processors, which are set to grow at a faster rate than other processors. Also, he predicts more emphasis on driving energy efficiency in processors.

“If you take the analogy of the auto industry, you’re seeing a lot of interest in hybrid cars and more being sold, but you are also seeing energy efficiency in the standard, gasoline-driven cars. People are looking for better overall power efficiency. Whether they get it with buying more high efficiency (HE) products or whether the standard products become that much more energy efficient, either way is a good solution as long as I’m saving power at the end of the day,” Fruehe said.

The race to 40nm is over. Some chipmakers are already there, taping out designs and implementing IP that has already been qualified at the 40nm process.

When exactly volume production begins and when yields improve is a matter of conjecture. TSMC so far is the only major foundry actively using the 40nm process, which is a half-node beyond 45nm. But the Common Platform already has briefed analysts and customers on its 40nm process, even though most of its work is at 45nm, and the Global Foundry—the AMD spinoff—has 40nm ready to go if there is customer demand.

A side benefit to consumers—and a big headache for design engineers—is that the power envelope continues to shrink with the line-widths. Low power is now standard in every design, which puts pressure on all IP vendors to create low-power versions at least concurrently with their newly qualified IP, if not first—or to make all versions low power. In the past, low-power versions typically trailed initial rollouts by 6 to 18 months.

And while that doesn’t mean all pieces of an SoC design need to be manufactured using a 40nm process—non-volatile memory, for example, is still at least a node behind—it does mean that research is well underway and on track for 32/28nm and that 40nm appears to be a relatively stable manufacturing process.

AMD, with its ATI line, and Nvidia both have 40nm versions of their latest graphics processors, which typically run at the leading edge of Moore’s Law because there is far greater potential for using more cores with existing software than many other chips. Video, in particular, is one of the easier applications to write for multiple cores because graphics rendering can be parsed into discrete units.

Low power everywhere

The power envelope in a more densely-packed piece of silicon has to be significantly lower, however. Signal integrity is a growing problem, according to design engineers, in part because of the density and the amount of current moving through the wires. Higher density also opens up real estate on a single chip for more functions that previously were on multiple chips or even multiple devices.

All of that points to lowering power wherever possible. And it means that to be successful in the market, low power design is a must. Virage Logic, which makes a variety of memory and logic IP, saw the trend clearly at 65nm when it incorporated low-power options into all of its IP instead of offering a separate low-power version.

“At 40 nanometers, if you want to create a new chip it has to be low power,” said Brani Buric, Virage’s executive vice president of marketing and sales. “We used to have high-density, high-speed and low-power versions of our IP. At 40nm, there are no separate low power products. There is a full set of low power features in both our high-density and high-speed IP, whether that’s memories or logic.”

AMD’s graphics processor group rolled out its first product at 40nm this spring. Stan Ossias, director of product management in AMD’s global/discrete graphics unit, said the bulk of the company’s work is still at 55nm and the company got a huge performance gain by re-architecting its 55nm chips.

“A lot of what we do has to do with predicting the readiness of the process at any time,” said Ossias. “We capitalize on the IP that’s available and the design he have to maximize our competitiveness. Last year, we had the choice of going to 40nm using the same architecture, but we thought we could do a better job of reaching our performance goals by redesigning the architecture. We didn’t feel the 40nm process was ready.”

That approach is one that is becoming more common among companies that typically hopped from one process node to the next in the past. The complexity of getting to the next node, along with the rising costs and uncertainties about manufacturability, yield and the IP needed in a design—not all IP available at 40nm has been proven in silicon yet—makes each new process node an increasing risk, and one that is no longer just an automatic decision.

At least part of the risk assessment also has to do with power consumption. Each new node also requires reducing the power consumption, which involves a litany of design tricks ranging from power gating for active power to utilizing power islands for static leakage, different gate structures and a variety of exotic insulation materials.

“Power is one of the fundamental areas we think about with technology evolution,” said Ossias. “Every time we shrink the process, we have to put more and more effort into decreasing power. That involves not just the individual device, but how that device interoperates with other devices. It’s a big consideration.”

40 vs. 45nm

Even moving from 45nm to 40nm is raising some questions. The foundry business is extremely competitive and having the next process used to be a competitive advantage, but so far only TSMC is actively pushing 40nm. The foundry told analysts that it opted for 40nm instead of 45nm because the process could be tuned better for device performance.

Joanne Itow, managing director of manufacturing at Semico Research, said the number of half nodes is exploding. She said that gives both foundries and companies a chance to firm up the processes and move more gradually to the next full node. The Common Platform, for example, is working on 28nm, which is the half node between 32nm and 22nm.

Global Foundries, which is the AMD spinoff, will work with customers for a specific implementation at 40nm or refine its bulk 45nm process, according to spokesman Jon Carvill. But he said the next step under development is a 32nm and 28nm bulk CMOS process.

Still, now that the foundries have reached the node and are working on the next one, the question remains of just how many chipmakers will move to the next half node and how quickly. There is a lot of conjecture now that the pieces are falling into place for 40nm production, but so far there are no definitive answers.