Part of the  

Chip Design Magazine


About  |  Contact

Posts Tagged ‘Ansys’

Next Page »

Low Power News, Jan. 6, 2014

Monday, January 6th, 2014

Happy New Year and welcome to the inaugural edition of the Low Power News for 2014.  Not too surprisingly, not a lot happens over the holidays when most tech companies have forced shutdowns.  Consequently, this week we’ll have a single  news story followed by a look back at the Low Power News of 2013.

It looks like the ‘Vegas CES announcements have begun!  Silicon Laboratories announced that Magellan has chosen their EFM32™ Giant Gecko microcontroller (MCU) for their Echo smart sports watch.  Clark Weber, senior director of Fitness and Wearable Products at Magellan says,

“Since sophisticated multiple functions potentially require a lot of energy, we chose the EFM32 Giant Gecko and companion Simplicity Studio design tools as our 32-bit low-energy platform, enabling us to maximize battery life without compromising the end user experience or future functionality.”

And now for a last look at 2013

ARM made a move into graphics last year, purchasing Cadence’s PANTA display controller cores, and acquiring Geomerics.

Women’s bra’s tweeted on the IoT.

It seemed like security was a big issue for everyone last year, and Jasper was no exception, announcing their Security Path Verification App.

ST Microelectronics developed technology that can help detect concussive blows during football, helping to improve the safety of the game.

Progress was made on the always ephemeral invisibility cloak, including an old-school invisibility demonstration from the University of Rochester.

Apache’s Aveek Sarkar filled us in on choosing low power design methodologies.

And finally, researchers in Chicago worked to offload some the of the GPS work from satellite receivers to the accelerometers in your smart phone.

Low Power News, December 27, 2013

Friday, December 27th, 2013

ANSYS, parent company of Apache, announced electronics upgrades for ANSYS 15.0 this week.  The upgrades include curvilinear element types important for antenna and stealth work; a new DC analysis tool for low voltage, high current, PCBs and IC packages; and a new flow that couples their electromagnetics and mechanical simulation packages.

Cadence announced that during CES 2014 they will be showing off products that demonstrate its Tensilica line of IP featuring audio, video, and WiFi solutions.

AMD blogged about their efforts to abstract the programming layer for their Radeon GPUs in an effort to make them accessible to a larger pool of programmers.

Earlier this year, I wrote about keeping an eye on government funding sources.  AMD has done just that, and it’s paid off in the form of a three million dollar grant from the DOE and NNSA to research interconnect architectures for high performance computing.

Finally, if you’re looking for a place to spend some of your Christmas cash, here are two suggestions.  First, I found a new maker toy.  A few weeks ago, I blogged about the Silicon Labs USB to SPI development kit.  This week I came across the Atmel AVRDragon development board.  I don’t know much about it yet, but it looks reasonably priced and pretty interesting.

Second, here’s a maker/spy novel.If you’re looking for something to read, you might check out the free first nine chapters of the latest novel from K.B. Spangler, author of the web comic, A Girl and Her Fed, (see below).   “Maker Space” starts with fourteen blocks of Washington D.C. taken out by terrorists.  The main character, Rachel Peng, must find out who did it before the country goes to war.

Expert Interviews: Apache’s Aveek Sarkar: Low Power Design

Monday, December 23rd, 2013

By Hamilton Carter, Editor/Verification-Low Power

LPE got to sit down with ANSYS Apache’s Aveek Sarkar to discuss how design engineers sort out the variety of low power techniques that are available to them.

LPE:  Where do design engineers start when looking at different power efficiency design techniques?

Clock gating was one of the first things people started to look at for power optimization.  In clock gating you shut off parts of your clock network such as a the portion of the clock network driving a particular bank of registers that do not have any data activity – this way you can save dynamic power.  It’s still one of the first places to look for savings as dynamic power is a big component of overall power.  There’s a pitfall however.  A common mistake is not taking the design of the enable signals or their efficiency into account.  If 99% of the design is clock gated, it doesn’t mean that you have a low power design – it also depends on whether the enable signal is operating efficiently.  Often times, projects which have clock gated the entire design can still lose sight of the fact that the efficiency of clock gating is controlled by the enable signal. If the enable signal is not designed properly it can limit the amount of power reduction you can achieve. So it’s  important to simulate the design and perform rigorous power exploration, tracking various metrics including clock gating efficiency especially at the RTL level to isolate and fix such scenarios.

LPE: What about power gating?

Power gating is commonly used to control  leakage current or standby power.  Its use started to become prominent around 2005 by mobile IC design teams, especially starting with the 65 nm process nodes.  The leakage current was an increasing trend in those process nodes – to control that, they started adding power gating as a low power design technique.  Power gating effectively breaks up power supply into two paths: an external path and an internal path by putting NMOS or PMOS transistor in series with the power rails.  For example, if the video block of the device is not being accessed then the video processing section of the chip does not need to operate. By flipping off that particular switch on the power rail, it turns off or disconnects that block from the rest of the power supply.  As a result, the leakage current drops significantly, sometime as much as 10x to 15x. However, based on some of the metrics that are printed in the press, especially with the advent of finFET, leakage power seems to be getting more under control as compared to dynamic power.  So power gating is still being used but it’s not clear if it’s going to be a standard technique going forward.

When using power gating, you need to worry about few things. The first thing to consider is that when you turn off power, you need to make sure that the state of certain parts of the device needs to be retained.  So you need well designed retention logic to make sure that you don’t lose whatever the design was doing last even if you shut off the power to that block.  You want to make sure you can recover the last state and move onwards. The second thing to consider is the time it takes to bring the block back on after its power off state and the current and voltage levels during and after the power up process.

The current trend is to look at power gating the design from a macro level – that means to power gate bigger sections of the chip rather than looking at it in a finer grain. With power gating at the macro scale, there are a couple of things you need to worry about.  For example when you turn a block back on you need a lot of current.  If the size of the power gated block is significant, such as an entire CPU core, a lot of charge is required to turn it on. If you have to supply power all at once, the battery may not be able to supply it quickly enough.  When this current goes through the package, it gets impeded. Two things can happen.  First, if you don’t power up quickly you can end up seeing an hourglass on the device’s screen since that block takes much longer to power up or doesn’t power up to the right voltage level.

Second, and possibly worse, the block that is turning on may borrow charge from a neighboring block.  For example, if  you powered off one of the CPUs in a quad core architecture and shortly thereafter turn it back on. This power-on process will require a lot of charge and you may end up stealing from the neighboring CPU. But the neighboring CPU may be still running.  So, as you take charge from the neighboring CPU it can end up experiencing higher voltage drop or increased noise coupling, which can impact its performance or cause it to fail.  This kind is scenario is fairly common and has to be watched out for, ideally with the use of a full-chip level package-aware power noise analysis flow that can model such a scenario.

LPE: How do dynamic voltage and frequency scaling factor in?

Depending on the type of application that is running, the chip can become very hot and to control the heat, the chip will need to be slowed down to extend the its lifetime or improve its power performance. But this technique, like others has the same set of challenges since it can introduce unknown behavior that can crop up when the device goes from one mode to another, or from one activity to another.  To protect against unpredictable behavior, the design needs to be modeled at the full chip level with the package and the board to simulate the transient current changes that accompany these mode transitions.

LPE: What other power saving techniques might be of interest?

Forward and reverse biasing rate techniques are making a comeback.  We are seeing designs where these techniques are being used.  Another interesting technology that is becoming prevalent is the use of on-chip voltage regulators (LDO).  When people want to control voltage for mission critical devices in an automotive IC or say for a sensor inside a pacemaker or other devices where you consume very little power over time, on-chip regulators will become increasingly critical. For these devices, it is very important to model the operation of the LDO in context of the design it is supplying power to. This ensures that the LDO can operate reliably across the entire range of operation of the chip.

Aveek Sarkar joined Apache Design, Inc., a subsidiary of ANSYS, as a senior applications engineer in 2003. Since then he has taken on different roles and responsibilities. Prior to joining Apache, Mr. Sarkar worked for Sun Microsystems on several generations of UltraSparc processors. Prior to Sun, he held engineering positions at Cadence Design Systems and National Semiconductor. Mr. Sarkar holds a B. Tech from the Indian Institute of Technology, Kanpur, a MSEE from Oregon State University, and MBA from Santa Clara University.

Low Power News: November 8, 2013

Friday, November 8th, 2013

ARM and Nordic Semiconductor announced an agreement to incorporate Nordic’s low power bluetooth solutions into ARM’s mbed IoT device development platform.

This announcement comes on the heels of Nordic’s introduction of an SoC that incorporates both bluetooth and ANT+ wireless protocols.

ASIC startups are entering the Bitcoin mining market.  The newish currency is created/printed based on networked computers solving crypto algorithms.  I wonder if the market could be crashed by the NSA at will.

Today is the deadline for the Movein3D design contest sponsored in part by Daassault Systemes.  Keep an eye out here for news of the winners.

GPS is battery hungry and often just unavailable in city centers.  A team of researchers in Chicago has developed an app that offloads some GPS tasks to smartphone onboard accelerometers.  The result is a more precise position and longer battery life.

Third quarter results continued to roll in with ANSYS of ANSYS-Apache fame reporting record results.

In other news of ANSYS, they’ll be offering a free ANSYS DesignModeler online course for egineering studentsNovember 28th and 29th.

Lockheed is working on the successor to the SR-71 Blackbird.  Initial mockups indicate the Mach 6 craft might be windowless.

Peregrine Semiconductor announced a partnershiop with Global Foundries to produce their SOI RF switch devices[pdf] paving the for their entry into the 3G handset market.

Digital vs. Analog and the verification of power: Inductors

Tuesday, October 29th, 2013

I got a chance to speak with Aveek Sarkar, vice president of product engineering and support at ANSYS Apache this week.  Our conversation about power aware verification revolved around the di/dt voltage drop caused by on chip inductors also known as power delivery grids.  Although, I grew up as an analog engineer dallying with inductors and capacitors on a daily basis, as a functional verification engineer, I’ve considered inductors and capacitors… well… almost never.  Consequently I thought it might be kind of fun to run through a high level review of why inductors drop voltages.

Inductors, Calculus, and the Time Domain

While discussing verifying the power distribution grid, the expression, ‘LDIDT drop’, came up a lot.  Written down, it looks like this

and is translated as: the instantaneous voltage drop across an inductor is equal to its inductance times the rate that the current through the inductor is changing with time.  Why does it matter?  When a block of a chip is powered off and then powered back on, there is a quick change from zero current running down the supply bus to the total amount of current needed by the block.

The above picture is idealized, but it gets the point across.  The current running down the supply bus jumped from zero to Io in a very short time.  Consequently, the voltage drop across the inductor went from zero to a big number, (Io divided by a number approaching zero).  It is this voltage drop that can cause problems downstream on the power bus, especially if the power bus in question is attached to other blocks.

An analogy of Aveek’s that I paraphrase here is apt.  If you’ve ever rented an old cabin, or had the pleasure of living in college slums at school, you may have noticed that with all the lights on, and the washing machine running, when you turned on the microwave, the lights all over the house flickered.  That flickering was due to the L di/dt voltage drop caused by the microwave quickly slurping a gulp of current off the shared power line.  Flickering lights can be intriguing and even romantic in the right setting, but in digital circuits, flicker is just plain bad.

Inductors and the Frequency Domain

Thanks to Heaviside lots of us like to think of inductors in the frequency rather than the time domain.  In the frequency domain the expression for the above voltage drop is:

where j is the square root of negative one and omega is the frequency of the current running through the inductor.  In short, the inductor acts as a larger impedance to higher frequency signals.  How does this apply to our step function above?  Any time-based waveform like our step can be expressed as sum of sine waves via a Fourier series.  The picture below illustrates how sine waves of different frequencies can be added to create a square wave-like shape.

Note that to get closer to an actual square wave, more waves of higher frequency have to be added to the sum.  The additional sine waves of higher frequency see a higher impedance due to the inductor and therefore, a larger voltage drop.

A Musical Side note

The same process described above is why audiophiles will tell you that music sampled at 56 kHz simply isn’t crisp enough and that they prefer the ‘more realistic’ sound of 96, or even 160 kHz sampled music.  It’s all about having more available frequencies to more accurately reconstruct a waveform.


Fast changes in current can make circuit elements that once looked like wires behave like inductors.  The associated voltage drop downstream can wreak havoc with the rest of the circuit.  The equation that governs this voltage drop can be thought of in either time domain as it happens via a bit of calculus, or in the frequency domain as a consequence of the high frequency waveforms required to create fast current transitions.

Low-Power News October 25, 2013

Saturday, October 26th, 2013

Find out what powers the internet of things.  Stephen Ohr of Gartner describes the two main R&D thrusts to provide power for IoT sensors that have to live in the wild unmaintained and without a power main for up to 20 years.

NXP introduced a new data acquisition oriented microcontroller which utilizes an ARM cortex processor this week.  The LPC4370 features “… the fastest 12-bit ADC available on a Cortex-M microcontroller today with a sampling rate of 80 Msps”.

Many companies announced their third quarter financials this week.  ARM and NXP both announced theirs.

For the most complete and up-to-date copies of any publicly traded U.S. company’s results, you can search the SEC’s Edgar database.

ARM will release new technical details for their ARMv8-R architecture next week at the ARM TechCon, in Santa Clara,  (Tuesday 29th – Thursday 31st October 2013).  The new architecture is targeted for the automotive and industrial controls markets and features new virtualization and memory protection technology as well as NEON SIMD instructions for improved digital signal processing.

Power Integrations were the first to demonstrate a reference design for Qualcomm’s Quick Charge 2.0.  You can read all about the design in their report [pdf], (it’s pretty and detailed!)

ANSYS moved into the top 100 of the Software 500, (as ranked by Software Magazine), list this year.

Researchers in Twente have announced nano-etching technology that should be able to store data for up to one million years.

Finally, astronomers announced the discovery of a new galaxy which now holds the record for being the farthest from the Earth.

Low-Power News: October 4th

Friday, October 4th, 2013

By Hamilton Carter

ARM Purchases Cadence’s PANTA display controller cores

ARM announced its purchase and transfer of Cadence’s PANTA display controller cores early in September.  ARM’s Pete Hutton, executive vice president and general manager, of their Media Processing Division said

“Display technology is critical to the mobile consumer’s user experience.  The addition of the PANTA family of display cores to the ARM product portfolio will help our ecosystem of partners get to market quickly with high-end displays that are fully integrated with ARM’s leading Mali™ graphics and video solutions and protected with ARM TrustZone® security.”

The processor cores started as a co-development project between Cadence and ARM.

Smart Phones and the Visually Impaired

Speaking of display technology, you might not have thought that a small very smooth screen would be of much use to someone who is visually impaired.  It turns out that with the addition of speech recognition, and other audio technologies as well as screen zooming, the smart phone has managed to cheaply replace several independent devices.  Dorrie Rush of Lighthouse International was quoted in an in depth New York Times article as saying:

“Before a smartphone was accessible we had to carry six different things, and now all of those things are in one of those devices.  A $150 money reader is now a $1.99 app.”

ANSYS/APACHE and TSMC Collaborate on a 16nm Reference Flow

ANSYS had this to say in their press release:

Apache’s RedHawk and Totem products have completed methodology innovations are to be included in TSMC’s reference flow for 16nm FinFET technology.  The methodologies will help design teams manage power integrity, and deal with electromigration (EM) reliability issues.

“The collaboration between TSMC and Apache provides our customers with the ability to efficiently produce more reliable and robust designs for next-generation SoCs (systems on chip),” said Suk Lee, TSMC senior director, design infrastructure marketing division.

SoC Power Integrity And Sign-Off For 28nm Designs

Thursday, August 8th, 2013

A presentation discussing how RedHawk enables physical design weakness identification, automatic repair the source of the supply noise, analyze impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s PDN for system-level analysis.

To view this video tutorial, click here.

RTL Design-for-Power Methodology

Thursday, July 11th, 2013

This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.

To download this white paper, click here.

Technologies For Power, Signal, Thermal, And EMI Sign-Off

Thursday, May 9th, 2013

This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache’s power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.

To download this white paper, click here.

Next Page »

Extension Media websites place cookies on your device to give you the best user experience. By using our websites, you agree to placement of these cookies and to our Privacy Policy. Please click here to accept.