This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements.

To download this paper, click here.

By Ann Steffora Mutschler
As the reality of true 3D IC design nears, engineering teams are keen to manage the heat between the stacked die in order to avoid catastrophic failures. Thermal modeling tops the roster of techniques to leverage in this area.

Herve Jaouen, director of modeling and simulation in STMicroelectronics’ technology R&D organization, explained that in 3D designs thermal modeling is very important for reliability. “In case you have thermal expansion it can generate defectivity. On the other part, on the design itself, you must take into account the gradient temperature in the stack.”

ST's Jouen: Thermal expansion can cause defects.

At the same time, Ji Zheng, director of chip-package-system at Apache observed that 3D design is something that scares people into thinking about the thermal issues, especially when one chip is going to be another chip’s heat dissipation channel. “These ideas are generally confirmed by the fact that you’re going to generate a lot of heat and your heat dissipation channel is tight so what is the impact on reliability and transistors when they’re using passive interposer or in the future active interposer? It means that the heat dissipation channel also will have to act as a device.”

These things definitely require more insight into the temperature distribution–how much variation there will be and how much heat can be sustained without affecting reliability.

“We need to do thermal modeling,” said Zheng. “The reason is that if you just do a package-level analysis, you won’t be able to get into the details of the temperature surrounding, for example, the TSVs and a particular layer inside the silicon interposer. A comprehensive thermal modeling that considers the spatial distribution of the die and the consumption in combination with the thermal environment provided by the package and board is important. But that is not a traditional thermal solution space. It is a new solution space.”

Further, it is important to distinguish between the two ways in which temperature can affect product design from an EDA perspective.

“Classically, and by far the most common adoption of thermal simulation capabilities, is for predicting operating component temperature as an indication of whether there will be any reliability concerns with the product,” said Robin Bornoff, product marketing manager in Mentor Graphics’ Mechanical Analysis Division. “The driver for considering thermal down at the silicon level is the relationship between the power dissipation and various functional blocks on the silicon and their operating temperature. This coupled relationship hasn’t really been a dominant factor until the length scales have gotten down to the levels they are now. The contribution of leakage power to the overall power of the package becomes a dominant contributor, and it’s the leakage power that is temperature dependent in an exponential way.”

The need to predict the coupling between temperature and the power dissipation—and the coupling between the power dissipation and the temperature and the effect that has on timing—while achieving the required timing are the drivers for taking thermal simulation as well as coupled thermal power or electro-thermal simulation more seriously, Bornoff believes.

“From a thermal perspective, an indicator of subsequent thermal problems and a leading indicator of how hot your electronics are going to get is a measure of the power density—the watts per square inch that you have in your package. When you stack silicon on top of each other the square inches don’t change, but you suddenly double or triple your power dissipation. That will cause operating temperatures to go right up. And because of this leakage effect, power consumption goes up, as well, and there is an increased risk of reliability concerns. You’ve suddenly drawn a hell of a lot more power than you designed in the first place so it really is a double whammy,” he added.

Thermal vs. electrical modeling
From a technical perspective, thermal modeling depends on the dimensions of the system you have. Electrical modeling for the device itself depends on that for simulation. At the design level, you must take into account all the environment, ST’s Jaouen explained.

The other element that thermal modeling takes into account is physical changes in the dimensions of whatever you are modeling, whereas with electrical modeling you don’t need to do that. But today there is no direct coupling between thermal and electrical performance. There needs to be a compact model simulation in SPICE. There also need to be two networks, one for thermal and the other electrical, with coupling between those networks, he said.

Apache’s Zheng also pointed out that thermal modeling is related to electrical modeling, but has its own unique characteristics. “Thermal modeling has to be related to temperature, and of course our other models are related to temperature but not a strong dependency. To model the power we have to characterize the chip function names as an explicit function of temperature. The temperature distribution is not only related to the fact that how the chip goes to the external world, it is also related to the fact that how the internal power consumption you actually will actually have a self heating effect–you are conducting current and you can generate the power through those currents. These are different from the electrical model.”

Another difference is that when you incorporate the thermal model you probably cannot do a so-called one-shot solution because of its dependency on temperature, he said. “You have to make iterations to make sure that you can actually calculate the converged power and the temperature because they go hand-in-hand. You cannot say I know the power without knowing the temperature or vice versa–we have to know them simultaneously.”

As great as it all sounds, Zheng pointed out that we do not do explicit thermal modeling for most designs today. “We rely on a package-level thermal simulation or module-level thermal simulation to come up with ballpark temperature distribution at the module or system level. We do not look to, generally speaking, the thermal temperature distribution impact on electromigration reliability of the diel. I don’t think it is a common practice because of the lack of such solutions.”

Updated standards needed
To enable thermal modeling to become part of the mainstream 3D IC design flow, standards need to be updated, Mentor’s Bornoff noted.

While JEDEC has put a lot of effort into creating standards and methodologies by which metrics and models can be created—thermal representations of packages—a lot of these standards are still rooted in the assumption that there is a single heat source within the package itself, he said. “That was fine for the majority of packages 10 or 15 years ago–that was absolutely acceptable. But as the industry is powering ahead there is a proliferation of various packaging styles, and almost all of the cutting-edge ones involve the fact that there are numerous heat sources within the package. That can include numerous individual die, side-by-side or stacked, or a system-on-chip where it is one piece of silicon but there are distinct areas of that silicon that are being used for very, very different purposes.”

Bornoff said standardization has to catch up to provide a method by which suppliers can supply thermal data not only for package selection but also for actual thermal simulation purposes that the end-users can actually utilize. And until that standard’s inertia accelerates the end users simply have to rely on NDAs to get the data from their suppliers or just accept the fact they’ve got relatively little data and the simulations they perform will be indicative at best. They certainly cannot be quantified down to the level of predicting temperature variations on the silicon that can give input to an electro-thermal simulation for timing considerations.

“There are already basic standards that talk about ways in which you can report the thermal performance of multi-heat source packages. There are other standards going through at the moment that should facilitate the communication of data between the supplier and end-user. The future has got to be the creation of standards to support multi-heat source packages and to break this single heat source paradigm that the thermal community has been bound by the last 20 years or so,” he said.

ST’s Jaouen agreed: “You need more. You need to compute the self-heating of each device and the relationship with the neighborhood devices through a thermal network. Today it is not currently in the CAD flow. You can compute the temperature map on your circuit and after that, introduce a few of the correct models that take into account the device temperature introduced in your netlist. But it is not a flow that is usually used in CAD flows today. But it is something that is mandatory and that is asked for by designers.”

By Ed Sperling
Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics.

Stacking die holds the promise of becoming something of a game changer because it can solve multiple issues at once—power, performance, physical effects such as noise and crosstalk—while creating its own issues such as who’s responsible when two known good die don’t work in a package.

But the surprise among companies working with this packaging approach is that it’s harder to remove the heat from stacked die than anyone initially thought. The generally accepted premise that silicon is a good conductor of heat is true, but apparently not true enough. Early tests show that 3D stacks are showing some limits for through-silicon vias.

“What we found is that you have about a 7 to 10 watt maximum for through-silicon vias using current technology,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “After that you have to go to an interposer.”

This is somewhat counterintuitive, because most engineers have always assumed that 3D stacking would be the successor to 2.5D stacks. Unless something is done to change the technology, it may be the other way around. This is good news in one sense. It’s cheaper and easier to work with an interposer, which contains TSVs on a separate piece of silicon, than with TSVs running directly through stacked layers of thinner chips. There is less stress to deal with from drilling through a layer of silicon, and yield is higher if those TSVs are run through a thicker piece of silicon.

“The big problem now is that with a dense TSV the heat is trapped,” said Dian Yang, senior vice president of product management at Apache. “You have to use metal to dissipate the heat. People didn’t know the power density would be so high, and that has causes thermal issues that are much more severe.”

In 2.5D stacking, the tradeoff is the footprint. A 3D stack is much smaller and can fit into smaller spaces, which is why it has been of particular interest to companies such as Broadcom and Qualcomm.

It’s not the TSV technology itself that is causing problems. It’s the location of the TSVs. There are still places where TSVs work extremely well, such as inside of interposers and in stacked memory configurations. Memory is particularly attractive because it doesn’t generate heat anywhere near the level of logic. Micron and Samsung are both developing stacked memory configurations using TSVs and claim faster performance, higher density and lower power. This kind of memory can be used in a 2.5D as well as a 3D stack.

Other considerations are under way, as well, such as using different substrate materials using different cooling methods, such as microfluidics. But there will either have to be a compelling technology reason, which so far has not been proven, or a major ability to reduce the cost of these approaches before this kind of technology hits the mainstream. Until then, it’s anyone’s guess whether and for how long a pure 3D stacking approach will be successful.

By Ann Steffora Mutschler
As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability.

CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very high-power technology.

“For many years it has been a very low power, very power-savvy technology. Moving from one technology node to the next would basically cut the power consumption by half. This was great because you could basically integrate twice as many transistors within the same power budget,” explained Marco Casale-Rossi, production marketing manager for Synopsys’ implementation group.

That was ideal when electronic devices were powered by the plug in the wall and weren’t hampered by batteries, he said, but when we moved to mobile it was already too late. “Basically, what has happened in the last decade is that we have shrunk basically the width and length of the transistor but our ability to shrink the thickness of the transistor is much, much lower.”

With the move from 45nm to 32nm, and then from 32nm to 20nm, there are twice as many transistors. Without leakage, the power consumption would remain the same, but because of leakage it goes up quite significantly. At 45nm, in a typical process technology the total power consumption is dominated by leakage. There is more leakage power than active power and the problem is that it’s there whether you are doing something or not and drains power from the battery.

“There are no secrets here,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “Power problems started at 130nm and have gotten worse since then. Historically, the problem was standby power, but it has shifted. There’s been a lot of talk about operating at a lower Vdd to help with this, but the only thing we’ve been able to do with every new technique is to forestall the problem. It comes back one generation later.”

With each process shrink leakage goes up exponentially with temperature—by a couple of orders of magnitude when going from room temperature to 125 degrees.

“Heat is a killer of electronic components. One of the issues, especially as we’ve gotten into some of the smaller geometries, is that the leakage current becomes exponential with the temperature. Small increases in temperature can have a large impact in the amount of current and heat that’s being generated by the actual chip or silicon, and clearly that’s not a good situation because if you add heat to it, it generates more current, which generates more heat, which generates more current—it’s going the wrong way fast,” said
Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics.

“Any type of engineering problem really, if you’re going to address an issue like that, it’s important that you have tools that can actually give you an accurate analysis so that the designers know what’s happening with the design and they can take measures then to control that and change the design to keep the design within the parameters that they need to,” he continued.

Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions agreed. He said that before the power densities can be measured, the right power-sensitive stimulus must be selected and that knowledge must be pushed all the way through the design planning process towards package selection. “The stimulus is becoming more and more critical in terms of really looking at and predicting what will happen to power before it reaches the physical side and meets these power density issues. If you are not properly predicting the power in the beginning of the flow then everything becomes academic. You overdesign or underdesign by definition.”

He recalled the horror story of a system designer who thought he would be designing a chipset at 10 watts, but when the ASIC came back from the manufacturer it ran at 5 watts. The explanation from the ASIC manufacturer was that they could not predict that well because they are at the back end of the flow from the RTL and microarchitecture decisions.

This illustrates the huge disconnect between designers using conventional spreadsheets, looking at library elements or taking guesses as to the activity factors and true power predictions. “The root cause of the issue is the ability to predict as much as possible, as close as possible to what your final, worst-case power states will be and then designing for such in terms of test patterns and so-called power patterns,” Kulkarni said.

Adding up the power
Add some 2.5D or 3D stacking to the power density mixture and things really heat up. Matthew Hogan, technical marketing engineer for LVS in Mentor Graphics’ Design-To-Silicon Division, observed one of the big issues for designers in terms of dealing with power density and stacking is that the thermal profile is cumulative going up the stack.

“One of the big concerns that they are looking for is if they do have a hotspot on a die and they are stacking it with either the same type of die or different die, and if there is a way they could rotate or make sure that the hotspots are not coincidences as they move in the vertical direction,” he said.

Engineers try to even out the thermal profile naturally through its operation and try to get a better understanding of what the dynamic thermal profile would look like. They do this so that when it’s in its operational mode that they don’t have, for example, the bottom left-hand corner be the hotspot for the entire stack while the top right-hand corner is cooler. Designers want to know how to move the hotspots on each of the dies around so they can create a more even thermal profile for the whole system rather than on a chip-by-chip basis. That turns it into a system and system verification problem, Hogan said.

When and where that analysis is done depends a lot on what internal flows and processes have been implemented.

“Ideally it would happen at a floorplanning stage where each of the design groups get a thermal budget or a power budget, because thermal and power are somewhat intertwined in the IC side. When they get their budget for their block and you’ve got a floorplanning region, you should have a reasonable estimate as to how much power is going to be used by this block, or at least what your budget is,” Hogan said.

Added Mentor’s Pangrle: “If you’re starting with cruder estimates at the beginning, as you get more information about what the final implementation is going to look like, you can improve those analysis and estimate numbers and continue to do a sanity check the whole way through. Any type of flow that somebody’s going to put together they’re going to want to make sure that as they’re crossing these different levels of abstraction that in fact they’ve got a framework where they can have these paths and loop back and put this information as they get it in to make sure that in fact its all still going to hold together.”

The temperature-leakage loop
The temperature-leakage loop discussed above is the very reason why 3D IC is causing so much concern. Its structure hampers the ability of the silicon to dissipate the heat.

“My impression is that manufacturing will not help in terms of heat dissipation. The only way to reduce the power consumption and avoid the heat dissipation issues in the future will come from design techniques,” Synopsys’ Casale-Rossi said. “If you think of today’s processors they are built with voltage islands so you can turn on and off a portion of the IC when you don’t need it — this was not needed 10 years ago, but now it is a method of survival. Moving forward, design and of course design automation—because all these techniques are awfully complicated—will be important to mitigate the power related and heat thermal related aspects.”

But there is at least some continuity in the tools flows. To accurately model, analyze and predict worst-case power problems in today’s chips as well as future 3D ICs, it is now widely agreed that most EDA tools will undertake an evolutionary change – not revolutionary, as some had predicted.

“Evolutionary means, for example, a place and route tool will need to understand that a certain area is forbidden because there is a TSV there,” Casale-Rossi said. “But this is not a big deal. Test will evolve because the accessibility of the various tiers will go down. I anticipate that all of the JTAG and BiST related technologies and algorithms will have a great future ahead. Extraction will need to account for the capacitance and the resistance introduced by the TSV. It will be the same for DRC and LVS. There will be more rules to be verified but it’s not a revolution.”

The reality is that many people are quietly doing 2.5D and 3D IC experiments without much pain because there are workarounds and scripts. Later, when it is understood what is really necessary, the scripts will get incorporated into the code of the tools and become an integral feature of the tools. “For the time being, the amount of code that is really needed is minimal,” he concluded.

By Ed Sperling
It was supposed to be the first IPO since Magma went public in 2001. Instead, Apache was bought by Ansys in a deal that closed earlier this month—at a record pace for the EDA industry of less than two months since it was announced.

So what exactly was behind the acquisition and why did Apache agree to sell? And what will become of Apache within the much larger Ansys?

Low-Power Engineering posed those questions and others to Andrew Yang, former CEO of Apache and now the president of Apache Design Inc., a wholly owned subsidiary of Ansys.

1. Why did Apache opt to be acquired rather than continuing with its IPO?
According to Yang, the answer was “a convergence of vision.” “Their vision has gone initially from mechanical simulation to fluid dynamics to electronics. Our vision started as chip-centric with a focus on power to package and board. So they’ve gone from system-level to electronic to IC and we’ve gone from IC to system level to board. Our thought was that either we remain separate and hire a lot of engineers with system-level expertise, or we joint hands to accelerate the same vision.”

2. What happens to Apache now that the deal has closed?
Apache will be a wholly owned subsidiary, but it also will be a separate division. “The reason we agreed to a deal with Ansys—and the whole discussion from our first meeting only took seven weeks—was that they have a history of acquiring companies of strength, not remodeling them. Our core focus will be leveraging each other’s resources and leveraging their channel for underserved markets,” Yang said. But he stressed that Apache will remain focused on its customers and existing tools, as well as exploring synergies.

3. What will happen to Apache’s focus on 3D stacking?
Ansys also has focused on stacked die from the thermal side. Apache’s focus has been from the power and power modeling side. “This will accelerate an integrated solution,” Yang said.

4. What about overlap and synergies?
Overlap is minimal, according to Yang. Synergies are still understood and developed. The key to the combined company will be to figure out “what the customer needs and what the competition lacks.” Talks are underway to figure out how the companies’ combined strengths can be extended into new markets and approaches, but one of the keys for Apache is Ansys’ strong, well developed sales and distribution channel.

5. What are the challenges ahead?
Figuring out exactly how to work together in the future. At this point, there is no comment about future directions, additional potential acquisitions and which companies will be viewed as the top competitors.

This power budgeting white paper presents a design-for-power methodology, starting early in the design process at the Register Transfer Level (RTL), to help deliver maximum impact on power.

To download this white paper, click here.

By Ann Steffora Mutschler
It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2.

But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most efficient way through the design flow.

If power is not implemented in the most efficient way, meaning if it isn’t optimized and reduced to the bare minimum, then what’s the purpose of designing it?

“Whatever the power ends up becoming, it is what it is, and in many traditional designs this has been the approach,” said Shabtay Matalon, ESL market development manager at Mentor Graphics. “There wasn’t in mind an objective to say, ‘Let me design it such that the power will be minimized.’ The power conservation and reducing the power is the primary objective.”

Most tools that address power today begin at the RTL, but there is an increasing consensus that this may not be early enough. “The percentage of gates or transistors in a design that can be exercised at the same time is shrinking and shrinking,” said Matalon. “On one hand we get this huge capacity to put billions of transistors on silicon. On the other hand, the power is [holding back] the percentage of the resources that we put on the chip that can be exercised. There is a need for this intelligence that is usually in the software. I’m sorry to offend anybody on the hardware side, but the intelligence is really in the software that is running the application—the software that understands the application context to play a role in reducing the power in the environment. Obviously, the hardware needs to be below the infrastructure and that’s why RTL might be too late.”

Design-for-power is not just analysis at the RTL. It is design for optimizing power. Some define a design-for-power methodology as having a gate-level representation, running some analysis, then predicting the power. Predicting the power accurately at RTL is highly questionable, though, unless you really run the device in the same operating conditions that you will actually use it.

“But there is not even a doubt that when you are doing this analysis at RTL down, that you lost your possibility to optimize,” said Matalon. “Design-for-power is not just analysis. It is the reduction of power.”

Example of a power methodology. (Source: Mentor Graphics)

Larry Hudepohl, VP of hardware engineering at MIPS, agrees. He said the importance of power as a design metric is one of the first and foremost criteria, not just an afterthought when putting the final chip together. “In the same way that the analysis of performance has moved much earlier in the design flow in advance of RTL, I see that same trend happening on the power side too. Earlier estimation of power, especially in a complex SoC where there are multiple devices driving multiple complex interfaces so the modeling of that—the power dissipation characteristics of the full chip under different operating conditions, under different power management modes—can really be assisted by modeling in a stage earlier than RTL.”

On the other hand, Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions, stressed that RTL is indeed early enough for a DFP (design-for-power) methodology. “Design for power must be done at the design level of abstraction, and for hardware design this means RTL. Anything after RTL is either automatic optimization (e.g. synthesis) or implementation, which in the case of the digital flow is also automated (i.e. place and route).”

Apache’s view is that a key part of a DFP methodology is power debug and power efficiency analysis, and the benefit of doing these at the RTL is a significant improvement in productivity (and corresponding turnaround time reduction) compared to traditional gate-level flows.

The cost of power-saving techniques
When designing an SoC or a multicore platform, there are a lot of architecture decisions that are clearly set before RTL is written and which must be considered in a design-for-power methodology, said Pete Hardee, director of solutions marketing at Cadence. “There are a lot of decisions that affect power that are already set in concrete before you are coding in RTL. Usually when a device like this is being designed, there is a lot of reuse going on. The rule of thumb is typically 70% to 80% re-use and 20% to 30% new design.”

There are some blocks that are being re-used that have already been characterized for power or known from previous use, or that can be recalculated if moving a design into a new node.

“What needs looking at is the cost of implementing the power saving techniques,” said Hardee. “We’ve got various techniques going on—power shut-off, including state retention. Some people call that power gating. What we are doing is splitting the design into various power domains and doing different things with those power domains, either switching them off and working out which registers need to hold value to come back on quicker or running from multiple supply voltages. There is a cost in implementing all of those techniques. Every time I split something into power domains, for every signal that crosses a power domain that I’m switching differently I need either isolation or level shifters or both. For every register that I need to hold a value during power off, I need a state retention register in there, which is roughly double the size of a regular register. Also, in normal operating mode, it takes greater power, there’s greater leakage due to the state retention registers compared with the normal registers. All of these decisions — how many power domains I’m splitting up into, how I’m switching those power domains — they have a cost and that cost can be assessed before RTL.”

Source: Cadence

Today, those costs are typically tracked by the power architect in a large Excel spreadsheet that contains all of the components that will be re-used in the platform. The architect tries to work out how many components need to be added for the power scheme in the new design, which are generally pre-RTL decisions. Of course, in a spreadsheet it is very difficult to work out for all of the combinations of domains being on and off as to what’s happening.

In lieu of the spreadsheet approach, there are a small number of commercial modeling frameworks available today from Cadence, Mentor and Docea Power, a French start-up.
This is also where things get interesting. A modeling framework captures the static power techniques, which need to be balanced with some kind of dynamic idea.

Above RTL that means simulation, Hardee pointed out. “This is where virtual platforms come into play and allow engineering teams to start exploring with running some software with a model of the platform and start to bring in a time element…the closer to the real operating environment, the better idea the simulation can give for whether the power architecture is sufficient or if changes need to be made to the power specification. Above RTL, I think most people’s goal is to relatively rank various candidate architectures. It’s a relative thing. What you are really trying to do as a power architect is at least get the ranking right to know if one architecture is better or worse compared with another.”

Obviously, the RTL tools can’t be abandoned because that’s where a lot of the detail design is done.

“It’s where most of the microarchitectures for the blocks being implemented are decided during the RTL coding phase,” Hardee said. “High-level synthesis is interesting because it can allow you to do better exploration of those microarchitectures before RTL. As soon as you start coding, you fix the microarchitectures. But RTL is still a very critical area. It’s really the first abstraction level that you can accurately verify the power architecture.”

The future of DFP
Looking at design-for-power from a high level, Cary Chin, director of technical marketing for low power solutions at Synopsys observed, “Advanced low-power optimization has come a long way in the past few years but clearly, we’re not done. There is much more to be done at a high level, looking at new methodologies and better ways of optimizing for power. It’s been a theory of mine that as we go forward, power becomes one of these things that we are designing around and it’s really something that is going to be a requirement and one of the fundamental keys to design going forward. I think we’ll see methodologies evolve even more going forward where, from the very high level, one of the main things you’ll want to consider is going to be power all the way through the design flow.”

And in future designs, the alternatives may be much less attractive.

This white paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power. To download this paper, click here.

By Ann Steffora Mutschler
Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower.

Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die capacitance and inductancel.

“In the past, when we talked about physical effects, we were very much talking about the transistors and above, such as the different layers of metals and resistance,” explained Dian Yang, Apache Design Solutions’ general manager and senior vice president of product management. “Now, it’s not only the metals. The substrate is becoming very important to consider in terms of physical effects impacting a design. Simple resistance models for physical effects are no longer sufficient to describe the vias, and now with deep submicron design those simple resistance models are no longer true.”

There are also heat-resistance effects, high frequency resistance effects, and pattern-based effects.

Complicating matters is an explosion in the number of design rule checks. For 28nm the simple decks are 3,000 checks, depending on the foundry, according to Joseph Davis, product manager for Calibre interactive and integration products at Mentor Graphics. In comparison, a simple fabless foundry deck for 90nm contained about 1,200 checks, while 180nm had between 800 and 1,000 checks. For a 20nm deck, there are between 3,000 and 7,000 checks.

“Determining which checks are critical to your design becomes tougher. And we are talking only about design rule checking. What’s happened now is that you’ve got DFM checking, litho checking, etc. and the real issue is you need to do all that but you still need to get your tapeout into the fab and yielding silicon by Christmas,” said Michael Buehler-Garcia, director of marketing for Calibre Design Solutions at Mentor Graphics. “Yes, the complexity is there. And yes, we think we are handling it. But how do you present all of this to the designer so he can get his tapeout done on time and make the right choices? One of the big discussions we’ve had is that one size doesn’t fit everything anymore because there are the basic rules. If you’re not pushing antenna rules, if you’re not pushing things, then you can relax. But how do I know which one to tradeoff? And oh, by the way, I still have to get the thing out in time.”

Consumer demand also plays a role in management of physical effects. Consumers want cool new applications and gadgets on their smartphones, which requires analog/mixed-signal content such as radios, sensors, I/O, controllers and power management. The following chart from International Business Strategies shows the percentage of designs that start with analog/mixed-signal IP and how fast this has grown. (See Fig. 1)

Fig. 1

Traditionally, analog/mixed-signal designs have tended to run on older manufacturing technology nodes. That’s not true anymore, said Buehler-Garcia. “The thing that has really changed is the ramp for a technology. It used to be that you’d enter a new technology with digital and then a year to 18 months later, you’d start seeing mixed-signal designs with analog content. With the drivers for the semiconductor industry moving from desktop and servers (pure digital) to consumer products which need to have sensors, and radios and so forth on them, now we are seeing the very first designs for every technology having analog content on them, which changes what the foundry has to focus on; it changes the whole ecosystem of what needs to be delivered.”

Analog developers historically stayed away from the leading edge. Many fabs still use processes as old as 250nm, although the core market has shifted tothe 130nm to 180nm range. But with CMOS RF companies can now build those designs on 65nm processes and below, which is a massive technology jump. That puts increased pressure on the foundries, which are having trouble meeting those demands in terms of the accuracy of their PDK and the types of devices they make. For these reasons, the EDA industry works very closely with the foundries in the development of reference flows and tools.

So are today’s design and verification tools keeping up? The answer is mixed.

Yes, in that process technology continues to advance and designers want to use advanced technology because the foundries provide that – they have a lot of benefits. “If the tools don’t work, the designers somehow make the tool work using work-arounds and different ways to handle that. On the other hand, the EDA guys try to improve the tools to meet the challenges,” said Apache’s Yang. “On the other side, no, I don’t think that our tools can keep up with the advanced technology as much as the designers want. The physical effects are very much process dependent. If you don’t keep up, well, then you may be behind.”

Another serious consideration is the impact of physical effects on the power in the design. “Power is very much related to the physical effects. When people didn’t care too much about the power in the early days, they could give 2.5 volts as the operating power. That made the margin huge, based on the transistor’s threshold. This gives around 1 volt to play with. With today’s operating voltages at 1.0, 0.9 or 0.8 volts, now your margin is in the millivolt range. Because the margin is so small…if you don’t model and simulate it well, the noise margin can either be overestimated or underestimated,” he pointed out.

Multiple power domains are a very big issue to contend with. S 30% to 35% of designs today use multiple power domains, said Dave Desharnais, group director of implementation and analysis/verification product management at Cadence Design Systems. “When you start messing around with models and abstractions, it is very, very important you have a way of modeling power domains in a very clean way so it carries the information along. Does it impact power? You wouldn’t be able to manage your power effectively otherwise unless you had some clean way of representing power.”

Mentor’s Buehler-Garcia believes more discussion on power will occur over the next year or so. “If I’m trying to adjust power down at the physical layout, then I can fix 10% to 15% of the problem. If I’m thinking about it at the architectural level, then I have a much better ability to impact it. But if my architectural level doesn’t understand the complexities and nuances, then that hypothesis is shot. How do we get fast prototyping? How do we work with an Atrenta-type offering where then it can quickly go down to Calibre and say, ‘Yep, that looks good,’ and pop back up.”

The importance of power
Power is an effect that now has to be dealt with at every process node, regardless of whether it’s dynamic or static leakage, noted Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. Power has been one of the key drivers behind the different gate manufacturing technologies, and on the tools side, the efforts have focused on meeting specifications for both leakage and timing.

“From the design side, for most designs, timing is paramount,” said Haider. “If there is a certain spec for how fast the design device has to run, that’s always been king. But now, with mobile devices and so forth, it’s not clear that’s always the case. We have some customers that will take a hit on timing if they reduce their leakage power a little bit more. The tradeoff on the tool side for us has been doing everything we can to honor the timing spec while at the same time adding new algorithms to drive down leakage.”

By Ed Sperling
Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine.

While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern over global warming and a steady reminder that smart phones have to be plugged in every night, car companies are shifting their strategy from efficient hybrids to even more efficient plug-in hybrids and electric vehicles, and California has gone so far as to mandate that one-third of all electricity sold in the state by the end of 2020 must come from renewable sources.

This shift in public awareness hasn’t been lost on the chip industry, which has been rolling out some very complex advances well ahead of schedule. Here are some of the most important:

Clouds
The push toward a cloud-based infrastructure is a way of centralizing computing—basically a return to the time-sharing model once perfected by the mainframe and then re-distributed with the advent of the commodity PC server. The data processing world is re-aggregating, but this time with a difference. It’s not just that the computing is being centralized. It’s that the centralization is taking place in proximity of cheap power sources such as hydroelectric power, nuclear plants (for now) and wind farms.

“Cloud leads to big efficiency gains,” said Chris Rowen, chief technology officer at Tensilica. “Now you can put the computing farm where the energy is available. It’s an arbitrage opportunity. It’s not hard to ship bits when you compare that to the difficulty in transporting electricity.”

There’s a clear business case to be made on this front. An estimated 6.5% of electricity is lost in transmission, according to the U.S. Energy Information Administration. That may not seem like a lot until you consider those are high-voltage transmission lines. Bits are cheap, in comparison—even trillions of them—which is why there is talk now of centralizing portions of even base stations. Those parts that do intensive computation with a high degree of redundancy are prime candidates for being located in a data center.

“There’s a lot of computation needed to reduce noise and create a clean signal,” said Rowen. “But there’s also some computing that has to be done locally because there are tough latency requirements.”

Adaptive Body Biasing
Adaptive body biasing has been under serious discussion for the past five years as a way of reducing current leakage by controlling a device’s body voltage, which in turn increases the voltage threshold. The big advantage here is less switching to the off state. The downside is this is has been difficult stuff to design and manufacture.

“This was not seen as a mainstream approach, but now it’s showing up almost everywhere,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “This was seen as a challenging technique to implement, but now TI and Samsung are using it. If you change the body bias voltage, you impact the threshold voltage. You can increase or decrease leakage, as needed, and boost performance.”

Consultant Bhanu Kapoor, president of Mimasic, noted that for some high-performance applications the alternatives such as power gating may be impractical because it simply takes too long to turn on and off sections of a chip. In those cases, body biasing is the only choice.

Atomic-Level Changes
Another technique that has been particularly difficult to master is atomic-level control of channel doping on the manufacturing side. And while most experts don’t expect the process and manufacturing side to offer any huge gains, this one may be the exception.

Scott Thompson, chief technology officer at startup SuVolta, said that by improving the doping technique, both dynamic and static current leakage can be reduced with regular bulk CMOS.

“The problem is that the wall around the channel is leaky and it’s hard to control the shape,” said Thompson. “Strain engineering helps to control the atomic-level analysis. But there has been no other breakthrough other than changing the transistor, and we don’t see a need for that for all architectures.”

At its unveiling last week, SuVolta had lined up support from Fujitsu, Cypress, ARM and Broadcom. The company claims the technology is an alternative to FinFETs, which are more difficult to manufacture.

3D Transistors And Packaging
Nevertheless, the major foundries have committed to building FinFETs at advanced nodes. Intel’s announcement of a Tri-Gate three-dimensional transistor at 22nm has been a major topic in the semiconductor industry. The question is now that Intel has publicly committed to the technology, can it really be manufactured with sufficient yield? And can it be built effectively using the disaggregated foundry model in the near future?

These kinds of questions will remain unanswered at least for the next couple years. TSMC is planning to use FinFETs at 14nm, and GlobalFoundries has been working on the same technology. Nevertheless, the big advantage of FinFET technology is a sharp reduction in leakage while providing a significant performance boost.’

Creating stacks of die also has a huge effect on power, in part because the distances between logic and memory can be shortened significantly. A system-in-package version of stacked die, using interposer technology, is expected to begin widespread production over the next 12 to 18 months, bolstered by the new Wide I/O standard that increases the size of the pipes between logic and memory.

New Materials
Fully depleted SOI, silicon on sapphire, as well as new ways of putting them all together in stacks connected by low-cost interposers that can be made of glass have turned into major research efforts as companies seek to knock costs out of the bill of materials for new chips.

While the FD SOI has been well tested for years by the Common Platform participants, the others have only been used on a very limited basis. One approach now being considered is actually designing chips to run hotter rather than trying to keep the power down. While there are limits to this approach—no one wants to pick up a hot phone—there are times when performance is more important than heat.

Taken as a whole, all of these changes can have a significant reduction in power, particularly when coupled with efficient software code and more customized user controls—and end devices that actually use the power-saving technology that is being built into these chips.