By Ed Sperling
Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that conversation.

LPE: How does this industry create models? No one is thinking about thermal over time or performance over time.
Agrawal: People have modeled temperatures for a long time. When they model corners they model temperatures. One of the major impacts over time is temperature.

LPE: But typically that’s a relationship of, ‘If you do this then this will occur over time.’ What we’re talking about here isn’t a standard corner.
Hardee: A better way to describe it might be vectors. You need to take a wide variety of system modes so you get all the different power situations that can happen. Intermittent peak power may not be enough to cause thermal issues because the peaks may not be high enough. But close to peak may cause a thermal issue. As long as you have the vectors for those cases, with power analysis tools we’ll find those cases.
Kulkarni: That’s especially true when you have islands of currents. That’s where you see the huge rush currents and peak power. You also need to look ahead of it and behind it in sustained power. That way you can address electromigration and the grid design. But that is missing sometimes in the stimulus. To excite those conditions is critical for the functional vector.
Murphy: I have seen some people doing heat diffusion equations where they are trying to model how the temperature evolves in the die. Then you have an even more complex problem.
Agrawal: But that’s coming. It has to go hand in hand with power management on a chip.
Murphy: If you don’t do it you have to bound everything by an envelope that says, ‘It could go here.’ That’s not optimal.
Agrawal: We really need better power models. We don’t have them.

LPE: Who’s going to create them? Is it the tools vendors, the foundries or the chipmakers?
Agrawal: At IBM we have been struggling with this so we began creating our own power models. But we’d be more than happy to standardize these models if we could get other vendors to work on them with us. What will happen is the people who need them will create them, and eventually we will see some standard models come out of this.
Hardee: It’s the kind of model you’d expect to see in a standard cell library.
Agrawal: A standard cell library all the way up to the ESL level. You have to have models at all levels.
Kulkarni: That model would need to contain net capacitances, cell types, cell inferencing, and some of the thermal effects as you’re going up and up. Capturing those at a higher level of abstraction would be a challenge. Power is where timing was 15 years ago. Just like we created timing models and area optimization curves, that took a few years as an industry. This is now coming together where a lot of the physical effects are getting captured from a power point of view. But power is not just capacitance, either, from a model standpoint. That’s where we saw a lot of cell inferencing and clock domains and various clock trees put into a higher level of abstraction and then into RTL. Otherwise it’s only implementation and verification and we head completely off from the power goals. Many techniques we use today in the implementation world really are directed toward verifying the designer’s intent. But the designer may be off from the goal.
Murphy: There are many challenges in power, but one is modeling the modal aspect. It’s not just about the technology. It’s how you use that cell. If you take a video codec, the power consumption is a very complex function of how that codec is used. Do you wrap an envelope around it and say, ‘It’s going to be somewhere in here?’ If you do that you accept a fairly significant level of inaccuracy.

LPE: You can build in inefficiency by setting that parameter too high, right?
Murphy: Yes.
Agrawal: I don’t think you can talk about power without talking about what you’re going to use that power for. If you’re looking at that codec and you’re worried about the thermal effects, you’re just looking at the average. If you’re looking at the instantaneous power, you would look at every single thing that’s happening. You have to define it differently. Power varies widely, but we have to define why we’re using it.
Murphy: That comes back to the application. How are you going to use it?
Kulkarni: That makes standardization a problem. It raises a question that will require the cooperation of a lot of people, from the foundries to EDA vendors to end users. They need to define what the power model will need to contain, including modes of operation and fundamental technology. People are stuck at 40nm and below, which is why they’re creating these capacitance models.
Hardee: And as you go through the flow, the need for modeling and the expectation people have for modeling need to change. If we can provide models that are good enough to do relative power measurement—if you’re looking at microarchitecture decisions, is this one better than that one—that may be good enough at a high level. Certainly before signoff you want a very good absolute power measurement because you want to make sure you’re meeting the spec. At the ESL level we may be quite a long way from technology that can really get to an accurate power number. But at least if we can provide enough relative accuracy for architectural tradeoffs, that would be a good start.

LPE: Are the biggest gains to be made in power at existing nodes or at the newest nodes.
Agrawal: It’s the functionality in a power envelope. That will be the benchmark. This is the power budget I have. Tell me what you can put in a chip. Is this amount of functionality possible in this given power budget?

LPE: Then does the process node matter?
Agrawal: No, but people are used to performance improvements, which is why they may go to the next node to get a slightly improved performance at a lower voltage.
Kulkarni: The battle will be played on power per MHz, at least for the consumer market.
Agrawal: And functionality.
Kulkarni: Yes. That’s why the mobile industry is working so hard. It’s not just more functions on a mobile phone. It’s creating a user experience. Everything over 3 watts becomes uncomfortable in your hand over time. That’s why all these standards are just under 3 watts. WiMax, 802.x and others will be at 2.4 to 2.6 watts. Many customers I talk with say 20 milliwatts will increase market share. That’s very good for this industry.
Hardee: In non-mobile applications we’re hearing the reciprocal of that. People are talking performance per watt.
Kulkarni: We have one customer doing flat panel TVs. We wanted to know why they wanted to lower power in set-top boxes—or set-behind boxes, more accurately. They said that if you’re watching a movie on your TV and it’s silent and then suddenly you hear the cooling fan, it would not be a good experience.
Hardee: These thermal issues also affect reliability. That’s why these set-top boxes keep failing.

LPE: But aren’t we getting to the point where there is enough performance for most applications?
Agrawal: Yes, and the frequencies are starting to level off. Gigahertz are gone.

Low-Power Engineering sat down to discuss a broad swath of power issues with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that conversation.

LPE: Can the power problem be solved in advanced designs or are we headed for a brick wall?
Murphy: What we’re dealing with is not a point problem. It extends all the way from application-level software design down into the implementation. It’s a stack.
Agrawal: When people were worrying about performance it was very easy to separate out instructions per cycle and cycles per second. You could optimize each of these and debug the optimized system. Power hasn’t had any such separation. People have tried look for some separation but it’s a very hard problem. That’s why the problem persists. Ten years ago people were saying power is very important, and since then some progress has been made. But we are looking for function in a power envelope all over the place, not just in a single application.
Murphy: The cell phone industry has been at the forefront of this, and one cell phone engineer told me they put a lot of functionality into the chips to do all kinds of sophisticated power-up, power-down tricks. The expectation is these knobs will be turned by the people who develop applications on top of these chips, but he said the big surprise is that no one takes advantage of those knobs because they don’t know how to. They’re lost bridging from the application to the power model of that piece of silicon.
Kulkarni: At last count there were about 22 different techniques, from system to microarchitecture to logical and physical for reducing power, analyzing power and managing power. It’s now come down to design for power. There is no single silver bullet. It comes down to dynamic power and static power, and simply managing those two equations across all levels of abstraction. But each decision you make has tradeoffs, so these 22 different techniques we’ve studied using area, timing and noise have an impact. That’s why no one has been able to solve this to date. If you look at the power grid or power delivery network, it becomes critical at all levels, not just the highest level. How you deliver that on the chip and around the chip involves tradeoffs for electromigration and electromagnetic interference. They all get impacted by microarchitectural decisions.
Hardee: A lot of these techniques have been around a long time, but what we saw at 45nm and 40nm is that leakage took over from dynamic power as being the biggest problem. We’re seeing a different emphasis on those 22 techniques that Vic talked about. The best ways to manage leakage involve shutting off as much of the system as you can. That has to be done under software control. But we’re also starting to see some physical limits as you go further down the process nodes about what you can do with leakage. The leakage is continuing to increase and the supply voltage is getting closer to the threshold voltage. There is some life left in bulk CMOS, but at 22nm people are starting to think about new approaches like SOI. The tradeoffs are not just timing vs. power. There are also cost tradeoffs for yield.

LPE: We’re hearing more about not just SOI, but fully depleted SOI. But how does all of this affect things like power delivery?
Agrawal: Suppose you have an electromigration problem in your power wire. What do you do? Do you need different materials for your wire? Can designers do something with the layout. If you move the wire, does the problem become bigger. It becomes a problem from the gate level to memory to the power level to the system-performance level. To get all these people at the same table talking the same language is not easy. People call it the kiss of death because it’s so hard, but the time has come where people have to do these things. It’s necessary.

LPE: Will this type of approach become mainstream, though?
Murphy: Everyone believes the biggest place you affect power is at the application software level. It’s going to be pretty interesting to watch Apple over the next few years. The iPhone has not been famous for its low power characteristics, but they have an advantage over the merchant market because they own the whole thing.
Hardee: Apple got people complaining about battery life after an OS revision. That meant they were back to the wrong defaults.
Kulkarni: There are many problems to solve. In the stimulus management, how do you measure power? When people generate their vectors those are not necessarily high-power-consuming vectors. With thousands of gates a clock can consume a lot of power. And memory-based designs can consumer a lot of power. The selection of right vectors will affect the power delivery metrics. Some vectors involve the package and the PCB, but when you are creating your stimulus that’s typically used for functional verification, not for power verification. The new challenge is what we have dubbed power pattern generation. That’s becoming important in most of the tough system designs like mobile phones—creating the right stimulus to drive the right power combinations. That may be multimode vs. high power-consuming vectors. If you create a functional vector set you need to select the right vector. We are finding convenient ways to live in our comfort zone, but finding the right vector is critical.
Agrawal: That’s the big difference between timing and power. Timing has been studied for a lot longer than power. People do static timing analysis—best case, worst case—and come up with one number. Power is not one number. There is different power for functional and IR and EM analysis. There is different power for di/dt (current change) and for battery life. So my power analysis has to be componentized so that given a power model I can do analysis at all these different application power corners for the same chip. That’s where patterns and switch factors come in.

LPE: But there aren’t many companies outside of IBM and Intel doing this, right?
Agrawal: That is correct. Because there is nothing available we’ve had to do it ourselves. It’s not because we love to do it.
Hardee: There are a number of people that need to work on this problem. As we’re getting the convergence of applications onto all kinds of devices, there isn’t one system mode where you can check everything. There are many different modes for just power alone. If I’m worried about leakage I’ve got to look at some modes that are shutting off a lot of the system as well as the modes where there is a lot going on. My peak mode may be in a totally different system mode to the peak mode that’s broad enough to give me a thermal problem. There are different kinds of peaks you need to look for. And with battery life, it isn’t power that you’re worried about. It’s energy. It’s the integration under the curve. You’ve got to run an awful lot of vectors for that. The other power measurement issue we’re all familiar with is accurate characterization, and the common wisdom is you need that late in the flow to be able to get a power measurement. Where people are failing is by having the wrong system activity.

LPE: With the future headed firmly toward multiple cores, will software written for specific cores or lots of cores that work as a generalized platform for whatever processing is needed?
Murphy: There’s no clear answer to that today. Almost invariably you have a housekeeping core, which is going to do stuff like boot management and configuration management. That may also be the center of where you manage your power. But if you look at any cell phone, you have DSPs performing all kinds of functions. It’s not clear yet how you divide up the software between the cores. What is clearer today is how you turn on and off all the peripherals like video and audio.
Agrawal: You design power switches and functionality that no one takes advantage of. At some point you can envision a chip with high power and single-thread performance, so you shut off everything else. But eEven though your whole chip doesn’t heat up, you may have a problem locally. So software needs to co-designed with the hardware, and today we don’t really do that.
Hardee: Using a general-purpose processor is not power-efficient. Using dedicated cores or programmable accelerators is better. And putting dedicated functions into hardware rather than running them in software may be the most efficient way.

By Ed Sperling
Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic.

Xilinx declined to comment, but a half-dozen independent industry sources familiar with its efforts have confirmed the 3D development is well under way. Rich Kapusta, Actel’s vice president of marketing, applications and business development confirmed his company has been approached by SoC makers to use the company’s non-volatile flash-based FPGA as a layer in their 3D SoCs. He declined to comment further.

Getting 3D chips this kind of work done is anything but guaranteed. It’s complicated and there are lots of pitfalls, such as accessing RAM or logic across multiple die. Nevertheless, the implications of these developments are enormous. Because of the very regular and controlled structure of an FPGA, it is extremely well suited to defining where components can be placed on a chip. That makes it much easier to predict hot spots caused by putting two or more chips together—a problem that becomes particularly thorny when chip layers are developed by multiple vendors without knowledge of the thermal characteristics and layout of the other components.

3D stacking makes it far easier to bump up performance at advanced nodes using shorter wires while reducing power because it takes less power to achieve that performance over shorter distances. But getting this accomplished with SoCs has been particularly difficult. As a result, sources say the need for FPGA prototypes may change FPGAs into the end game rather than an in-between step.

Moreover, both moves also are expected to open huge markets, finally, for advanced EDA tools to work on complex FPGA designs, as well as third-party IP, processor cores from companies like ARM, MIPS and Virage Logic, and interconnect fabrics such as network on chip. They also can open up 3D to mainstream development. While companies such as IBM, Freescale, Qualcomm and Texas Instruments have been working on 3D chips for years—IBM started its R&D in this area almost a decade ago—most of that work has been a closely held secret because it is considered a competitive advantage for performance and power. FPGAs can quickly turn that into a less expensive option that may have more overhead than bottom-to-top 3D ASIC designs, but far less than 2D ASICs.

Issues in 3D
FPGAs can solve one of the biggest problems in 3D stacking, namely standards for placement of components. Without those standardized approaches there will likely be some ugly finger-pointing when two chips are put together.

“One of the problems that we see coming is who’s going to pay for a bad part,” said Andrew Yang, chairman and CEO of Apache Design Systems. “Testing may show that memory and logic are all good and that the die works, but when you put it together with another chip it may turn into a bad part. So you can say it’s good, and all your testing and verification may show that it is, but when it doesn’t work who pays?”

Yang said there is a need for far more analysis of the stacked die, measuring everything from heat and power to electrostatic discharge and signal integrity.

“We also need to understand what are the killer applications and what applications are not good for 3D,” he said. “The compelling value of 3D is shorter distance, which is the TSV promise. The challenge is in coupling chips together. In 2D you could shield high-speed signal transmissions. You get a cross-coupling effect with a TSV, so there is promise but there are also challenges.”

One of the big draws for 3D in general is the ability to re-use IP, which may come in the form of entire chips. That doesn’t work too well, however, when those chips were created for the best utilization of real estate on a 2D structure, where heat dissipation is relatively simple. In 3D, putting chips together can sandwich heat between die with no way to get it out of the chip.

“When you stack die you concentrate the heat,” said Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. “That affects chip reliability, either short-term or long-term because they’re operating at temperatures they’re not expected to operate at. Circuits perform differently at 100C or 125C or 130C. At 130C it may affect the core, the timing, the signal integrity.”

While the overall heat of a chip hasn’t changed much, the more tightly everything is packed together the more difficult it is to cool. “When you stack them, you concentrate that heat even more,” Robertson said. “Potentially, when you move the wires closer together you can reduce resistance and IR drop. There would be a decrease in power and heat, but we have not seen enough of that yet to draw that conclusion.”

Under the covers, there are two technical ways to make this all possible, according to an ARM insider. “The first is for TSVs at similar pitch to solder bumps (about 50nm). This expands the capability of FPGAs and creates what amounts to multi-FPGA chips, as well as allowing for better-integrated flash, DRAM, and high-performance logic. The limited inter-chip bandwidth and power delivery, along with thermal issues, keep this as more of a cost dynamic – an extension to existing SiP approaches,” said the source. “The second answer is for high-density future TSVs, at a pitch of less than 5nm. These increase inter-chip bandwidth by a factor of 100 over the first solution and allow for some game-changing capability, including wide word high-speed off-chip memory access, combined FPGA/logic solutions, multi-die FPGA (greatly increased gate count) and so on. The reconfigurable aspect of FPGAs may also help solve the test and fault tolerance issues that are a very significant impediment to making tight pitch TSVs viable. Neither of these eliminates the crossover argument on power and performance, but they both have the potential to move it.”

Programming the future

Whether this effort ultimately succeeds is anyone’s guess. What is known is that a lot of resources are being marshaled into 3D stacking and a lot of hopes are being pinned on the back of efforts such as those from Xilinx and Actel’s partners.

Tom Quan, deputy director of design methodology at TSMC, said the great advantage of FPGAs is that they are very regular. “You can predict the thermal profile much better than with a mixed-signal SoC. Analog can be all over the map. But while the base array may be regular, in another corner of the chip you might have a USB so the outside of the chip might be hotter than the inside.”

Still, there was a lot of hype behind multi-chip modules in the 1990s and so far they have failed to materialize as a popular solution, largely because of cost. That could change as double patterning becomes the norm at 22/20nm and standard production costs rise, but visibility remains limited at that node.

At the very least, the moves by FPGA players are worth tracking, and a lot of companies are predicting major changes if these scenarios work. There are reasons FPGAs may hold more promise than multi-vendor or multi-generational SoCs. But there are still a lot of challenges to resolve before the total cost of development is known

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related.

Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher levels of digital and analog integration on the same die with several isolated and independent power and ground networks, (c) proliferation of hand-held devices resulting in more direct access to IC components, and (d) advanced package designs with tighter pitch, fewer layers, and complex shapes. Specifically, with technology migration, both gate oxide thickness and wire geometries are getting smaller, making the impact from the high current flow during an ESD event more detrimental.

This whitepaper will discuss PathFinder, a layout and circuit verification technology targeting ESD robustness and integrity. Using IP-level static and dynamic techniques and full-chip level static techniques, PathFinder can verify that a design meets ESD guidelines and identify “weak” areas of the design (layout or circuit) that are most vulnerable. It can also perform early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip. To download this paper, click here.

By Ed Sperling
Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them.

What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good news is that new tools are being developed, existing tools are being enhanced, and virtually everyone is aware and talking about the problem. The bad news is that that problem isn’t going away or getting any easier to deal with.

“ESD has always been a problem, but historically there have been a number of good approaches,” said Rob Aitken, R&D fellow at ARM. “We settled on a clever snapback device, which is parasitic bipolar, and had it operate in forward bias mode. That pretty much got rid of ESD for awhile, but the oxides in the new generation of chips are causing problems. Oxides have gotten to the point where they’re so thin that high voltages kill them.”

To a large extent, ESD protection works like a lightning rod. Voltage spikes need to be routed around anything that can be harmed by it. In advanced chips, particularly those with multiple cores or power islands, that gets significantly more complicated because it usually means sharing the circuitry. “You’ve got to make sure that every pin has diffusion to Vdd and ground, then put a clamp on the ground, clamp on the Vdd and a clamp between them,” said Aitken.

The power of touch
There are several well-known models for electrostatic discharge: the human body, machine-to-machine and a charged device model. All are capable of blasting apart the increasingly thin wires and insulation at advanced nodes, particularly with a voltage surge that goes far beyond what the system was designed for. At older process nodes, the wires and gate oxides typically could handle that surge. At advanced nodes, where the number of atoms in a gate oxide can be counted on two hands, the situation is much different.

“You really need your ESD protection window to be much bigger than the device,” said Andrew Yang, chairman and CEO of Apache Design Systems. “The problem is that the oxide breakdown voltage and the metal breakdown current are lower, so it’s a much smaller safety window. Your operating voltage cannot be scaled down beyond about 1.2 volts.”

Making matters worse, there are numerous voltage islands—often with different voltages—that need protection circuits. “In the past there were two voltages, Vdd and ground,” Yang said. “Now you have some voltage islands for speed, which typically are higher voltages, and others at lower voltage to reduce leakage. There’s also a tighter pitch on layout, which gives you higher ESD sensitivity.”

Fig. 1: Total current density at surface of device at four different times. Source: Synopsys

Most engineers agree that the problems in ESD became particularly acute after 65nm. At that node and prior nodes, most of the solutions were either confined to the I/O or proprietary. At 45nm and beyond everything changed.

“What’s evident is that now there are more circuits at risk,” said Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. “Also, because more chips are mixed signal we’re seeing many different power supplies. That adds to the complexity. How you dissipate ESD is dependent on whether the voltage supply is 5 volts or 1 volt.”

Lessons from I/O
To the companies that have been creating I/O structures and IP, ESD is nothing new. Several generations ago the rule of thumb was that if the voltage on the oxide layer was larger than a certain value it would rupture and short. All that needed to happen was that you had to prevent that maximum voltage from ever reaching the I/O subsystem.

“An oxide could bust at a nanoamp,” said Bob Lefferts, director of R&D for Synopsys’ Hillsboro PHY development group. “Today the oxides are porous so there’s a question of how much charge actually goes through. Failures are harder to detect and more difficult to protect.”

In fact, it may be harder to actually classify a failure. There are ESD events that prove harmless to the silicon. There are others that alter the device in ways that don’t kill the device but which may change its behavior, such as causing malfunctions when a particular circuit is involved. That circuit may not involve a core function of the chip and it may be powered down most of the time.

That has pushed companies to address ESD in two completely distinct directions. Lefferts said some of the large IDMs have been tracking ESD for decades and actually want to relax the rules for the minimum amount of protection from a shock caused by the human body. The current standard is 2 kilovolts, but the number of incidents that large companies have seen involving ESD damage warrants dropping that level of protection down to an as-yet undetermined number. On the other side, there are some companies looking to boost the protection to 8 kilovolts—quadrupling the current level of protection.

So far there is no agreement on anything, but there is lots of talk about ESD. “Going back 20 years I worked with design engineers who didn’t know what ESD was,” he said. “Today, any I/O engineer and every analog designer knows ESD and takes it into account. You can’t afford to design it in later.”

Side benefits
Interestingly, some of the same techniques that were developed for ESD are beginning to show up in other areas of design. The best examples involve isolation techniques, which are part of every ESD solution.

“Different people are approaching the problem from different angles,” said John Pierce, director of circuit simulation product marketing at Cadence. “The companies with process experience, like an ex-IDM or a company with fabs, will look at variability effects on metal and attack the problem head-on. A fabless company or IP group—especially independent IP vendors—never actually get their hands on the process so their solution is architectural.”

He said that isolation has become a particularly thorny problem in areas with multiple power islands. An isolation structure in advanced chips may be dependent on sequencing of power modes. In a real world example, one customer required three weeks to debug an isolation problem. “It was a second-order effect in complex analog.”

But those same isolation approaches also can be used to improve reliability of a device. For example, if a transistor can handle a certain number of signals before burning out, those signals can be spread across multiple transistors to lengthen the product life.

3D stacking and new materials
While many companies are looking at 3D vertical stacking as a way of easing the pain of migrating analog designs to advanced process nodes, very few are thinking about ESD effects. They should be. Through-silicon vias can move the charge to the outside and to adjacent chips, increasing the risk of failure.

There are ESD effects in different materials, as well. “The substrate is an important medium and Silicon on Insulator and standard bulk CMOS have different resistance,” said Apache’s Yang. “If it’s high impedance the charge will go to the package. That’s what happens with SoI and GaN. If it’s low impedance it will go through the wire.”

The bottom line: ESD has never gone away, but in the past most engineers didn’t have to deal with it. They do now.