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Posts Tagged ‘Apache Design’

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SoC Power Integrity And Sign-Off For 28nm Designs

Thursday, August 8th, 2013

A presentation discussing how RedHawk enables physical design weakness identification, automatic repair the source of the supply noise, analyze impact of dynamic voltage drop on timing and jitter, verify power and signal EM, and provide a model of the chip’s PDN for system-level analysis.

To view this video tutorial, click here.

RTL Design-for-Power Methodology

Thursday, July 11th, 2013

This paper presents a design-for-power methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.

To download this white paper, click here.

Technologies For Power, Signal, Thermal, And EMI Sign-Off

Thursday, May 9th, 2013

This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache’s power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.

To download this white paper, click here.

Optimizing Cost-Performance-Schedule With A Chip-Package-System (CPS) Methodology

Thursday, April 11th, 2013

To meet smart device requirements with high levels of sophistication from an exceedingly small device running off a battery, the underlying electronics must evolve at a rapid pace.

To read more, click here.

RTL Design-For-Power Methodology

Thursday, February 14th, 2013

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power.

To download this white paper, click here.

ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow

Thursday, January 17th, 2013

This paper presents solutions for effectively managing design specifications (performance) and margins (price). It discusses solutions based on accurate and predictive simulation software from ANSYS and Apache that offers electronics designers a simulation-driven chip–package–system convergence methodology.

To download this white paper, click here.

RTL Design-for-Power Methodology

Thursday, December 6th, 2012

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power.

To view this white paper, click here.

Technologies For Power, Signal, Thermal And EMI Sign-off

Thursday, November 8th, 2012

This paper discusses the challenges associated with designing smaller, faster, and lower cost products. It provides an overview of Apache’s power and noise solutions and how these products enable comprehensive chip-package-system convergence flow across multiple design disciplines.

To download this white paper, click here.

Meeting Emerging Needs For Next-Generation 3D-IC And Sub-20nm Designs

Thursday, August 9th, 2012

To remain competitive, IC designers must meet performance, power and price goals. However, these mutually conflicting goals require design techniques including 3D stacked-die architectures that will help meet performance and power targets by extending the integration capabilities beyond traditional SoC methodologies.

To download this white paper, click here.

PathFinder Solution For Full-Chip IC ESD Integrity

Thursday, April 5th, 2012

This paper describes how PathFinder helps designers meet ESD guidelines and identify “weak” areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.

To download this white paper, click here.

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