By Ed Sperling
Intel rolled out an ultra-low power Atom processor for smart phones and tablets. The company claims it can cut power consumption during idle by more than 50 times over previous versions to as little as 100 microwatts, but mileage will vary. In some cases it will vary greatly. For example, it will only offer about 4 to 5 hours of browsing, and the numbers go down from there depending upon how much graphics-intensive computing is involved. The bottom line: This chip sleeps well and it wakes up with a roar, but beware of what you feed it.

By way of comparison—and competition—ARM’s Cortex M0 processor idles at 85 microwatts, but the software stack is significantly thinner. Legacy has its advantages–namely its ability to run everything under the sun–and its disadvantages, which are namely the same as the advantages.

AMD is pushing into the low-power space, too, although it’s not exactly clear where the company’s embedded chips will play. At the very least, it will be more power hungry than a smart phone. The new chips will have power envelopes as low as 8 watts, which isn’t something you want to stick in your pocket. It may be something you want to include in a tablet computer, however.

Apple bought Austin-based Intrinsity, which makes design tools for turning up the clock on processors without increasing the power. Industry insiders say the real reason was the engineering talent. Speculation is rampant about which companies Apple will displace as it continues developing its SoCs—and why. Incidentally, Apple’s Web site has no mention of the deal.

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”

By Ed Sperling

Business seems to be picking up everywhere in the design world, with an emphasis on speed—quicker deals, faster product rollouts and overall time to market—and all of it with an underlying emphasis on low power and tighter power budgets. Could it be that after the recession, everyone is trying to get back on track quickly?

Virage Logic completed the acquisition of NXP’s IP technology and its development team. That comes on the heels of its recent acquisition of ARC. The fact that Virage completed both of these acquisitions in a 12-day period is nothing short of an accounting miracle. And just in case the company didn’t have enough to do, it added a Silicon Browser for post-silicon bring-up and system debug.

Android seems to be getting its share of attention these days. Mentor Graphics introduced an Android Development System for Texas Instrument’s OMAP35x processors. TI’s processors also include ARM Cortex-A8 technology, which puts ARM squarely in the center of this effort, as well, with a heavy push toward better battery life. But will any of this take a bite out of the Apple iPhone?

On the get-things-done-quicker side, Digital Imaging Systems used Synopsys’ Galaxy Custom Designer to achieve first-pass silicon in 22 days. Not all of it was from scratch, of course, but that’s still a very tight timetable.

And Atrenta’s deal with Fujitsu’s Kyushu Network Technologies is aimed at reducing design risks in integration of third-party IP from multiple vendors with different clock domains. Translation: Faster time to market.

Also on the business side, Cadence expanded its design alliance with Toshiba for the consumer and mobile markets.

Intel invested millions of Euros in an Exascale Computing Research in France, as part of Intel Labs Europe. This is the second time in two weeks that Intel has paid out big bucks to appease antitrust regulators. This deal will add 900 new research jobs in Europe. That follows Intel’s settlement with AMD, clearing the way for Intel to go after ARM with its Atom chip.

ARM’s comeback was largely a reiteration of the strength of its ecosystem. It struck up a strategic architectural license agreement with Infineon for advanced security applications and created a solutions center for Android.

By Cheryl Ajluni

The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices.

To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power consumption. To achieve that, they must spend more time and care in choosing the components, materials and techniques they will employ to drive down power consumption. They also must look closely at the wireless communications protocols they choose to employ.

One protocol that has received a great deal of attention of late is IEEE 802.11n—one in a long line of standards to emerge from the alphabet soup that is the Wireless Local Area Network (WLAN). Its improved performance and enhanced reliability over previous WLAN standards is thought to be the critical component in finally enabling WLANs to function as predictably as their wired counterparts. It’s no surprise than that a recent study from ABI Research predicts that by 2012 shipments of 802.11n technology will account for a full 60 percent of the market. Today, virtually 84 percent of the WLAN market stems from 802.11 a/g technology accounts.

Unfortunately, as is typical with any new technology, 802.11n faces a slew of challenges. In the Wi-Fi enabled, battery-sensitive market, for example, a key challenge to 802.11n’s widespread proliferation is power consumption. Meeting this challenge demands an ultra low-power technology, but can 802.11n deliver the low power necessary to take the battery-sensitive mobile by storm? Let’s take a closer look.

802.11a, b, g…n?

Essentially, IEEE 802.11n is designed to enable Wi-Fi networks to do more, faster and over a larger area. Well suited for both enterprise and home networks, it has the potential to deliver up to twice the range and five times the throughput of traditional WLANs (e.g., 802.11a, b or g). To date, draft 2.0 of the 802.11n standard has been approved and forms the basis for Wi-Fi CERTIFIED 802.11n draft 2.0 products. Certification of such products began in June 2007 and is done by the Wi-Fi Alliance (www.wi-fi.org). The final 802.11n standard is expected in September 2009.

802.11n technology builds on previous 802.11 standards by adding 40MHz operation to the physical (PHY) layer (enabled in either the 5- or 2.4-GHz mode), and frame aggregation to the MAC layer. It is based on Multiple-Input-Multiple-Output (MIMO) technology, which employs multiple receiver and transmitter antennas to transport two or more data streams simultaneously in the same frequency channel. This allows MIMO to coherently resolve more information than possible using a single antenna.

Is low-power 802.11n possible?

While the use of MIMO gives 802.11n significantly increased data rates, its multiple transmit-and-receive chains also increase power consumption—turning MIMO-based products into potential power hogs and dramatically impacting battery life. That fact alone has raised many concerns. A full-featured 802.11n access point (AP) will typically consume much more power than a legacy 802.11a, b or g AP, although a device’s actual power consumption will depend heavily on the implementation and vendor involved.

To address this power concern, IEEE 802.11n has extended the power management capability of the 802.11 MAC to include the following mechanisms:

• Power Save Multi-Poll (PSMP). This mode is an extension of the Automatic Power Save Delivery (APSD) approach specified in the 802.11e standard for improved Quality of Service (QoS). With PSMP, the client schedules the frames that it transmits as the trigger for delivering downlink frames. This reduces the contention between clients and between the client and the AP, which in turn dramatically improves power conservation in the clients. As a dynamic method, PSMP immediately adjusts to changes in traffic demand by the clients using it. While this mode is often touted as a way for VoIP clients to save power, it is generally best used only in situations with relatively heavy traffic loads.

• Spatial Multiplexing (SM) Power Save. In contrast to PSMP, SM Power Save allows an 802.11n client to power down all but one of its radios and can operate in either dynamic or static mode. In dynamic mode, all but one of the client’s radios is turned off. The client can quickly turn on radios, as needed, when it receives a frame. After the frame reception is complete, the client can return to a low-power state by again disabling all but one radio.

  In static SM Power Save mode, the client behaves as an 802.11 a or g client by turning off all but a single radio. The client’s AP is notified that the client is operating in the static single-radio mode and that it must send only a single spatial stream to the client until otherwise notified.

  802.11n also specifies an optional power save mode—Dynamic MIMO Power Save. This mechanism essentially allows 802.11n devices to dynamically change the number of transmit-and-receive chains that are active when traffic loads are light, such as by downshifting from 3×3 to 1×1 MIMO.

  The wave of 802.11n products

  By employing the mechanisms previously specified, low-power operation of 802.11n is possible. Of course, it doesn’t end there. Today, 802.11n Draft 2 chip developers like Atheros, Broadcom, RedPine Signals, and Qualcomm, just to name a few, are employing their own advanced techniques and process technology to minimize power consumption. Their continued pursuit to develop low-power 802.11n chips is bolstered by announcements like Apple’s use of 802.11n in its next-generation iPhone and iPod Touch models.

  The Apple devices are said to use the Broadcom BCM4329 wireless chip, a complete IEEE 802.11 a/b/g/n system (MAC/baseband/radio) with Bluetooth 2.1 + Enhanced Data Rate (EDR), and FM radio receiver and transmitter (Figure 1). The chip not only adds support for 802.11n features, including the ability to find and join 5-GHz networks, but also incorporates new power savings, such as advanced design techniques and process technologies to reduce active and idle power consumption and extend battery life.

  

  Figure 1. Broadcom’s BCM4329 wireless chip supports a variety of 802.11n optional features such as SpaceTime Block Coding (STBC), Short Gual Interval (SGI), A-MPDU aggregation, Block Ack, Greenfield, and RIFS. During WLAN operation, it achieves low active transmit and receive power consumption and ultra-low power in standby and idle modes.

  Perhaps one of the most significant low-power 802.11n offerings to come to market recently hails from Qualcomm (www.qualcomm.com). Its new WCN1320 N-Stream WLAN chip is the industry’s first dual-band 802.11n standards-based WLAN solution with 4×4 MIMO technology (Figure 2). Based on 65-nanometer CMOS process technology, the chip combines an embedded applications processor, media-access controller, digital baseband, radio-frequency transceiver, and system power-management in a single compact 12×12 mm package. With its 4×4 MIMO technology, it uses four spatial streams to distribute multiple streams of concurrent voice, video and data in either the 5- or 2.4-GHz radio bands. The WCN1312 chip incorporates advanced power-management techniques to minimize sleep, standby, and active power consumption.

  

  Figure 2. With performance of 600 Mbps, Qualcomm’s WCN1320 chip enables the distribution of multiple simultaneous streams of high-definition video, voice and data throughout the home. Sophisticated algorithms take advantage of the chip’s multiple transmitters and receivers to increase data throughput, extend range and overcome interference with a spectrally-efficient solution.

  Conclusion

  IEEE 802.11n is a technology whose time has now come. Expected to be fully approved later this year, it will open the door to a wealth of high-performance mobile applications like HD video, high-resolution imaging and voice over wireless LAN (VoWLAN). Realizing this goal will require special attention to reducing power consumption. Many of the current 802.11n Draft 2 chips achieve this goal through use of advanced design techniques and process technologies, but they also take advantage of the standard-specified power saving modes. Future chips based on the final 802.11n standard will need to follow suit. Doing so will help ensure the success of 802.11n, while also driving continued growth of the wireless connectivity market.

By Ed Sperling

The market seems to be picking up on all sides, even if the hiring hasn’t started in earnest yet. After months of depressing news, there are all sorts of deals being made and had, almost all of them with a low power angle even if that’s not prominent in the announcements. These days, low power is a prerequisite.

The FPGA world seems to be getting lots of attention these days. Aside from a slew of prototypes being built in China with FPGAs, the tools for developing FPGAs are are improving. In fact, they look a lot like the tools being used for ASICs and SoCs these days.

Mentor Graphics introduced logic and physical synthesis support for Xilinx’s Virtex-6 and Spartan-6 lines. Cadence and Xilinx also joined forces to add encrypted simulation models of Xilinx IP with complementary simulation models from Cadence. Xilinx, it appears, has been very busy.  And Actel and Synopsys renewed their OEM relationship for design software for Actel’s low-power FPGAs.

Design activity seems to be picking up in China in recent months. Synopsys inked a deal with Shanghai-based foundry SMIC for a 65nm reference flow. Synopsys contributes the Eclypse Low Power technology and Galaxy and SMIC contributes…well…the customer base to use the stuff. What’s interesting is just how quickly SMIC got to 65nm. Last we heard, their volume market was 180nm.

In the processor world, Intel’s purchase of Wind River passed another regulatory hurdle and the company signed a development deal with Nokia. Those are foundational moves. Whether Intel can break into new markets with this strategy is still in question, though. It depends on just how low it can get the power requirements for Atom.

And if anyone has doubts that there is still money in the consumer market, Apple sold 1 million of its new iPhones in the first three days of its launch. That’s a lot of electronics. If Apple begins designing its own chips, that’s going to require a lot of system-level design tools, as well.