By Ed Sperling
Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine.

While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern over global warming and a steady reminder that smart phones have to be plugged in every night, car companies are shifting their strategy from efficient hybrids to even more efficient plug-in hybrids and electric vehicles, and California has gone so far as to mandate that one-third of all electricity sold in the state by the end of 2020 must come from renewable sources.

This shift in public awareness hasn’t been lost on the chip industry, which has been rolling out some very complex advances well ahead of schedule. Here are some of the most important:

Clouds
The push toward a cloud-based infrastructure is a way of centralizing computing—basically a return to the time-sharing model once perfected by the mainframe and then re-distributed with the advent of the commodity PC server. The data processing world is re-aggregating, but this time with a difference. It’s not just that the computing is being centralized. It’s that the centralization is taking place in proximity of cheap power sources such as hydroelectric power, nuclear plants (for now) and wind farms.

“Cloud leads to big efficiency gains,” said Chris Rowen, chief technology officer at Tensilica. “Now you can put the computing farm where the energy is available. It’s an arbitrage opportunity. It’s not hard to ship bits when you compare that to the difficulty in transporting electricity.”

There’s a clear business case to be made on this front. An estimated 6.5% of electricity is lost in transmission, according to the U.S. Energy Information Administration. That may not seem like a lot until you consider those are high-voltage transmission lines. Bits are cheap, in comparison—even trillions of them—which is why there is talk now of centralizing portions of even base stations. Those parts that do intensive computation with a high degree of redundancy are prime candidates for being located in a data center.

“There’s a lot of computation needed to reduce noise and create a clean signal,” said Rowen. “But there’s also some computing that has to be done locally because there are tough latency requirements.”

Adaptive Body Biasing
Adaptive body biasing has been under serious discussion for the past five years as a way of reducing current leakage by controlling a device’s body voltage, which in turn increases the voltage threshold. The big advantage here is less switching to the off state. The downside is this is has been difficult stuff to design and manufacture.

“This was not seen as a mainstream approach, but now it’s showing up almost everywhere,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “This was seen as a challenging technique to implement, but now TI and Samsung are using it. If you change the body bias voltage, you impact the threshold voltage. You can increase or decrease leakage, as needed, and boost performance.”

Consultant Bhanu Kapoor, president of Mimasic, noted that for some high-performance applications the alternatives such as power gating may be impractical because it simply takes too long to turn on and off sections of a chip. In those cases, body biasing is the only choice.

Atomic-Level Changes
Another technique that has been particularly difficult to master is atomic-level control of channel doping on the manufacturing side. And while most experts don’t expect the process and manufacturing side to offer any huge gains, this one may be the exception.

Scott Thompson, chief technology officer at startup SuVolta, said that by improving the doping technique, both dynamic and static current leakage can be reduced with regular bulk CMOS.

“The problem is that the wall around the channel is leaky and it’s hard to control the shape,” said Thompson. “Strain engineering helps to control the atomic-level analysis. But there has been no other breakthrough other than changing the transistor, and we don’t see a need for that for all architectures.”

At its unveiling last week, SuVolta had lined up support from Fujitsu, Cypress, ARM and Broadcom. The company claims the technology is an alternative to FinFETs, which are more difficult to manufacture.

3D Transistors And Packaging
Nevertheless, the major foundries have committed to building FinFETs at advanced nodes. Intel’s announcement of a Tri-Gate three-dimensional transistor at 22nm has been a major topic in the semiconductor industry. The question is now that Intel has publicly committed to the technology, can it really be manufactured with sufficient yield? And can it be built effectively using the disaggregated foundry model in the near future?

These kinds of questions will remain unanswered at least for the next couple years. TSMC is planning to use FinFETs at 14nm, and GlobalFoundries has been working on the same technology. Nevertheless, the big advantage of FinFET technology is a sharp reduction in leakage while providing a significant performance boost.’

Creating stacks of die also has a huge effect on power, in part because the distances between logic and memory can be shortened significantly. A system-in-package version of stacked die, using interposer technology, is expected to begin widespread production over the next 12 to 18 months, bolstered by the new Wide I/O standard that increases the size of the pipes between logic and memory.

New Materials
Fully depleted SOI, silicon on sapphire, as well as new ways of putting them all together in stacks connected by low-cost interposers that can be made of glass have turned into major research efforts as companies seek to knock costs out of the bill of materials for new chips.

While the FD SOI has been well tested for years by the Common Platform participants, the others have only been used on a very limited basis. One approach now being considered is actually designing chips to run hotter rather than trying to keep the power down. While there are limits to this approach—no one wants to pick up a hot phone—there are times when performance is more important than heat.

Taken as a whole, all of these changes can have a significant reduction in power, particularly when coupled with efficient software code and more customized user controls—and end devices that actually use the power-saving technology that is being built into these chips.

By Ed Sperling

Going Vertical
Now that everyone has gotten the energy-efficiency message down pretty well, the next step is to apply that to specific markets. That’s beginning to happen, too.

A leaked product roadmap from AMD shows machines with all-day battery life and a focus on everything from ultra-mobile notebooks to tablets.

Intel is refining its own message to go after specific markets, as well. The company has created a small-business cloud platform on a pay-as-you-go basis. Given the amount of energy consumed by underutilized servers, this is a huge efficiency play—as well as a way of Intel sidestepping the PC OEM for its share of the profits. 98

Companies such as Tensilica, meanwhile, have been focused heavily on low-power communications, most recently in the LTE and LTE Advanced space. And ARM and MIPS have been divvying up targeting a variety of specific markets. ARM has been focused on mobile devices and a slew of vertical applications ranging from medical devices to other consumer electronics is well documented. Likewise, MIPS has focused on set-top boxes and Android-based devices.

Lowering Carbon Dioxide
The International Energy Agency issued a report today that carbon dioxide emissions must be eliminated from electricity generation to limit the rise of global temperature to 2 degrees Celsius.

The report noted that total output of electricity and heat grew 55% between 1990 and 2008, but corresponding CO2 emissions grew 64.5% in the same period. The report recommends greater efficiency in lighting, heating, cooling and information technology, and powering with renewable sources of energy, nuclear, and carbon capture and storage.

This is good news for the electronics industry, in general, and the low-power engineering portion in particular.

By Ed Sperling

The Other 3D
Intel will roll out processors using tri-gate finFET transistors at 22nm, which it says will sharply lower the operating voltage, boost performance and reduce leakage.

Multigate transistors have been the subject of research for decades, most prominently at UC Berkeley, because they can be used to reduce current leakage and increase density. Going vertical allows more transistors to be loaded onto a piece of silicon, which in the case of a processor is particularly important because more transistors can translate into better performance.

Intel claims the new structures will improve performance by 37% at low voltages. The company said that makes it ideal for small handheld devices, a market where Intel has not done very well in the past primarily because its chips are considered power hogs next to those using ARM and MIPS cores. That statement alone caused ARM’s stock to plunge 7% as speculation mounted that Intel could replace ARM cores inside of some Apple devices. This is pure speculation, of course. Apple never talks about that stuff and Intel hasn’t even intimated that. ARM’s stock recovered rather quickly, too.

Still, most companies have shied away from finFETs because they are extremely difficult to manufacture and potentially can add to the design and manufacturing cost. Intel’s big advantage in this regard is that it still owns its own fabs and develops its own manufacturing process, something that is far too costly for all but a handful of chipmakers.

An alternative to 3D structures is ultra-thin body silicon on insulator, which is now being tested by IBM, STMicroelectronics, Soitec and Globalfoundries. And there is a possibility of mixing things up to include both. But the writing is on the wall—big changes are ahead, and Intel’s move is a first big step in that direction.

TI Pushes FRAM
Microcontrollers have been used for years to reduce power in devices through such developments as multispeed motor control and intelligent sensors, but the real battle of late has been inside the microcontrollers themselves. Companies in this sector have been playing leapfrog with power numbers taking priority over performance increases.

TI’s latest rollout includes an ultra-low-power FRAM, or ferroelectric RAM (previously written as FeRAM). This type of RAM uses 250 times less power than EEPROM-based microcontrollers, according to TI, and can be written at speeds of 100 times faster. FRAM is not a new technology. It was developed in the 1990s by Ramtron, and has been manufactured by Fujitsu for more than a decade.

Apparently major strides have been made in the pricing of this technology since then. TI’s microcontroller is priced at $1.20.

By Ann Steffora Mutschler
The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate.

The ITRS’s most recent projection provides some insight as to current market drivers. The following figure illustrates that the power consumption trend versus power requirements is creating the “Power Gap” akin to the “Design Gap” that the industry dealt with a decade ago, noted Vic Kulkarni, senior VP and general manager at Apache Design Solutions. “This gap is forcing people to think hard on how to manage power at all levels of abstraction.”

Source: ITRS

With mainstream users, there is no controversy about whether abstraction of power and performance needs to shift higher in the designer’s mindset. There is no choice. Designers must shift their thinking from high accuracy/power validation to relative power/power exploration, but making that shift is easier said than done. Designers are not typically accustomed to thinking that way, barring a few architects at some of the largest and most advanced chip companies.

From a technical perspective, the role of power at different levels of abstraction, as well as its nuances and characteristics, is not always well understood.

“There is a need for a lot of education here,” said Shabtay Matalon, Mentor’s ESL market development manager. “I think that power is mostly understood at the transistor level because that’s where people can very tightly correlate power with transistor switching activity, with the threshold levels, with Vdd, and all of those basic equations that people can calculate the static power and dynamic power.”

At the gate level, design engineers still have a good understanding of problems because that involves a relatively low level of abstraction. They can change states on those gates and still clock the flops. Move further along in the flow and things become less clear, however.

“When you go to the RTL things become very vague. Frankly, the challenge here is that there is a limitation what level of accuracy you get at the RTL,” Matalon noted. Raising that to transaction-level modeling (TLM) will offer some relief here, but not until there is more education about how to use these ESL approaches. “That’s the reality. We are dealing with this reality in the marketplace. However, what works well in favor of dealing with power at the TLM is that the payoff is huge, in terms of power optimization.”

Moving up in abstraction from the gate level to RTL it is possible to achieve approximately 5% to 10% improvement in power optimization. “Given that the payoff is so high at the architectural level (up to 80%), on one hand we are seeing that there is a lot of attention to it but on the other hand, I can’t say that the knowledge is yet prolific,” Matalon added.

Where power optimization occurs
While power needs to be planned for at the architectural level, the real optimization of that power happen further down the flow.

“Power optimization really happens purely on the hardware level and purely on the RTL down level so you have all these cool techniques starting at RTL down,” said Frank Schirrmeister, director of product marketing for system level solutions at Synopsys.

The following illustration presented by Synopsys at ARM’s TechCon shows the impact of power optimization techniques at different levels of abstraction and stages in the design.

“One triangle identifies the leverage you have, and the other identifies the time you need to implement, which is the cycle time. The earlier you start, obviously the more impact you have (shown by the wider part of the inverse triangle) and you need less time to do it because you have a shorter cycle time and you can still make changes,” Schirrmeister explained.

Today the majority of techniques are employed at the RTL on the hardware side with the software then trying to optimize things like cache utilization by itself on fixed hardware.

“So now the objective has to be, given the very intuitive notion, that the earlier you start the more impact you have and the more leverage you have on power consumption. We need to move upwards,” Schirrmeister said. “On the architectural level, before you have even decided between hardware and software, you will try to make very early considerations about how to separate it into hardware and software. That’s the architectural analysis part and what people are doing there is really around taking abstract descriptions of the software and the function and figuring out whether the architecture will actually support that. Once you have made the decisions between hardware and software you really have a couple of components running in parallel— in the wider sense it’s block design and how those blocks integrate.”

Bringing these concepts together, Apache believes that an ESL power design flow can be realized by leveraging ESL simulation, ESL synthesis to RTL and RTL power analysis using ESL simulation results. Kulkarni stressed this has been demonstrated successfully by working closely with an ecosystem of an IP provider and a system company.

In addition, virtual prototyping will play a vital role in this upcoming ESL power design flow. As just one example, Mentor’s Vista can be extended to the virtual prototyping space. Traditionally, virtual prototypes have been perceived as just a functional model that only allows people to validate—to do verification of software against a hardware model. This landscape is changing today because software is becoming such a dominant part of a modern design. So much design know-how and IP is implemented in software, and software has such a major role in setting the performance and the power that it is no longer sufficient to provide legacy virtual prototypes that only are functional. Software engineers need a model that is a more hardware-aware virtual prototype where power and timing are modeled so they can evaluate based on their software getting not only the functional spec of the design, but the spec of the design in terms of performance and power, Mentor’s Matalon observed.

Synopsys plays heavily in the virtual prototyping space, while Cadence is still mum on the topic, focusing more on its hardware emulation approach.

The power optimization challenge
Still, as we go up in abstraction, designers need to try to understand software issues and how the software relates to hardware.

“As you get into advanced power management schemes in the hardware a lot of times that’s controlled by the software, so how effective is the software at doing that?” asks Jack Erickson, product marketing director at Cadence. “Ideally, you’d like to be able to run your software on your hardware and have a better understanding of how much power is consumed by software. The more you can do in the software before you ship the product the better. If you can get your chip into emulation and run your actual software in emulation and examine the power effects of your software, that’s late in the hardware design cycle, but you can have large effects on your software before you ship your system.”

The biggest challenge is that it’s really a new space, he said. “Folks have started to worry about power only in the past few years and now we’re also talking about moving up to a higher level where they have even less experience typically. The combination of those two is very difficult,” Erickson concluded.

Power Struggle Heats Up—So To Speak
The battle between ARM and Intel has come down to a fight over power—which one can run at the lowest power.

This is becoming particularly important in the tablet market, which is becoming the tool of choice for consumers of information—executives and salespeople on the go—rather than creators of content. And it’s one that could seriously eat into Intel’s mainstay computer market.

Intel’s latest salvo in this war involves the next version of its Atom processor, code-named Oak Trail, which is aimed at the tablet market. That will be followed by the 32nm Cedar trail. New in the technology is what Intel is billing “all-day” battery life and “enhanced deeper sleep.

Despite its prowess in the PC world, though, this market appears to be ARM’s to lose. Apple’s iPad runs on an A4 chip, which is a 45nm package-on-package that includes an ARM Cortex-A8 paired with a graphics processor. ARM also has made some inroads into the Android tablet space along with MIPS, which was one of the first processor makers to embrace Android. Both run at lower power than Intel’s Atom chips, in large part because there is no x86 legacy to support. http://en.wikipedia.org/wiki/Apple_A4

By Ed Sperling
Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed.

Prapanna Tiwari: UPF and CPF are text files that capture the power intent of the design.

Power management is one of the main problems we’re trying to solve in every design. The goal is to operate every given part of the chip at the lowest voltage you can get away with. If you can shut it off, you do that. If you can’t shut it off—and you can’t shut off memories—then you reduce the voltage to the lowest possible level so you don’t lose as much through leakage. From a verification standpoint, what you used to write in Verilog would appear in silicon and that was all there was to it. That’s no longer true. Now there is this idea of power intent that has to be captured. It has structure to it. It has semantics, and it has simulation sequences. It impacts every part of a design. (See Fig. 1)

Fig. 1

The product behavior has two components. One is the design. The other is the power. Verification needs to take care of this.

The power intent itself has two aspects. One is static. What are the regions? How are the regions partitioned? How do they map onto my design hierarchy? That’s where UPF comes into play. It says these are the domains. These are the different level shifters you’re going to insert in your design. That’s the structure.

But there’s a second aspect, which is dynamic. How are you going to exercise these different voltage regions on a chip? What is allowed, what isn’t allowed? If ARM or MIPS delivers cores to their customers, they need to let them know here’s how you should use it. There is no way in our current methodology, when you deliver a Verilog model, what voltage levels its supposed to be instantiated at. There’s nothing in Verilog that lets you do that. Different customers will use ARM and MIPS cores using different power management techniques, different voltage levels, different process nodes. How do you let them know you’re not supposed to do certain things?

If an IP can provide constraints that you can’t use IP in a different way, that’s where power intent comes in. You can do that from a functional standpoint today. You cannot do that it in a power-aware model. There’s no way to figure out where IP gets used. Context is missing. (See Fig. 2)

Fig. 2

Even within the same semiconductor company you will see different modules have different design owners. You don’t want anyone to be using IP in the wrong way even years from now. There is IP in designs where no one has any clue where it came from. That’s one of the key challenges for an IP provider—to generate behavioral and verification IP, not just with the VHDL view but with the power-aware view to go with it. If you can deliver this, it will eliminate an enormous amount of risk that it will reduce the cost.

For any verification, there are three pieces. There is the testbench, the design itself and then assertions and coverage. (see Fig. 3)

Fig. 3

In the overall verification, the testbench needs to be power-aware. IP users need to be able to monitor any region of the design. The way IP is growing, it may have many power domains inside. It may even have its own power controller that reacts to events from outside the IP. A customer testbench needs to know power events and sequences in different parts of the IP. Otherwise you have no idea if the IP really shut down or not.

You also need to be able to write models for the IP. One user may be at 1.2 volts. Another might be at 1.0 volts. Different signals will react differently. All this behavior needs to access the power information.

All of that power information needs to be available, and it should be context-free. And last but not least, assertions need to be power-aware. When the system is shut down, how is the IP being isolated, what are the level shifters being inserted?

To solve this, you need to be able to merge UPF and HDL into one. In your RTL you should be able to query information and build models around it.

Rob Aitken: If it’s not clear what are the issues are involved, what would make it clear?

There’s an existence proof. In one chip we had some RTL and a power spec and it turned into a chip and the chip worked. There were multiple decades of ARM experience, the latest IP and EDA tools, access to IP designers, skill in all available EDA tools and some magic smoke. But what if you don’t have all that? How many of those things do you need?

In addition, there’s no one thing called IP and there are lots of different uses for the same IP. There’s one group that says, ‘Whatever it is, give it to me, I want it to work and be done.’ Then there’s another group that might say, ‘I don’t care what you think should be done with this IP. Give me the parts and I’ll do it myself.’ What we really want to make sure of is that the standards don’t interfere with the use models and that they cover all of the possible use cases.

Context also matters. We like to talk about something like an always-on buffer. If it’s in a system where there’s a battery connected to it and part of the processor is shut down, that has a different meaning than when it’s plugged into the wall and the system is turned off. That always-on buffer isn’t always on anymore. It’s just sometimes on.

And what happens if I run my IP at 0.6 volts? If no one designed it for that, will it work? Maybe.

There are all sorts of other clever things we can do. An SRAM will retain data at much lower voltage than you can read or write it. You can have SRAM-dependent behavior. If it operates at a very low voltage you can store data, but if you write it, it will fail. Trying to model that in a high-level language is an interesting challenge.

From a soft IP standpoint, you can say here’s some RTL and here’s a power description. You only need four things:

1. What are the atomic power domains? Are there more than one?
2. If you shut it down, some key element of the state needs to be retained. If you haven’t thought about that initially, it’s pretty much every flip-flop.
3. You need to know the signals that need to be isolated.
4. And you need to know the legal power states and the transitions between them.

If you have those four things you have the power intent for soft IP. That’s not enough to actually build something. Then you take the low-power intent and refine it. (see Fig. 4)

Fig. 4

Based on the various failures we’ve had, here are some things not to do. First, avoid non-contiguous power domains. When in doubt, align it with the logic hierarchy.
Second, don’t use clock gating on both ends of the clock. That ties you to specific libraries. Third, avoid partial retention within a power domain. Don’t try to retain some things but not all. It leads to weird behavior. And make sure that your power domains clocks and resets can be controlled externally. One other thing I would add is avoid test power or scan chains crossing multiple domains because that leads to interesting test challenges.

By David Lammers
A group of companies within the SOI Consortium, including ARM, GlobalFoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—said they have created 20nm Ultra Thin Body Silicon on Insulator (UTB-SOI) test circuits that meet the needs of the smart phone and mobile systems markets.

Silicon was fabricated at IBM’s Albany Research Center, using SOI wafers from Soitec with thin silicon and buried oxide (BOX) layers. An ARM Cortex processor, with memory, was fabricated as the prototyping vehicle, with reliable operation down to 0.7V, said Horacio Mendez, executive director of the SOI Consortium. The consortium said performance was roughly double the levels possible with bulk planar transistors.

The test circuits were based on planar, fully depleted transistors, built on SOI wafers with a top silicon layer of about 10 nm and a BOX layer of about 20 nm, Mendez said. In the past, SOI has been limited to high-performance systems. Mendez said the cost of an UTB-SOI substrate has declined quickly. Besides Soitec, SEH and MEMC are beginning to ship SOI wafers with the ultra-thin layers, which assures semiconductor manufacturers of a stable supply.

Also, IBM and its research partners have developed transistors targeted to the low-power market, he said. Partially depleted SOI has been targeted for high-performance markets, with transistors that were necessarily more leaky that their low-power bulk cousins. “This does not mean that low leakage transistors are not able to be fabricated in the technology; they can be,” Mendez said.
In addition, a back gated FD-SOI device can adjust the back gate bias to reduce leakage even further, adding yet another lever to control static power, he said.

Details of the test silicon will be discussed next week at the Mobile World Congress in Barcelona.

By Ed Sperling
The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power.

Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party IP is actually used, the interaction of multiple states, and even how software utilizes a processor.

Consider, for example, a virtualization layer that is added into a consumer device—an approach now under widespread consideration among device manufacturers because not all of the functions can take advantage of multiple cores. At the architectural level this makes perfect sense because virtualization simultaneously maximizes performance and utilization, which is a winning formula for efficiency. The problem is that using more cores also uses more energy, and the distribution of average use may vary greatly depending on applications or the interaction of applications. Running multiple games, for example, could drain a battery in a fraction of the time it would normally last for a voice call or playing music. And multitasking can greatly accelerate battery drain.

That’s only part of the issue, though. Higher utilization generates more heat in the form of dynamic and static leakage current. The more functions in use, the greater the dynamic current (or switching current). That can affect everything from signal integrity to the ability of memory to function properly to the overall lifespan of a device. And it can make modeling extremely difficult.

“This is a function of the operating system, or whatever software layer you’re using,” said Rob Aitken, an ARM fellow. “You determine the wake-up time and if it’s supposed to shut down different cores. But you can’t power it up right away because the IR drop would be too large, so you have to power up slowly. That means you have to model a speed limit on how quickly it wakes up.”

The challenges grow as more voltages are added for different CPUs. “If you’re operation a CPU at one voltage and the next at a different voltage you get an IR drop across the buses,” said Aitken.

New tools
Most of the large chipmakers have developed their own power models, which are specific to their particular designs. This isn’t something many chipmakers see as a core competency, however, which is why a number of EDA companies have put stakes into this market.

One of the most ambitious efforts comes from Apache Design Solutions, which has created a chip power-modeling tool. It’s an important start, but the accuracy depends on a lot of other factors beyond Apache’s control. That explains why Apache is working with the GSA to create some standards in the IP world.

Startup Parallel Engines is providing details about the available information on power, as well, for about 12,000 pieces of IP. But the accuracy of that information varies, in part, depending on how it is used.

“The power model of a chip needs to include accurate characterization of the multiple IPs that are included in the design,” said Dian Yang, Apache’s general manager. “But if those vendors supplying the IP do not give enough details about its power parameters and behavior, the resulting model will not be very accurate. Also, an accurate model needs to know things like the impedance of the die. But a simple power number based on an average estimation does not tell you that. You need a model that is based on transient analysis to address the dynamic behavior and the true impedance of the die.”

All three of the largest EDA vendors have worked to build power intent models, which help greatly on the functional verification side. Both Synopsys and Mentor Graphics back the Unified Power Format, while Cadence backs the Common Power Format. There has been work to bridge those two specifications by major standards organizations such as Si2 and Accellera. But no matter how much the EDA vendors and standards organizations insist that those differences are easy to bridge, that’s not the experience of chip companies.

“I have major issues with these standards,” said Sunil Malkani, director of IC design engineering for the GPS group at Broadcom. “The standards for power intent don’t work together, and sometimes the previous versions of a those standards don’t work with the current standard.”

He’s not alone in that viewpoint. John Busco, senior manager for design implementation at Nvidia, said the very existence of competing standards defeats the purpose of having them in the first place.

“I’m a little more forgiving when the standards don’t do everything you want them to do,” he said. “My pet peeve is dueling standards like CPF and UPF.”

While EDA vendors publicly don’t like to challenge their customers or potential customers, they say privately that more often it’s the fault of the IP and the way it’s being used than the power intent models themselves. “The user can capture the intended behavior of the design already, and if they add a few more lines of code involving the IP they can make sure the power intent is captured, too,” said one EDA insider.

Mixed models
The power intent specifications are particularly important in the verification stage, which remains the most time-consuming part of the design process. Those design intent specs are integrated with the power models, allowing engineers to map the power limits of the chip and the safe parameters for operation. But in the IP world, and even when it comes to reusing blocks and subsystems, there are not always power models available. At that point, the best that can be hoped for is that the existing models are power-aware.

“The biggest problem our customers are impacted by is legacy models,” said Prapanna Tiwari, CAE manager at Synopsys. “They were created when low power was not a concern, and the models don’t comprehend voltage. The second problem is that even if they want to create a power-aware model, they can’t do the entire power network in Verilog and hook it up to every power model that is being created.”

Limiting choices
Another major problem is the sheer number of choices that are available to designers and architects of these chips. The number of variables increases with each new process node, as well as the proximity effects of other components in an SoC, packaging, what software is being used and how it is being used, multiple cores, multiple states, multiple voltages and ultimately 3D stacking. Add to that multiple IP options and the effects on power models become overwhelming.

“We may well see standards for limits on the number of power models that are available,” said ARM’s Aitken. “If you look at the 1801 standard (UPF 2.0), there are certain things that are legal in it and certain things that aren’t. This could well be the direction.”

That doesn’t mean having a menu of choices will make SoC development any easier, but at least it would limit the number of variables that engineers have to wrestle every time they decide to integrate third-party IP or re-use their own IP. Still, there are a lot of changes to be made before even this step happens. As with all SoC engineering, nothing is guaranteed and not everything is predictable.

By Ed Sperling
AMD jumped into the low-power market with a new version of its Fusion chip for the tablet market, which the company claims can reduce energy consumption by 40%. That puts AMD squarely in competition with Intel’s Atom, ARM’s Cortex A9 and A15, a swath of MIPS chips aimed at Android, Apple’s A4 and probably some others that sources say will be produced for localized markets. AMD also rolled out an updated parallel processing development kit, which is absolutely essential for performance.

The U.S. Air Force is developing a new ultra low-power RF transceiver to preserve battery life in military sensors, including radar and infrared cameras. The less power drawn and the lighter these devices can be made, the smaller they can be designed and the longer they can be in the air.

Toumaz, a U.K.-based developer of low-power telemetry technologies, introduced an ultra low energy radio for wireless sensor networks. The company says the device can run at 1 volt using a single button-sized cell battery and consume less than 3mV of continuous power. That should make for some interesting application possibilities.

By Ed Sperling
Microsoft is looking for 16-core servers for future data centers using Intel’s Atom and AMD’s upcoming Bobcat processor lines in order to lower power consumption in data centers. The announcement, made at the Linley Data Center Conference in San Jose this week poses an interesting dilemma for Intel and AMD—as well as challenges for ARM and even Microsoft.

On the Intel and AMD front, the big question is how such a shift would impact revenues, given the fact that both companies have used the power-saving lite versions of their processors in much lower-cost devices such as netbooks. While some data centers are experimenting with Atom-based arrays for servers, the real savings have come from virtualization to improve server utilization, and cloud-based strategies to quickly ramp up and ramp down compute capacity as needed.

Virtualization has been extremely successful. Most large companies have adopted it to some extent because it costs money to power and to cool a server, whether it’s utilized at an optimal 60% to 85% or whether it’s running at 5% to 15% utilization, which was the industry average prior to virtualization. The problem for Microsoft was that the virtualization was done using VMware and Citrix software, not Microsoft software.

Without virtualization, it’s not entirely certain whether many applications will be able to natively take advantage of 16 cores, considering most currently don’t use more than one or two. In fact, the main applications that can be effectively parallelized are databases, graphically-oriented applications such as Adobe Photoshop, and highly computational scientific applications, where the biggest threat to Microsoft and Intel is Nvidia.

Microsoft’s approach will likely be a more effective management of virtualized applications across those cores so that cores can be turned on and off as needed, but it’s certainly not the only company that sees that opportunity. Virtualization currently uses all the cores indiscriminately, but much more intelligence is being added into the virtualization and middleware layer to cut energy consumption.

For ARM, that means even greater engagement with both Intel and AMD, where it will have to push lower power while defending its performance and the competitiveness of Linux. Given ARM’s grassroots type of ecosystem marketing, it remains to be seen whether it can rise up to the din of the marketing machines of its new competitors. Lower power consumption is a good story, but in the enterprise so are performance and deep relationships.

The old adage that no one ever got fired for buying IBM can now be applied to Microsoft, Intel, AMD and to a lesser extent VIA. Most IT departments have no history with ARM, except in handheld devices, and IT is one of the most conservative purchasing groups on the planet because the stakes of making a bad decision can be monumental. Breaking into the mobile market takes months. Breaking into the IT world can take years, and sometimes even decades. This isn’t a battle fought on technological merits. It’s like a medieval siege. And while ARM may meet the technology challenge, it remains to be seen whether it can meet the long-term marketing challenge.

In this part of the market, the adage about IBM is still true. IBM’s mainframe sales are up, in part because mainframes are still the most secure and effective virtualization environment. IBM invented virtualization in the 1960s, incidentally. And on its newest machines it’s offering water cooling once—which can further cut power consumption because it costs less to cool.