Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

LPE: What is concurrent design and how has the definition changed?
DeLaCruz: This is a legacy we created for ourselves because physical design teams can operate separately from CAD tool developers and packaging and everyone throws what they’ve finished over the wall. Concurrent design is a way of undoing the damage we’ve driven into our culture. We can do this by creating CAD tools that allow concurrent work on the same thing. Cadence, Synopsys and Mentor are all trying to create tools for this. Another way of doing this is by getting your people to talk together more effectively. That’s difficult because people have been told they should work in different departments, not talk to each other because things get messy that way and take too much time.
Gianfagna: There are two things that caused the problem. One is that we used to do things sequentially. You did placement, you did routing, and then you’d tweak the placement and timing would be closed and everyone would be happy. You can’t do that anymore. Now when you change placement you break timing. When you fix timing you mess up clock synchronization. When you fix clock synchronization you mess up power. And they’re all related. One breaks the other. So there’s a need to simultaneously optimize. Beyond that is an even bigger problem. The supply chain is now spread out. You’re dealing with a separate packaging company, a separate substrate company, and five or six IP developers.
Brambilla: There’s another level of complexity. My team does turnkey designs and ASICs. When it’s turnkey it’s easy. When it’s an ASIC you also have a huge separation between the customer doing the RTL and us doing the rest. There’s a big discontinuity. When people want to go to the next node, sometimes they’re approaching it with a software mentality and don’t realize that a forward loop becomes a million gates. Once upon a time we did software-hardware co-design. Now you have separate entities who say that’s your job and this is my job, and we have to cross-educate them.
Janac: You’re taking a serial design and that serial design has gotten longer, and now you’re trying to make it parallel. The parallelization of that process cuts the time. The answer is that you have to consciously create islands where this parallelization works and then have very well defined communication between those islands. Let’s take this problem of the RTL designer and physical layout separation. If the physical layout guys can get the constraints up front into the RTL, then the physical layout people will not get junk from the RTL designer. There needs to be a well-defined set of interfaces between those islands.

LPE: But this is all getting more complicated, right, and not just within a single block or subsystem? You have proximity effects because of density, you have electrostatic discharge issue, power issues, heat issues, software that may or may not work across the whole thing, and version-control issues on IP.
Janac: Within these islands you have to take into account an increasing number of constraints.
Gianfagna: We’re hearing it with timing constraints. The front-end guy needs to worry about timing constraints more. What we hear is that’s a back-end problem. It’s hard-wired into everyone’s brain that it’s a back-end issue, but that’s wrong. Is there a human issue here? As an industry we don’t have a great track record of changing quickly.
Janac: Atrenta had an advertising slogan that I liked, which is that timing closure begins above RTL. The earlier you solve some of these problems the cheaper it is to solve them.
Gianfagna: Intuitively that makes sense. When it comes down to the real world that isn’t always the case. People don’t always approach it that way.
Janac: But then their chips don’t come out. It’s hard to tell an RTL designer they have to worry about congestion. But if you give them a capability to eliminate that congestion, such as cutting wires in half, then they’ll use it. But if you tell someone they should speak French it’s not going to happen unless you teach them to speak French.
Brambilla: There are several issues here. I wish we could still work in islands. The islands are getting blurred, or they require more people from different functions to work in them.
Janac: You need to build bridges between the islands.
Brambilla: But you also need to populate those islands. They’re no longer homogeneous. We have started on 28nm devices. These are 17 x 17 or 18 x 18 mm. You’re talking in excess of 100 million gates for non-repeating logic. The graphics guys are doing 100 million gates but it’s copies of the same thing. There is still a problem of validation, but from a design point of view it requires a different amount of resources. When we’re doing a communication ASIC of 100 million gates, that’s all random logic. You have people putting 4x more gates in the same area with greater productivity. They don’t have time to worry about congestion. And they’re moving up, up, up in terms of higher-level coding languages. If I want to port to double the frequency I might have to change my bus width rather than just doubling the clock.
Gianfagna: That’s a microarchitecture change.
Brambilla: But you can’t do that in Verilog. At that point you’re talking to a software person or an algorithm person, not to a designer. Try to explain to that person what the structures are that can cause congestion. Sometimes I have trouble explaining memories to a designer. They don’t get it. There are Verilog designers who don’t understand what their Verilog becomes in gates. How do we ask them to be more proactive?
DeLaCruz: We’re victims of the way we used to be organized. I keep hearing this term ‘islands.’ I think it’s a big crutch. We’re just putting Band-Aids on this. These islands need to be moved. Within eSilicon, rather than the physical design team creating something that can cause problems with packaging, and packaging causing problems with PCB design, we moved the line. We overlap physical design significantly. The packaging team does floor planning, pad ring layout, and all the SSO operations on the die. By the time it’s gotten to packaging we know it’s done properly. All of our packaging personnel are mixed in with our physical design team. That’s blurring the line. The islands aren’t being kept separate. As we go to through-silicon vias, is that interconnect a packaging issue or a design issue? You can’t have the delineation anymore.
Janac: Why not give them the tools that isolate them from the complexity?
DeLaCruz: Let’s say you have a chip design that can be a certain die size, in round numbers 4 x 4. The physical design team wants to add more signals. If you go to 28nm, you’ve got all these signals and your die has to grow. They don’t know about all these things like silicon interposers, which would translate that 4 x 4mm die into an 8 x 8mm die.
Janac: You can have an interconnect that contains all the wires. Do you put all those wires on one die or on another die? You’re giving them the tools to deal with that.
DeLaCruz: You have to cross-train because 3D silicon is not a physical design issue. It’s a packaging issue. There’s a methodology in physical design. There’s an issue in packaging. It’s a little bit of each, and you can’t have different people doing each.
Janac: It’s a combination of training and methodology. You have to train your designers and tell them that a 3D toolkit is part of the methodology they have. And then you have to give them the tools to successfully implement their technology.
Gianfagna: You can come up with the tools. We in EDA can come up with the vision. But it doesn’t mean anything unless there’s a mandate from the top down that this is the way things are going to work.

By Ed Sperling
ARM took a new tack in its war with Intel. The company is working on a Green Cloud Services project using the ARM architecture in conjunction with Nokia, IMEC, EPFL and the University of Cypress to create a 3D package with low-power processing. This is particularly interesting in light of gamers using Intel Atom-based servers.

Along the same power-saving lines, Actel introduced its power management solution for its SmartFusion mixed signal FPGA, complete with a reference design and a configurator for power sequencing and trimming. Given Actel’s focus on low power in its other chips, this isn’t all that surprising.

Also on the low-power front, Virage Logic introduced a big update of the open source GNU and Linux toolchains for its ARC processors, which will soon belong to Synopsys. That puts Synopsys firmly into the open source world, as well, with interesting implications.

Arteris joined forces with other EDA and IP vendors supporting TSMC Reference Flow 11, this time with network on chip interconnect IP. This is more like networking the industry on chip.

eSilicon will provide logistics services and production operations to Ember and Pixim. This is an interesting extension of supply chain expertise.

Mentor Graphics rolled out its commercial embedded Linux platform for Freescale, building on a strategic alliance the two had signed in April.

Mentor also won a couple deals with Mindtree for its Questa functional verification and with Autoliv for machine programming.

Both Synopsys and Cadence trumpeted successes with their products. Cadence global services enabled a 65nm TD-LTE baseband chip from Innofidei, a company with operations in Taiwan and Beijing. Synopsys, meanwhile, demonstrated interoperability between DesignWare IP for PCI Express 3.0. The company also awarded the Tenzing Norgay interoperability achievement award to IEEE-ISTO. We’re not sure what the famed Sherpa had to do with interoperability, but congrats.

Arteris, which makes network on chip technology, announced it is working with ARM to provide interoperability with ARM’s AMBA 4 bus specification. This is an interesting deal. On one hand, it expands ARM’s options with a faster and easier interconnect strategy. On the other, it moves Arteris deep inside ARM’s ecosystem, which includes 750 companies at last count. Many of those companies are on the short list for handheld devices such as smart phones—so far the leaders in low-power design—which now have to support more I/O options and communications protocols in a very narrow power budget. And not to be forgotten, until now most outsiders viewed these two companies as competitors.

Virage Logic rolled out new D-PHY and controllers for the 40nm low-power process across a number of standard interfaces such as the mobile industry processor interface (MIPI) and the camera serial interface receiver (CSI Rx). The company says power is down 80% and area is down 70%.

Mentor Graphics’ Calibre DFM is now qualified for TSMC’s 28nm processes. For anyone who thought the Roaring ’20s was something out of history, wait until you see the sounds coming out of the semiconductor design world over the next couple of nodes.

IAR Systems, which makes middleware for microcontrollers, threw its support behind Actel’s new SmartFusion chip. While this is a good deal for IAR—SmartFusion is the first chip to combine a programmable analog subsystem with an FPGA on a single low-power chip—it also gives Actel access to the industrial, medical and communications markets.

Synopsys completed its acquisition of CoWare. It now owns a company in which rival Cadence once invested, not to mention the vast majority of the commercial software prototyping market.

Cadence, meanwhile, acquired Taray, which makes tools to put FPGAs onto printed circuit boards. This is an interesting move for a couple reasons. First, it’s something of an acceptance that there are plenty of tools around for designing FPGAs and the most successful ones are those made by the FPGA vendors themselves. The reason? They’re cheap. Second, it moves Cadence out of the fray of whether FPGAs actually need more advanced tools made by Mentor and Synopsys and addresses a very real problem, namely putting the chips on a board. The main competition in this space will likely be Mentor Graphics.

Is this considered an adjacent market or a sharp left turn? TSMC broke ground on an LED lighting R&D center. The focus is LEDs and solar power, according to TSMC Chairman Morris Chang.

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”