By Ed Sperling
Near-field communications has attracted an enormous amount of attention of late. Banks are allowing customers to scan checks from their cell phones and, increasingly, smart phones are being used for everything from airport access to paying bills at the grocery store. They’re even being used for parking lot fees.

But there’s a hidden pricetag behind all of this—the amount of energy needed to drive these transactions. That has led to a slew of development efforts behind the scenes, with the latest entry showing up this week from Texas Instruments. TI’s is bragging that its new NFC transceiver uses half as much power as the competitors’ products, running only as high as 120 milliampere in full-power mode and less than 1 microampere when it’s powered down.

TI clearly is not alone in this game of leapfrog. Companies such as Broadcom, Qualcomm and ST are racing in the same direction. But what’s interesting is that energy consumption has become the marketing focus rather than performance. The transceiver comes with eight possible power modes, which is particularly important in matching user preferences with the end devices.

EVM Board. Source: Texas Instruments

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: Has there been any progress in providing a feedback channel for software development to link that with the hardware design effort?
Low: Our software team is larger than our hardware team now. The consumer and the market are driving that.
Castagnetti: Part of that has to do with whether there are good models. One issue is how you predict power consumption. If you write code this way or that way, how good is that number compared to the end number? That’s part of the issue.

LPE: And if you have your cell phone on and you’re searching for base stations, you’re consuming power. Accelerators are running in the background and not even showing up on your dark screen. But is this even being considered by developers?
Low: We certainly have the use case model for this scenario.
LPE: The foundries have a super low-power process. What’s different there?
Brotman: Pieces of that are fundamental engineering—engineering the channels for low energy and high k/metal gate structures. Those are all part of putting together a transistor that is low power in operation and low leakage when it’s in standby. On top of that we have reference flows in place to do power predictions on the devices.

LPE: So how much will the process save us over the next couple nodes?
Brotman: We’re going to see improvements, but as we push down in process nodes we’re also going to have penalties. To some extent these things partially negate each other. We get improvements from node to node. High k/metal gate is showing improvement going from 45nm to 32. High k at 45nm is less leaky than at 28nm.
Castagnetti: The past improvements we’ve seen will never offset the designs again as we double the number of transistors and increase data rates.
Low: As we move to 22nm/20nm, the Vt level is decreasing. The EDA vendors have to make sure the flow is optimized for lower portable power.

LPE: What happens when we go into stacked die? Will that give us a big boost in power savings?
Brotman: 3D packaging will result in power advantages. Wide memory sitting on top of a graphics core will allow you to drive the power down. There will be lower parasitics and less inductance, which will allow you to drive that power down, as well. There are other things we need to take into account with 3D, though, such as temperature management. If we don’t deal with those, they can impact power in the wrong direction.
Low: When you stack the die you minimize the interconnect distance. That can help reduce the dynamic power. But thermals become a problem. As temperature increases, leakage increases, so you have to make sure that the temperature does not become a problem.
Castagnetti: The true 3D, which will offer a significant improvement in power savings, is quite far away. From a 2.5D approach, one of the key promises from a wide I/O is shorter latency. You will be able to push more data through. That’s a fundamental benefit.

LPE: How close are we to 2.5D?
Brotman: We’re pretty close. We’ll see the first ones quite soon.

LPE: Will we immediately see a power savings?
Brotman: It depends on the type of stacked device. If you’re doing memory on logic, we can cobble something together that will work. If we’re talking about logic on logic with different process technology, doing floor planning and partitioning will take more work.
Castagnetti: Even the decision process of how to partition and what to partition is not in place today. To make the best tradeoff from a power standpoint, what do you put in each node? That’s a tough nut to crack.
Low: First of all, we have to make sure we have the tools to put the design together. Second, we have to make sure we understand whether the design should be for 40nm or 28nm. What is the most cost- and performance-effective, while achieving time-to-market?

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: How do we get the message out that there is frequently more designed into an SoC than is being used by OEMs—and which could greatly benefit the user?
Low: We have a long way to go. We have hundreds of knobs tin hardware that can be turned by the software to take advantage of low-power circuitry within the design. You need to optimize the software to take advantage of what is available to minimize power.
Castagnetti: No one wants to take risks in this industry. As we start seeing power limits becoming unachievable, customers are willing to go that extra step. So we are definitely seeing much more aggressive adoption of power management techniques, even in the wired space where you could argue that power is unlimited and available. But there is a challenge in the wired side that needs to be addressed.

LPE: Is power now a differentiator in chips?
Brotman: From a foundry point of view, giving our customers capabilities to model all of these effects is critical. That’s a differentiator for us. As far as the marketplace goes, customers that have better power and performance will win.

LPE: Who’s responsible for the power models?
Brotman: The base power models are modeling device performance. That’s the foundries’ responsibility to provide. We also have to provide reference flows that people can look at to take advantage of these models. How do you put this into a design that generates proper performance?
Castagnetti: That’s a starting point—having good models at the transistor level that correlates to silicon. The other piece involves high-level models. So if you have a piece of IP, what are the power numbers associated with that? That may involve the IP providers, or maybe the overall system piece. And finally, just understanding from a system-use case which is the worst-case condition is critical. In the past, we have measured in-system power and found some interesting surprises.

LPE: You’re talking about a free flow of information across a disaggregated supply chain. How do you break down the barriers to make that happen?
Castagnetti: You have to show the value of what it means to be able to correlate predictions of worst case or average vs. what you can measure so you can make a more intelligent choice.
Low: As an IC designer we provide chip-level power models to our customers so they can use this model for their platform/system power analysis.

LPE: Are you getting that kind of information back from the foundries?
Low: No.
Brotman: We’re providing models at the transistor level, parasitic extraction models, libraries and power models. The models you’re talking about are higher-level.
Low: Yes, very high-level.
Brotman: That isn’t something the foundries can provide.
Low: We’re taking all these models from our foundries and building a chip-level power model that was discussed earlier. Another step up is building a power model based on use case at the platform level, for example.

LPE: Are the tools there to do this kind of power measurement?
Low: Yes and no. We can leverage some of the tools we have today to analyze the power, but we still have a way to go with improving the power methodology/analysis. We have UPF and CPF, but they are not compatible.
Brotman: There are some tools that are adequate for doing predictions at the low level. At the abstract level, there are interim tools today for how different software architectures are going to impact performance and power. There is definitely room for improvement.

LPE: Where is the low-hanging fruit in power savings? What can we do that we haven’t done so far?
Brotman: Turn off your phones.
Castagnetti: One thing we’re doing is designing for worst case with the maximum number of corners. Maybe we need to be able to live with a design that isn’t bulletproof. Whenever we do this bulletproof design we increase the power requirements.

LPE: That’s market-specific, right? A cell phone doesn’t matter as much as a pacemaker, for example.
Castagnetti: That’s correct.
Low: The ability to turn the logic off when it’s not needed enables us to minimize the power requirement. Other techniques like dynamic voltage and frequency scaling allow you to lower the frequency when the performance is not needed. Higher VT class is for leakage reduction. Tri-Gate enables engineer to achieve performance and power with further reduction of the operating voltage.

LPE: How low can we actually drop the voltage? If we drop the voltage of memory too far we lose data.
Castagnetti: You can design chips with a much lower operating voltage. The question is how much performance or throughput you want to maintain. There is still a performance-voltage tradeoff. But fundamentally, you could switch the question around. If you want to be at 300 millivolts, how do you have to design your system?
Brotman: Yes, it’s a matter of what kind of performance you want in your system.
Low: You have to trade off that ability. Digital logic can use lower operating voltage than a memory bit cell. This operating voltage level really depends on how much performance you want to achieve at that level. It’s a use-case model and it dictates how low the logic voltage level can bring down to.

LPE: Can software be written more efficiently so we can seriously drop power and boost performance?
Castagnetti: We at least should look at that. Software designers should consider how much power their software consumes.

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: At 28nm we have clock gating, power gating, dynamic voltage switching, power islands, power states, and a whole bunch more engineering miracles. Are they working?
Castagnetti: The methods are there. In some occasions they have been proven. But do we know which methods to use for which designs? That’s where the challenge is today.
Low: We are already deploying all of these tricks to our design since 65nm nodes. We are leveraging all we can, and it is increasingly important as the complexity of logic keeps increasing as we head down to next technology nodes.
Brotman: There are a number of things we are trying to do in the physical space. We’re providing a small amount of power savings with things like 3D devices. We also try to provide a lot of things in the flows to show people how to conserve power. But the biggest way to achieve good power savings is on the system level.

LPE: But some of the most interesting power savings developments recently are out of the process side, right? There’s Intel’s Tri-Gate, better atomic-level control on doping, and then there’s a push into fully depleted SoI.
Brotman: You have to use all of those things. But there are things that can be done even on planar chips at the system level that can impact power.
Castagnetti: There’s still that hope that process technology will come to the rescue, but we have to realize that is unlikely. Everyone is talking about moving to the next node to save dynamic power, and now leakage is coming down. But as long as you’re doubling your transistor density every node your power density will go up and therefore the issues you have to solve from a power delivery and power management and thermal point of view are here to stay.
Low: At 28nm, we started seeing an increasingly finer granularity of VT options to combat leakage. However, the higher the VT class, the higher threshold voltage of a device. This limited our engineers to lowering our operating voltage while maintaining acceptable performance. The Tri-Gate concept is certainly the right direction to optimize both dynamic and leakage power.

LPE: One of the hardest concepts to understand is that there is no such thing as off. Does it really matter if you turn something completely off?
Castagnetti: If you keep switching on and off then potentially you can burn more power. But customers are trying to make more use of power-island types of approaches. There is another component, as well. It’s very expensive to do a complex chip today. You want to leverage that across multiple platforms, so you want to maximize your power efficiency across those platforms by being able to turn things off when you don’t need them.
Low: You have to be careful when constructing power islands to the power delivery network that there isn’t any hidden path between different power domains. That’s very important.
Brotman: The system itself has to be efficient when you’re shutting things down and bringing them back up. Too often that’s going to burn more power.

LPE: So how do you figure out what to shut down and what not to shut down? An optimum configuration depends on who’s using the device because it varies from one user to the next.
Castagnetti: Even in the wired space we try to determine the use model of that device and what makes sense to turn on and off. For instance, do I make use of memories with low-power modes when I don’t know how often they will be accessed? You need to have that understanding. There’s room for the EDA industry to have analysis tools in this space to guide the end user toward that. They should have the end application and end user in mind.
Low: In the mobile space, our software knows when a device is active and what’s being used, and it can power down the unneeded logic. You can write software to enable the system to stay awake, shut down after a certain period of time, or go into sleep mode when you want.

LPE: Are there issues around whether some of these devices can actually be manufactured?
Brotman: We’re not seeing those. We do have to define how devices are going to be used, and in the tool flow we need to predict when to power them down and power them up. When people are doing designs and implementing certain functions, we want to make sure they work.

LPE: Will we see more restrictive design rules to ensure that?
Brotman: There certainly are more design rules as you go down in process geometry. A few of them may make it into interpath parasitics. We’re definitely going to see those, but I don’t think the restrictive design rules will directly impact the things we do to control power.
Castagnetti: It’s not necessarily power-aware restrictive design rules.
Low: On the design side we need to pay a little more attention to the overall power delivery network. As we head down to advanced technology nodes, performance degrades significantly as we lower operating voltage. We have to look at the package-level power network extraction along with those in silicon to make sure we’re not overly designing our chips.

LPE: As we get down into advanced nodes there’s a lot more third-party IP and software. Is all of this stuff power-aware? And if it isn’t, how to we get it to be more power-aware?
Castagnetti: When you start mixing and matching parts, you have to start thinking about whether they are all in line with your power-management. That’s being power-aware from an overall system point of view. And sometimes the IP doesn’t lend itself to aggressively dropping the voltage. Memories might stop working, or they might stop working reliably.

LPE: But if you have a piece of software and it’s being used part of the time, that software should be able to understand it may not need to power up quickly for a certain application or it needs to power up very quickly. Does that happen now?
Castagnetti: It does in some circumstances. There is energy-efficient Ethernet. You have a plug in your laptop that you probably don’t use very often because you’re connected wirelessly. The energy-efficient Ethernet standard has implemented handshake signals so you can bring that PHY back up when you plug in a cable and start moving traffic. The industry is starting to see value in those kinds of things.
Low: We have power-based switching where the software enables a port only when it’s being used. That helps to conserve energy.

By Ann Steffora Mutschler
Optimizing design methodologies for effective power utilization sometimes meaning throwing out old ideas and approaches and starting fresh. This is exactly what wireless chip giant Broadcom did in its quest to manage power in its chips. Low-Power Engineering spoke with Michael Hurlston, vice president of the mobile wireless group at Broadcom, to discuss current and future power challenges.

LPE: What are some of the business challenges of developing new low-power designs?
Hurlston: Wireless LAN chips originally were designed for applications like notebook computers, home routers and home gateways. In those particular applications, power was not so much a concern—maybe in notebooks a little bit—but I would say that the majority of questions we were getting from our customers had nothing to do with power consumption. Then in 2007 we got the crazy idea that maybe we could put Wi-Fi technology into ultra-portable applications like cell phones, portable games, iPods—things that were really battery-sensitive. As a result, obviously a focus from our customers was going to be on power. We had to at that time change our whole design philosophy to really focus on power. We ripped out our entire design methodology at that time and re-did it with a central theme of how do we get this power consumption out. There are a number of different aspects to power consumption. For a wireless chip there’s power while you are just sitting there in an idle state. There’s power when you’re transmitting or receiving—when you are actually active. And then there’s power that’s somewhere in the middle where you are kind of operating but you are really not. We had to optimize all three kinds of power consumption and rip out our entire design flow to refocus on power. That became a big challenge for us. In a wireless technology it’s all about balancing those demands: idle/leakage demand, active demands and then the quasi-on state, which we call sleep mode.

LPE: Specifically what did you change about your design flow?
Hurlston: A couple of key things changed that were very significant. In the old topology we had basically one power plane, which means that everything was operating off of sort of a universal power supply. One of the key architectural advancements we made was to do power islands and focus on things that were going to be ‘on’ at the same time by virtue of their operation. So rather than having one supply that is essentially running the whole chip we now have dozens. And each of the different power supplies is feeding a different part of the integrated circuit, and that power supply can then be turned on or off depending on whether that particular portion of the circuit is going to be needed for whatever operation is at hand. That was one thing. The second thing was to carefully architect the design to gate clocks going to areas that were non-essential for that particular operation. So rather than having the clocks indiscriminately fan out on the chip and then be running and toggling all the time we shut off clocks going to one portion of the chip or another. And the third advancement most specific to wireless LAN technology was bringing power amplifiers onto the chip. Any wireless technology needs some kind of power amplifier. Before that we were funneling our signaling off chip to an external power amplifier that we had very little control over. By bringing the power amplifier on chip we were designing in CMOS technology, which is a lower power technology than the BiCMOS or silicon germanium that was used for our external power amplifiers. We also were able to bring a tighter control loop between the power amplifier and the rest of the circuit, which allowed us to do some intelligent monitoring of the power amplifier and increase or decrease its output power. Obviously as you’re increasing the output power you’re increasing the power draw. We were able to create a feedback loop. Bringing those power amplifiers on chip was a very big benefit for us. We were the first company to be able to do that, and now it’s fairly pervasive in Wi-Fi technology.

LPE: Which foundries do you work with?
Hurlston: We have designs that are portable among four partners that we talk publicly about: SMIC, TSMC, Global Foundries and UMC. We feel like we are relatively unique where we can do one tapeout that is portable among those foundry partners and, depending on loading conditions in the fab, the pricing in a particular fab and a number of different factors we’ll ultimately steer a chip tapeout to one of those four. In certain cases, we’ll multi-source it where we will run the same device at two or more of those foundries.

LPE: What process geometry are your products manufactured with today?
Hurlston: Most of our products are at 65nm. We’ve announced as a company that we’re aggressively embarking on 40nm and that’s been a companywide shift toward 40nm. We are still shipping some of our older products in 130nm.

LPE: Do you ever run into issues with a single design between foundries?
Hurlston: Very, very rarely. It’s probably not fair of me to say, ‘none.’ You have to remember we are the largest tenant at three of those four foundries and among the top three at the fourth. So we definitely have the ability to get these guys to do some of the work for us. We have to do some of the work ourselves and try to come up with a common set of libraries and a common set of models that work across all of the foundries, but they are equally motivated to work with us. The goal is that our customers can have a board that would accept silicon from any one of those foundry sources.

LPE: When embarking on a new design, how much IP is being re-used?
Hurlston: Broadcom is interesting in that regard. We have a multi-layer model where first, we have centralized engineering—a central engineering team—and that central engineering team actually does things like phase-lock loops, analog-to-digital converters and power supply types of circuits. There are a whole host of things that they do and then farm out to all of the different chips that get done within Broadcom. All of the different businesses within Broadcom are drawing from that central engineering team and that gives us a tremendous amount of re-use. Even a wireless LAN block that my team is responsible for, we make it so it is portable among other chips so in the event that another business unit wanted to incorporate the wireless LAN function in a larger chip, they can very easily take our wireless LAN block and marry it to a larger system chip that they might be doing. We recently announced a chip like that where we took a DSL engine and it had a wireless LAN block inside. Our whole company is built up on IP re-use.

LPE: Looking ahead, what are the biggest technical challenges going to be in terms of developing for low power?
Hurlston: Obviously we are getting to a point where there are tradeoffs between lower and lower process geometry and leakage. I think the biggest thing that we get into now is standby power, which is somewhat inversely proportional to process geometry. Active power is directly proportional to process geometry, standby power is somewhat inversely proportional. In other words, as we go down in process node the leakage current goes up without a lot of extra precautions being taken. I would say that is the singular biggest challenge is how to solve this leakage problem.

By Ed Sperling
The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power.

Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party IP is actually used, the interaction of multiple states, and even how software utilizes a processor.

Consider, for example, a virtualization layer that is added into a consumer device—an approach now under widespread consideration among device manufacturers because not all of the functions can take advantage of multiple cores. At the architectural level this makes perfect sense because virtualization simultaneously maximizes performance and utilization, which is a winning formula for efficiency. The problem is that using more cores also uses more energy, and the distribution of average use may vary greatly depending on applications or the interaction of applications. Running multiple games, for example, could drain a battery in a fraction of the time it would normally last for a voice call or playing music. And multitasking can greatly accelerate battery drain.

That’s only part of the issue, though. Higher utilization generates more heat in the form of dynamic and static leakage current. The more functions in use, the greater the dynamic current (or switching current). That can affect everything from signal integrity to the ability of memory to function properly to the overall lifespan of a device. And it can make modeling extremely difficult.

“This is a function of the operating system, or whatever software layer you’re using,” said Rob Aitken, an ARM fellow. “You determine the wake-up time and if it’s supposed to shut down different cores. But you can’t power it up right away because the IR drop would be too large, so you have to power up slowly. That means you have to model a speed limit on how quickly it wakes up.”

The challenges grow as more voltages are added for different CPUs. “If you’re operation a CPU at one voltage and the next at a different voltage you get an IR drop across the buses,” said Aitken.

New tools
Most of the large chipmakers have developed their own power models, which are specific to their particular designs. This isn’t something many chipmakers see as a core competency, however, which is why a number of EDA companies have put stakes into this market.

One of the most ambitious efforts comes from Apache Design Solutions, which has created a chip power-modeling tool. It’s an important start, but the accuracy depends on a lot of other factors beyond Apache’s control. That explains why Apache is working with the GSA to create some standards in the IP world.

Startup Parallel Engines is providing details about the available information on power, as well, for about 12,000 pieces of IP. But the accuracy of that information varies, in part, depending on how it is used.

“The power model of a chip needs to include accurate characterization of the multiple IPs that are included in the design,” said Dian Yang, Apache’s general manager. “But if those vendors supplying the IP do not give enough details about its power parameters and behavior, the resulting model will not be very accurate. Also, an accurate model needs to know things like the impedance of the die. But a simple power number based on an average estimation does not tell you that. You need a model that is based on transient analysis to address the dynamic behavior and the true impedance of the die.”

All three of the largest EDA vendors have worked to build power intent models, which help greatly on the functional verification side. Both Synopsys and Mentor Graphics back the Unified Power Format, while Cadence backs the Common Power Format. There has been work to bridge those two specifications by major standards organizations such as Si2 and Accellera. But no matter how much the EDA vendors and standards organizations insist that those differences are easy to bridge, that’s not the experience of chip companies.

“I have major issues with these standards,” said Sunil Malkani, director of IC design engineering for the GPS group at Broadcom. “The standards for power intent don’t work together, and sometimes the previous versions of a those standards don’t work with the current standard.”

He’s not alone in that viewpoint. John Busco, senior manager for design implementation at Nvidia, said the very existence of competing standards defeats the purpose of having them in the first place.

“I’m a little more forgiving when the standards don’t do everything you want them to do,” he said. “My pet peeve is dueling standards like CPF and UPF.”

While EDA vendors publicly don’t like to challenge their customers or potential customers, they say privately that more often it’s the fault of the IP and the way it’s being used than the power intent models themselves. “The user can capture the intended behavior of the design already, and if they add a few more lines of code involving the IP they can make sure the power intent is captured, too,” said one EDA insider.

Mixed models
The power intent specifications are particularly important in the verification stage, which remains the most time-consuming part of the design process. Those design intent specs are integrated with the power models, allowing engineers to map the power limits of the chip and the safe parameters for operation. But in the IP world, and even when it comes to reusing blocks and subsystems, there are not always power models available. At that point, the best that can be hoped for is that the existing models are power-aware.

“The biggest problem our customers are impacted by is legacy models,” said Prapanna Tiwari, CAE manager at Synopsys. “They were created when low power was not a concern, and the models don’t comprehend voltage. The second problem is that even if they want to create a power-aware model, they can’t do the entire power network in Verilog and hook it up to every power model that is being created.”

Limiting choices
Another major problem is the sheer number of choices that are available to designers and architects of these chips. The number of variables increases with each new process node, as well as the proximity effects of other components in an SoC, packaging, what software is being used and how it is being used, multiple cores, multiple states, multiple voltages and ultimately 3D stacking. Add to that multiple IP options and the effects on power models become overwhelming.

“We may well see standards for limits on the number of power models that are available,” said ARM’s Aitken. “If you look at the 1801 standard (UPF 2.0), there are certain things that are legal in it and certain things that aren’t. This could well be the direction.”

That doesn’t mean having a menu of choices will make SoC development any easier, but at least it would limit the number of variables that engineers have to wrestle every time they decide to integrate third-party IP or re-use their own IP. Still, there are a lot of changes to be made before even this step happens. As with all SoC engineering, nothing is guaranteed and not everything is predictable.

By Pallab Chatterjee
In late September, the IEEE ratified the 802.3az Energy Efficient Ethernet (EEE) specification. The standard, and associated test certification specification, was supported by co-development of over 20 commercial products from multiple vendors, of which 13 were release to market simultaneous with the ratification.

Wael Diab, from the office of the CTO at Broadcom, and vice-vhair of the 802.3 working group, indicated that the importance of the specification is high, which why there was a simultaneous release. The adoption of the product is in progress now.

For lower data rates (10Mb and below) there is a power-down mode for the Ethernet connection that is based on a “wake on LAN” methodology. For 100Mb, 1000Mb (1G), and 10Gb data rates, the original specification has the port, both transmit and receive, on at all times. As a result, there is a lot of wasted power dissipation in a product such as a multi-port switch.

In most cases, on a 24/7 schedule, any given port has significant periods of being idle. However, there is only an “on” state so the power usage does not change. The EEE specification identifies a tweak that can be made tot the PHY so that there is both a low-power idle state and deep low-power sleep state added. The worst-case “wake” time from these states is 5uS, so the overall switch throughput is not significantly upset. Advanced features of the spec include a “blank” mode where both the transmit and receive ends of the port connection are powered down, not just the receive side. The specification was made possible, as the packet based data traffic going through these high bandwidth connection is typically less than 10% of the time, with 90% idle.

Broadcom has created a series of products that implement the specification and the EEE parts are available as full stand alone controllers, and as IP in the form of a 10G PHY. All the products meet or exceed the 802.3az specification (http://standards.ieee.org/announcements/2010/8023az.html) . Their designs use the idle state to turn off the additional control logic subsystem for the port as well as the associated L2 Cache. To enable customers to get to market quickly, they made the PHY external from the MAC and created a signal control path between them. This allows for the use of the new PHY is an existing system, as it does not require the custom part containing the MAC from the original 802.3 specification to be respun. Developers can simply drop in the new EEE PHY part. The parts are designed to support 100M, 1000M and 10G applications.

The specification is smart in that it is application-independent. If the data transfers are standard short blocks—extended length video style blocks or new Advanced Format (AF) larger block size data—the power-save modes are the same. The PHY does not care about the application or the data size. The transmitter side of the port pairs controls whether the connections are in active, idle or sleep mode.

Based on using the PHY or new ICs in systems applications, the control logic has “knobs” that are able to support tweaking of the idle state. The control hardware supports this optimization and the resulting shifts in the power waveforms, in real time, so it can be tuned to make sure there is no change of state in the power-up and down sequence. The idle state control is set from a policy engine rather than a straight sense configuration.

In addition to Broadcom, Realtek, Intel and others are producing the product, and the end systems from providers like Netgear will be available starting this month.

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”

Imec and Holst Centre unveiled an analog-signal processor ASIC that reduces the overall power consumption of a heart activity signal monitor by five times. Key to the process is intelligent processing from an adaptive sampling scheme—slashing the amount of data that needs to be processed by the DSP and then transmitted by the radio.

This is one of the hidden benefits of Synopsys’ announced acquisitions of CoWare and VaST. The more you can control the software, the more you can control the overall efficiency of the entire system—particularly when it comes to a multicore system. The key is adding intelligence into the processing up front, which is where software prototyping comes into play. The amount of data in circuit design is exploding, but not all of it has to be processed at every step.

Imec wasn’t the only one looking at low-power medical devices. MIT is developing a series of self-powered sensors that harvest electricity from temperature differences in the body. Who needs batteries?

Broadcom introduced a new low-power chip that combines Bluetooth with FM and a GPS, as well as all the normal stuff you’d find in a smart phone. Most of the services in smart phones have been software-based. This should change the market—and potentially the amount of power necessary to make it work.

On the utilities side, Springsoft introduced a power-aware debug solution for verifying low-power chips that supports both UPF and CPF. Spanning rival formats is always an opportunity, particularly when companies use tools from more than one EDA vendor.

By Pallab Chatterjee
Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology.

There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions from Nvidia, Samsung SLSI, Imagination Technology, NetlogicMicro, Broadcom, and Qualcomm. To address the usability specs required by e-readers, mobile Internet devices and other mobile information products, a new compute architecture was needed that did not just rely on “function disabling” as a power reduction technique. All of these companies introduced designs that are focused on multicore architectures, where there is complete functionality available at all times even though the process has been optimized for low power.

This low power optimization has to do with custom library design creation, modification of internal clocking schemes, datapath and buffer optimization, memory segmentation and placement, and most importantly dynamic control of the design’s power use and speed based on the data content of the information being processed on a per-packet basis. This re-architecture of products was the key enhancement with the new dual Cortex Nvidia Tegra, which is targeted to e-readers and tablet PCs, as well as the high-performance Alchemy multicore and multithreaded processors for automotive and navigation applications, and the many new video and communications appliances from Broadcom and Qualcomm.

The basis for most of these systems are ARM processors cores (A8 or A9 primarily) or MIPS cores. This shift has allowed both a performance increase in the end systems as well as a nearly doubling of the operating battery life.

The second prevalent low-power methodology is the segmentation of design to a CPU and a GPU rather than a single compute engine. While the initial impression is, this takes more power, the GPU is actually more power-efficient on graphics and some video data than the CPU, and on general use functions, the CPU is more power-efficient than the GPU. For most of the smart phones and media processing chips, this approach has replaced bigger single-processor cores with clock-gating and multi-voltage device process solutions.

These architectural changes were implemented to address both the data dependence of the power use and the yield-process variability of sub-wavelength manufacturing. As most of the applications have a very thin and small form factor, they are bound by a fixed or diminishing power envelope. To address the longer term of operation the components can lower the operating voltage, but this does not take into account the associated reduction in performance in the power envelope that is associated with it. In order to address this aspect of design, the mobile handset and mobile computing requirements have driven to the smallest geometry process flows available.

The utilization of these processes (45nm and 40nm, currently) requires restricted design rules, restricted topologies and limited device size diversity to yield well. These designs are optimized with new RTL and physical libraries, new floor plans, and power routing to highlight the data path symmetry that is required by the data sets being processed. Examples of this are new 3dmedia processor in 40nm by Samsung for mobile phones that utilize the IMG Tech 3D video and graphics engine and a high-performance ultra low power ARM CPU.

The distributed multicore approach also has been utilized in high performance for lower power products. AMD/ATI introduced the 5970 Radeon graphics card at the Consumer Electronics Show. The card has two GPUs and is a Direct X11 product with more than 4.6TFlops of peak performance. The restructuring of the device/cell library, its reliance on proven 40nm bulk CMOS processing and the use of GDDR5 memory allows the product to operate with a peak power of about 300 watts but only requires 51 watts for nominal operation. The design was optimized for power and a data control flow to support the 3200 parallel stream processors and the 160 texture units. Dynamic power is managed based on how many streams and texture units are needed at any time based on the contents of the data that being processed on any given cycle.

Most of these new systems are targeting use of Samsung’s low-power DDR3 memory, which operates at 1.3v vs. 1.5 volts and offers higher densities than DDR2. These higher-density, low power solutions can provide in excess of 35% overall power footprint reduction for the design, if used with 32nm low-power flash memories in SSD applications rather than rotating media.

The takeaway from CES this year is that architectural engineering and new firmware control methods are now seen as essential to address the functional requirements of the new mobile communication and processing platforms. This is an intelligent shift from recent years, when only feature size reduction and blind tool-based selection of power gating and power routing were in vogue.