By Ed Sperling
It was supposed to be the first IPO since Magma went public in 2001. Instead, Apache was bought by Ansys in a deal that closed earlier this month—at a record pace for the EDA industry of less than two months since it was announced.

So what exactly was behind the acquisition and why did Apache agree to sell? And what will become of Apache within the much larger Ansys?

Low-Power Engineering posed those questions and others to Andrew Yang, former CEO of Apache and now the president of Apache Design Inc., a wholly owned subsidiary of Ansys.

1. Why did Apache opt to be acquired rather than continuing with its IPO?
According to Yang, the answer was “a convergence of vision.” “Their vision has gone initially from mechanical simulation to fluid dynamics to electronics. Our vision started as chip-centric with a focus on power to package and board. So they’ve gone from system-level to electronic to IC and we’ve gone from IC to system level to board. Our thought was that either we remain separate and hire a lot of engineers with system-level expertise, or we joint hands to accelerate the same vision.”

2. What happens to Apache now that the deal has closed?
Apache will be a wholly owned subsidiary, but it also will be a separate division. “The reason we agreed to a deal with Ansys—and the whole discussion from our first meeting only took seven weeks—was that they have a history of acquiring companies of strength, not remodeling them. Our core focus will be leveraging each other’s resources and leveraging their channel for underserved markets,” Yang said. But he stressed that Apache will remain focused on its customers and existing tools, as well as exploring synergies.

3. What will happen to Apache’s focus on 3D stacking?
Ansys also has focused on stacked die from the thermal side. Apache’s focus has been from the power and power modeling side. “This will accelerate an integrated solution,” Yang said.

4. What about overlap and synergies?
Overlap is minimal, according to Yang. Synergies are still understood and developed. The key to the combined company will be to figure out “what the customer needs and what the competition lacks.” Talks are underway to figure out how the companies’ combined strengths can be extended into new markets and approaches, but one of the keys for Apache is Ansys’ strong, well developed sales and distribution channel.

5. What are the challenges ahead?
Figuring out exactly how to work together in the future. At this point, there is no comment about future directions, additional potential acquisitions and which companies will be viewed as the top competitors.

By Pallab Chatterjee
Recently Samsung gave an update on the status and availability of its advanced 32/28nm process technology for use in foundry. The process is targeted for shipping designs to customers at the end of this year, with a road map that continues through the 22/20nm nodes and down to 15nm.

What was particularly interesting were several key innovations that have made this all possible, as well as the company’s statement that the real driver is reduced power.

The new processes, co-developed with IBM, follow the large commercial success of the Intel achievement of using a Hafnium “Hi-K” metal gate process. Although this terminology has been around for a few years and is the dominant technology in the microprocessor marketplace, there has been some “uncertainty” in the design community about what it actually buys the designer. The Hi-K gate technology is a process development that directly addresses the leakage current problem that arose in CMOS technology at the 90nm node and has persisted through the 45nm node. The scaling on process technology using Moore’s law is a three-axis scaling—x and y for the length and width of the transistor used to make the basic devices, and also z or the vertical dimension. Z is the thickness of the gate dielectric, which controls the intrinsic speed and performance of the device by setting the difference between “on” and “off.”

Since the late 1960′s the scaling of all three axes has taken place concurrently—until the 90nm node, that is. At 90nm the complexities of lithographic processing, planarization, materials used for interconnect, isolation between devices and reduction in application power supply were moved up from third- to fourth-order issues to become the dominant drivers. This made the leakage current and capacitance issues with the z-direction scaling the secondary challenge. This focus on the other processing issues caused the gate scaling to stall, and not continue proportionately with the x and y scaling, resulting in leakage, multi-power islands, high electric fields, and high-stress devices and designs that have dominated the past few years.

The lithography solution is staying optical with multiple patterning solutions through the 22/20nm node. The planarization, interconnect and device stacking for “multi-die” technologies are progressing to address the function vs. density vs. space requirements going forward, which allowed time to develop the new materials needed to make the gate dielectric (replacement of standard SiO2 with an Hf based material) and re-start the z-dimension scaling. At the 32/28nm node, the reduced leakage and increased device performance (difference between “on” and “off” states) brings a new level of design capability.

Results using the process in foundry-type circuits (embedded processors with memory, custom logic, and standard commercial interface connectivity) are showing as much as a 35% power reduction for the same operation specification as existing circuits. This power reduction comes from both the ability to drop the operating supply voltage for the same performance specification and from an overall reduction in leakage/standby state power for “idle” modes in a design.

The new process technology, now starting to become available from multiple suppliers, does bring an opportunity to create a new generation of mobile appliances. There is a significant challenge to the design community to address these benefits as a mainstream technology solution. The cost of entry into the design game at these nodes is very high. A typical 32/28nm SoC is probably going to contain more than 500 million devices, including embedded memory, and will likely have a very high pin count. This will require a big design team to architect, design, assemble, and test, not counting the very aggressive 20-plus man-years of IC design (5M devices/man year for the flow X 20 people = 100M devices + 400M in third party embedded memory), and application software development.

These design costs are on top of the fab costs, which are targeted at more than $4M for masks, plus the wafer fab, package and test. And it is looking like the big boys at the $30 million-minimum per design are the only ones who will be left at the table for real “low power” process game.

By Ed Sperling

You have to look pretty hard in the EDA Consortium’s most recent numbers to find good news, and even that’s relative.

The first quarter everywhere was painful. EDA did better than most industries, and it certainly did better than the semiconductor industry as a whole, but that’s still in relative terms. For example, the number of jobs decreased 2.8% in Q1 of 2009 compared with the same quarter in 2008. But add that up with the drop in the overall EDA market—down 10.7% in Q1 2009 vs. Q1 of 2008 and you begin to see a deeper drop. What jobs remained often came with a price, namely forced time off—a number of companies are shutting down for a week or more this summer—and more work to do while employees are on the job.

“In general, designers have a skill that’s valuable,” said EDAC Chairman Wally Rhines. “The total number of designers is not down because of the recession, and they’re usually the ones that are laid off because design activity doesn’t drop that much. You still need good products, and you especially need them coming out of the recession.”

Still, there has been some displacement of jobs, which seems to have contributed to the rise of services revenues. Normally in downturns service revenue declines because companies take work inside rather than outsourcing. That wasn’t the case this time. Services rose 20.8% to $105.7 million.

Rhines noted that while EDA has improved overall, it is still in “uncharted territory.” In past downturns, EDA still managed to stay in positive territory. That isn’t the case this time.

“The number of designers will increase in the long term,” he said. “In the short term, there is a negative hit.”

By sector, EDAC reported the following for Q1 2009 vs. 2008:

• CAE: $427.9 million in revenue, down 18.8%
• IC Physical Design and Verification: $119.9 million, down 7.1%
• Intellectual property: $236.3 million, down 12.8%

By region, the Americas were down 11.6%, EMEA was down 15.9%, Japan was down 17.7% and Asia/Pacific was up 11.5%.

For many chip designers, the real tradeoff is in doing more with the same amount of power, not doing more with less.

During the last quarter (Q1 2009), more chip architects performed design investigations in the 0.25 watt to 1watt power range, followed closely by the 1.5w to 4w range (see Figure 1). Designs using less than 0.11watts continued to decline.

Figure 1: Total design investigations – a prelude to chip starts – versus total chip power shows a marked increase in lower power devices.

This may seem counterintuitive, especially at a time when low-power devices are the rage among consumers. But digging a bit deeper into the data (1) reveals other clues. For example, the most popular market segments targeted for these investigation are in the areas of communication and consumer devices. Also, while a significant percent of these investigations appear to be at the higher process nodes, namely 90nm and 130nm, the first month of the second quarter (2Q09) experienced a sharp increase in design exploration at 65nm.

Let’s add one more data point into this mix before we draw any conclusions. Most handheld wireless devices operate in the 1w to 3w range. Embedded processors tend to be in the 3w to 5w power range. That reinforces the hard data that pegs the power-range of interest at communication (wireless devices) and consumer (wireless devices and embedded) markets.

Do these trends support the much-touted growth of low-power systems? Certainly, because devices in these power ranges are doing far more in term of overall feature sets than similar devices from a mere two years ago.

Doing more with less makes good press. But doing more with the same amount of power makes good products and – many would argue – is equivalent to a decrease in overall power usage.

+++++++++++

Note: (1) * This data represents over 44,000+ unique worldwide and regional pre-silicon design investigations, aggregated from the major IDMs, design shops and IP vendors, from 1996 through the present.

By Ed Sperling

The semiconductor industry is getting a better reception from the Obama administration than it has in years from previous administrations, which all but ignored warnings about global warming and a destabilizing dependence on foreign oil.

In fact, the new mantra of saving power while improving the quality of life could drive one of the biggest boons in the industry’s 60-year history. Much of that is included in a new report from the American Council for an Energy Efficient Economy, a non-profit group comprised of some of the top companies in the chip industry. The group issued a new report entitled, “Semiconductors are now the driving force behind U.S. energy efficiency gains.” It said the U.S. economy could expand 70% through 2030 and still consume 11% less energy.

That estimate may be conservative, however, particularly once things like energy harvesting and broader power-saving features begin hitting the market.

“We certainly can do things differently to save energy,” said John Perzow, marketing director for the power management group at Analog Devices. “In a wind farm, you can do a lot of monitoring to avoid human intervention with vibration sensors. That lowers the cost. It also means that you don’t have to drive out there and check them, and then drive back.”

He said the same is true with lighter televisions. The new ones use less power, but because they weigh less they also take less energy to ship.

But the biggest gains may come from utilizing some of the same power-saving techniques developed for portable, battery-driven devices inside those with a plug. If a server in a data center is only 15% utilized, for example, parts of it—particularly cores within the processor—can be turned off completely when they’re not being used.

“Those kinds of techniques are definitely getting shared between portable and non-portable systems,” Perzow said. “We talk to our colleagues in the hall.”

Everyone seems to be on a low-power kick, from the ASIC/ASSP world to the growing market of low-power embedded processors and SoCs. But what do the actual numbers tell us about the future trends for such low-power designs?

One way to answer that question is to look at the result of architectural tradeoff studies currently being performed by chip designers. (See chart below) A causal glance at these results for total chip power investigations, which are precursors to actual design starts, suggests that interest in the lowest power designs is trending off.

That’s what seems to be happening for designs with total chip power budgets below 0.11 watts. But a closer look reveals that ASIC designers are performing architectural explorations for future chip projects in the 0.25-to-1 watt and 1.5-to-4 watt power ranges. This makes sense, as the chip industry is just on the cusp of a new wave of low-power embedded processors and SoCs designs and applications whose current target power consumption is at about 5 watts.

The numbers are significant as they represent the architectural tradeoff from almost 1,000 unique design investigations. Still, it is difficult to separate all the market influences that affect this aggregated data. A future report will attempt to filter out these influences by cross referencing other data points, such as targeted end-market applications and more technically oriented data (i.e., gate counts, metal layers, etc.)

For now, though, the data supports what the market place is saying—that low-power designs below 5 watts are growing.

(1) Does not include FPGA design starts. This data is part of the annual “Chip Design Trends Report.”

By Ed Sperling
If the new releases of Synopsys’ Ly nx  environment and Mentor Graphics’s Calibre are any indication, managers should probably take note. The tool automatically gathers information for power, timing and area—everything you’d expect from a tool of this sort—but it also provides what it calls a management cockpit.

Synopsys’ management cockpit and Mentor’s dashboard allow upper management to see what’s happening throughout the design process and to track progress. And while that may be useful from an efficiency perspective, both products also move the blame up a few notches. If something goes wrong, the top managers can no longer claim ignorance. They have all the information they need for a detailed understanding of a design’s progress.

It also means that upper management will require at least some expertise to use these kinds of tools effectively. A business background is great for understanding operating expenses and sales, but a technical background will be essential for making sure the job gets done. And in public companies, it will be much tougher to hide behind the paneled walls of the C-suite and claim incompetence from below.

“Ly nx provides visibility across a design flow with its management cockpit, roughly the way economic data has been added inside many corporations at the enterprise level,” said Ganesh Ramamoorthy, an analyst at Gartner. “There will be more scrutiny from team manager all the way up to the CEO/CFO with this kind of data. Given the current economic conditions it is only natural that engineering teams will come under more scrutiny in terms of their productivity levels. So whether they like it or not, one way or the other, management will try and push tool such as these to get a better grip on design tape outs and resource utilization.”

Likewise, Calibre’s focus on design for manufacturing can zero in on which engineers are getting the best yield from the foundries. “You can analyze different design groups and determine their yield,” said Jeff Wilson, Calibre DFM marketing manager. But while that tool may be good for managers’ ability to get a good look at what’s going on inside an engineering group, it will be tougher to push the blame off to someone else. 

Ramamoorthy believes that, like most advances in existing tools, these changes will make engineers more effective. But whether they actually improve innovation now that someone is watching over them is uncharted water.

“Tools such as these basically make engineers life easier,” Ramamoorthy said. “But innovation is not something that can happen just because these tools are now available. Engineers were innovative when these tools where not there within the given constraints. With these tools now at their disposal, ultimately, they will have more time to innovate. But then who ultimately innovates is the million-dollar question.”

At the very least, it will increase visibility in both directions.