By Ann Steffora Mutschler

Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models.

Thanks to Moore’s Law, the number of transistors that can fit on a chip has grown to the billions, which obviously can’t be counted with the naked eye. But they also no longer scale with SPICE. Abstraction has been the way out by providing a higher-level view on the design.

“Clearly, even when I’m at gate level, I know I’m not getting the same accuracy that I would be getting at SPICE level, but if my models are good enough and it is close enough, I’m willing to take that slight hit to be able to do bigger designs,” noted Barry Pangrle, a solutions architect for low-power design at Mentor Graphics. “That’s the progression that we’ve gone from—transistors to gates. Then people were doing schematic capture and everything was gate-level models. Then we went to RTL and we started moving to RTL models. Now we are moving on into system and bigger components and functional blocks. At each level, we’re giving up some measure of accuracy—it’s just not going to be as detailed. It’s not going to be as fine-grained and the hope is though that we have enough information that we can make the decisions at that level of abstraction.”

The abstraction levels in use today were developed over a long period of time. They are well-defined because a huge amount of work was done in terms of both modeling, to make sure we can move between levels, and to ensure there is the appropriate level of detail to accomplish what needs to happen in that level.

“Today, we’ve tuned it and created enough modeling around it so we can get the information that we need out,” said Cary Chin, director of technical marketing for low-power solutions at Synopsys. “But I would say that the model isn’t general enough if we thought of some new use of these connections and voltages and expected it to give us the data that we wanted. Whereas if you did that all in SPICE, it likely would [provide the right data] because that’s one indication of the maturity of the model—whether you can use it for things that weren’t anticipated originally when you built the model.”

At the RTL level engineers synthesize down to a gate-level netlist so that they can bring in their gate level models, Pangrle said, with the hope that based on the information they get from those models, they can create something that’s going to be representative of what they need at the RTL level. “Now we’re looking at going one level beyond that and saying, ‘Okay, at the next level of abstraction what kind of information can we capture here?’ The tricky part is making sure that you still have the level of accuracy that you need to be able to make the types of design decisions that you’re going to rely on that information.”

But these levels of abstraction are not all fun and games. For engineering teams doing low-power designs, there are many challenges moving between these different design abstraction views, the biggest one between the RTL to gate because these two abstraction levels have too many big differences, explained Qi Wang, technical marketing group director for low power and mixed signal at Cadence. “On top of that, there is a lot of handshake of tools between those two levels.”

For example, he said an important aspect of low-power design is to gather activities. RTL simulation is run to collect activity, so all of the signal activity is annotated along with all the signal names. The engineer hopes to re-use that activity at the gate level, but the problem is the name seen at the RTL may not be the name seen at the gate level because the synthesis tool renames the files.

Power formats

In addition to this renaming, a lot of optimization can happen between the RTL and the gate level, which means that some signal may simply optimize out. Another possibility is that the logic may not optimize out but the representation can be changed, Wang said. “On the activity side, this is a flow challenge. The activity file you get for the RTL you hope you can re-use for the gate level, but many times you will find it is very difficult.”

Another kind of difficulty involved is with the power format, no matter what standard is, Wang noted. “The whole idea is that you describe your power intent in another file… If you write a power format file for RTL, which means it will be used for the RTL so all the names you refer to would be the RTL names. Now when you get to the gate level you hope you can use the same RTL level power intent because I want to keep my golden power intent through the design and verification flow.” But this will have the same problem as in the activity file.

To address this formal verification techniques can be used to indicate which RTL register names map to the corresponding flip flop on the netlist with a name-mapping file.

Then on the power intent side, he suggested the easiest way to deal with the renaming issue to have the synthesis tool write out a new power intent file, which automatically will reflect the name changes and the hierarchy ungrouping. When it comes to enabling the flow, however, the power intent written out by the synthesis must be equivalent to the original power intent, which is where power-aware equivalence checking tools are utilized to prove that the new power intent and the old power intent are equivalent.

Twenty years of hard labor

Traditionally, traversing levels of abstraction has been relatively straightforward—it’s just a lot of work. “If you look at the library modeling process that has evolved to go from kind of transistor level to gate level, things are very well defined today,” Chin said. “Libraries are super solid and vendors know how to characterize things even as the technology changes. That’s an example of a level of abstraction that’s pretty mature because over the last three, four or five generations of technology, we haven’t had to make major changes. There have been many, many little extensions and timing models and functionality and things like that but basically since we haven’t changed the fundamental design flow, the models and libraries have stayed pretty much the same, which is great.”

There have been similar advances in synthesis. “If you look at this between RTL and gate level, synthesis has changed a lot over that time, as well, but in general if you couple synthesis with verification tools and formal verification tools, things have actually grown nicely so that we still have very dependable flows that most people are still pretty happy with. You can push the button and trust what comes out at the other end. And as you recall, it took us 20 years to develop that level of trust,” he concluded.

Once the engineering community moves en masse to the system level, that 20 years could easily be duplicated.

By Ann Steffora Mutschler
Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events.

“These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Mentor Graphics. “We’ve had to wrestle with them for some time. Fifteen years ago when I was doing microprocessor design at 0.35-micron at DEC (Digital Equipment Corp.) we had an electrical migration budget and the reason for that requirement was that DEC—which put chips into VAXes and things that would do your financial statements—essentially had budgets that said our chips will last 10 years and expected 1%t of them to have failures due to EM.”

That type of requirement was never applied to the mobile market because devices aren’t expected to last that long, and fabless companies historically have not been particularly concerned about EM. Automotive companies have been a different story because cars are expected to last for a decade or more. That’s all changing as designs scale and chips get smaller and smaller, however.

“There was an inflection point some time ago when we switched from aluminum to copper—at about the 65nm/40nm process node,” Robertson said. “The characteristics of copper made them much more robust against electromigration, so we bought ourselves a couple of generations of time. At 28nm and 20nm, the wires are now thin enough that regardless of the chip, they are running at very high frequencies so electromigration is a concern for nearly any type of designer, not just for those who expect their chips to last 10-plus years. It’s a concern for those who expect them to last one to even five years. It really gets down to the scaling of the geometries and why it’s such a concern.

ESD and EM require analysis of power/ground nets at the full-chip level. Source: Mentor Graphics

Smaller nodes magnify electrical effects
When the design moves to advanced nodes, reliability becomes one of most important challenges. Reliable chip operation increasingly is affected by environmental conditions, such as electrostatic discharge (ESD), electromagnetic interference (EMI), and soft error rate from radiation (SER), and these things could even damage devices on a chip, according to Tianhao Zhang, senior product marketing manager at Cadence. “In the meantime, the multiple power domain application requires the appropriate signal protection to make a device work, which is more susceptible to ESD.”

Arvind Shanmugavel, director of applications engineering at Apache Design said in terms of electromigration, the single biggest driving factor for making things more complicated is process migration. “What we have noticed over time is the transistor drive strength has almost remained constant over the different technology nodes, meaning they can push out the same amount of current from 65 to 40 to 28 and even going down to 20nm, but the wire geometries have decreased over these generations. The wires have become thinner and they have decreased in overall geometry sizes and the EM limits for these wires have also decreased over these different technology nodes. The EM limit is essentially how much current can be pushed to a unit area of metal for a particular technology node. This depends on the metal properties and so on. We have noticed that those limits have also decreased with technology migration.”

ESD on the other hand, is an event-based failure. Technology migration as well as design styles have affected ESD design. In terms of technology migration, ESD needs to be designed within the operating window of device breakdown and normal operation. “As we move from one technology node to another, our device breakdown characteristics have drastically decreased, meaning that the drain-to-source breakdown, the gate-to-source breakdown voltages have drastically decreased but the operating voltage of ICs has not really changed that much,” he said.

Interestingly, Mentor’s Robertson said some fabless semiconductor companies aren’t necessarily so concerned with reliability of chips over a 5- to 10-year span and equate ESD failures to yield issues/the cost of doing business. ‘It’s a hard problem so we’re willing to lose a couple of percent due to this simply because it’s difficult to verify or difficult to protect against.’ However a greater and greater portion of your circuit is going to be susceptible to ESD failures. The oxides of your transistors are so small these days that it’s not just a human with a large piece of static electricity that’s a concern, it is potentially what we would consider rudimentary voltages in the past not dissipated correctly and blowing the oxides of a delicate 28nm or 20nm oxide. A larger portion of the chip could fail due to these events and so there’s been a push for new techniques.”

New techniques fall into a couple of camps, none of which are really new. “Since the beginning, we’ve always been able to simulate. We could always run circuit simulation for electromigration or ESD. The problem, however, is as these chips get bigger, this really requires a transistor-level simulation, and transistor-level simulators cannot accommodate today’s chips because of the size of the designs–multi millions, billions of transistors. In order to do this appropriately, you need a transistor-level simulator. Even the best Fast SPICE tools are not going to accommodate today’s designs. And static timing, while people are doing full chip static timing sign-off, with these ESD, electromigration issues many times you need to go down to the device level. At 20nm, you need to have even more stringent rules that identify what’s possible or not [with EM] and I think you have to be more sophisticated with your analysis. For ESD I don’t think it changes all that much because you’re trying to find out which are the sensitive devices and what they can tolerate, and then if there are protection devices that will accommodate the charge or currents that are possible. It’s essentially a math problem.”

Cadence’s Zhang said a new industry approach called design for reliability is emerging, which consists of adding more protection to minimize or even solve the impact of ESD and EM. However the verification this protection is extremely challenging. Right now most of design houses do the verification manually by experts, which has the significant risk of missing design flaws.

Cadence, Apache, Mentor Graphics, Synopsys and others provide tools here to help designers automatically verify their designs.

Looking ahead
Solving full-chip challenges for reliability are very interesting because, “when you put more components on the same die or when you put more dies in the same package, you’re affecting the reliability behavior of that system,” Apache’s Shanmugavel said. “With IC integration, for example, we have seen a lot more IPs being integrated on the same piece of silicon and that really effects the ESD design of the full chip. Because every IP has its own power delivery network and for each PDN, we need to have ESD protection devices protecting the power, the ground and the signal nodes associated with that particular domain. With the increasing number of IPs being used today comes an increasing number of voltage domains. Similarly with the increasing number of voltage islands for low-power design comes a higher complexity of verifying ESD protection for all these domains.”

ESD has to be verified not only on every domain but must also be checked cross-domain. This means that between every power domain and any other domain on the chip, there must be some kind of an ESD protection to make sure that there is a reliable discharge path of current during an ESD event. “This is no longer possible by visible checks. ESD is one of those art forms where people have visually looked at a layout and qualified that it’s ESD ok. But that’s no longer going to be possible—it has to be translated into a rule-based check and not just an art form,” he explained.

“The ESD limits have not really changed over time — it’s the same ESD standard that we’ve been using for the last 25 years but the geometry sizes have obviously gone down quite significantly, so pushing the same amount of ESD current through the geometries and the geometry sizes going down, there is a higher propensity to metal burnout. That is a huge aspect in terms of ESD verification that has to be available in your analysis platform,” Shanmugavel concluded.

Power-aware design differs from conventional design in both well-understood, as well as, subtle ways. For a typical design today, the RTL describes the functional intent, drives the implementation process and relies on equivalence checking to assure the intent carries through to silicon. In power-aware design, the power format file – either CPF or IEEE 1801 (UPF) – is the specification for the power intent. The functional intent becomes the RTL and the power intent file. While many tools in the end-to-end flow can read the intent, how do we verify that each of these tools has interpreted the intent in the same way? Where does the equivalence checking need to take place for power- aware design?

To read more, click here.

By Ann Steffora Mutschler
The increasing amount of mixed-signal content being included in SoCs for automotive, networking and all manner of mobile devices is reinvigorating the mixed-signal industry. While this is great news for companies playing in anything related to mixed-signal technology, it also means increasing complexity for the engineering teams pulling all the pieces together.

“People have been designing mixed-signal for a long time and the composition of mixed-signal is changing drastically,” explained Mladen Nizic, engineering director at Cadence Design Systems. “Traditionally, mixed-signal was viewed as big digital with some analog in there, but now we see that mixed-signal has really expanded in complexity. So we have designs today that are about equal mixed with respect to analog and digital content. With designs that in the past were predominantly digital, engineers didn’t need to worry about analog impacts and effects. Now they have to, at least to some extent. Digital designers doing verification need to have some representation for these analog parts or mixed-signal parts or they might not completely verify their designs.”

Given that consumers are the driving force behind semiconductor demand today, there are very high performance and cost demands. In fact, cost is now viewed as a primary design variable, according to Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys.

Packaging—a significant portion of system cost—plays a deterministic role in the architecture of SoCs because the choice of package dictates a number of technological aspects of the system.

“Our customers are selling package-tested parts, so packaging becomes an important part of the cost equation. Customers would like to use the cheapest possible package that they can get away with, and the design challenge is that the cheapest package has the worst performance in terms of parasitics. You’ve got really bad parasitic inductance, parasitic capacitance, lead frames are very badly put together, and there’s a lot of leakage through the substrates. These things are typically in some kind of cheap BGA or wirebond implementation,” he explained.

To illustrate, Nandra shared a recent situation with a customer that wanted very high performance capabilities on the die but were going to put it into a really cheap package because it was going into a low-end smartphone they wanted to sell under $200. “The discussion was around how to get a very-high-speed memory to connect to the chip being developed without compromising signal integrity. In that particular package configuration that they had, there would be a limitation on speed. At a certain speed they’re going to get skew and reflections on the line, which is going to impact performance of the chip. Then the customer asked if they could save cost by compromising on the board—maybe use a two-layer board instead of a four-layer board. That’s certainly possible but, again, you have to downgrade or degrade the performance because the two-layer board doesn’t have that many degrees of freedom in terms of performance. So cost is absolutely a critical part of the equation when you’re coming into designing not only IP but also when you’re looking at it from an SoC perspective.”

He believes a lot of engineers don’t quite understand these tradeoffs. While it is certainly possible to get the performance with a very expensive technology at 28nm with all the process options, all the different masks that allow all the different voltages, a nice package and an expensive board or connector, the reality is that many SoCs must be designed and manufactured in the cheapest possible environment.

“This could be the biggest mixed-signal challenge, because every six months or so engineering teams look at ways of getting the cost down on their product. But they want the performance, too, so the ingenuity from the engineering side really needs to apply to that: ‘How can I get the most out of very little in terms of the package, the board material and such,’” Nandra continued.

Complicating mixed-signal designs is the persistent drive for lower power, said Pat Hunter, product marketing engineer responsible for developing strategies for point-of-load power solutions at Texas Instruments. “Integration and power consumption [are trends,] but the biggest trend I really see is battery life because we all know—we’re consumers—the biggest complaint we all have about our cell phones is the battery life. In TI we do a lot in the area of charging the battery, but the more important part of it is accurately gauging the capacity of the battery.”

Low-power challenges in mixed-signal come from a couple of aspects, noted Cadence’s Nizic. “One is that we brought more digital into analog. Before we didn’t worry much how much of that digital was consuming because it was really small parts. If I have instead of a few hundred or a couple thousand standard cells now I have a hundred thousand or a few hundred thousands with my analog, that’s becoming a significant part of my overall power budget. Second, I want to use this digital to better optimize power of my analog — shut it down when it’s needed — it’s all interacting — now I have to apply low-power techniques on my digital part but at the same time, that complicates my interfaces with analog. That’s another dimension when I try to verify power modes and functionally entire design.”

Like Nandra, TI’s Hunter has seen customer demand for cost reduction, as well as the accompanying struggle to make the right architectural tradeoffs.

Speaking to designing devices for longer battery life, Hunter said, “If you look at them like they are fuel gauges, the biggest architectural tradeoff is you are adding cost to your system because the microcontroller will have an analog/digital converter on board and they can do their own gauging. But it’s very inaccurate because the batteries have internal impedance, and if you don’t keep up with internal impedance you’ll think that there’s less energy in the battery than there really is. I’ve got customers that were doing laser wrinkle removers and so they had their own A-to-D gauging the battery. They were doing a cost reduction. But the biggest complaint from their end customers (the consumer) was that they could never trust the battery reading. Here’s the case where they were going to do a cost reduction but they are adding my part because they needed that extra accuracy. The challenge is trying to justify the extra cost. The way you do that is with consumers. If you’ve got two smartphones side by side—they pretty much all do the same thing nowadays—but if you’ve heard this one’s got twice the battery life you as a consumer will buy that. Nobody cares that my solution is in there. They just care what my solution does for the product.”

When it comes down to it, cost defines everything. “It’s choice of process technology, choice of the IP that you’re going to use, speeds that you’re targeting, packaging, risks you’re willing to take. In the end, if you were to devote significant resources your quality would be great, but you have to make that tradeoff now between ‘my cell phone probably is going to be on the market for six to nine months before someone is going to expect an update or a new cell phone, so do I need to now run through all the qualification standards that require five years of operation?’” Nandra said.

By Ed Sperling
The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary.

All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, Altera and Xilinx, have rolled out 2.5D prototypes. The big foundries have developed processes and interposer technology. And IP vendors are beginning to talk about how IP will have to be characterized to work effectively in stacked-die configurations.

Unanimous vote of confidence
Possibly the most dramatic change has been at Synopsys, which has been vague about stacked die for the past couple of years as it tried to sort out where the issues were and where the opportunities will be.

“For some time, the situation has been very foggy,” said Marco Casale-Rossi, product marketing manager for implementation platforms at Synopsys. “We decided to let things settle to understand the main directions, and believe that over the last 18 months we have understood where mainstream will be—2.5D with an interposer. It will be a number of die, side by side, communicating through an interposer and with the outside world through a TSV.”

Synopsys has decided to focus in three areas: a complete solution for implementation and verification; an evolutionary 2.5D to 3D flow that builds on what already exists; and an R&D commitment with customers and research groups to solve whatever problems may come up in the future.

“Extraction will be very important,” Casale-Rossi said. “We need to take into account a number of new elements such as microbumps, TSVs and interposers. And historically, EDA tools have been designed to deal with one process technology at a time. Now we’ve got bricks manufactured using different process technologies and the rules are different depending on the die.”

EDA’s next big thing
Synopsys isn’t alone in trying to predict where the pain points and the opportunities will be. Both Cadence and Mentor Graphics threw their support behind stacked die over the past couple of years, and Cadence has been working on system-in-package since the beginning of the millennium. So far it appears that the opportunity is large enough and broad enough that there isn’t much overlap.

Cadence has built its 2.5D suite from its SiP tools, which were introduced in in 2007 at a time when the market was still focused on planar ASIC solutions. At that point, the company was divided over whether stacked die would really be an opportunity going forward. There is far less doubt these days that it was the right choice.

“The big question as we got into 3D was whether we build separate tools or use the same tools,” said Samta Bansal, senior product marketing for SoC Realization at Cadence. “We did need new layout tools because of the new electrical features—TSVs and microbumps. The analysis tools also have to be able to comprehend the new constraints, which are thermal and mechanical. And we needed new models and tools with respect to microbumps, and had to make sure the current tools understand the new dimensions.”

She said TSVs are similar to vias, but still different enough to require changes in the tools. And floor-planning requires understanding of placement in a stack to optimize behavior. But she noted that what customers discovered they really needed were tools for packaging.

“Customers that are developing 2.5D are looking at this one of two ways,” she said. “One is a package-driven flow, where the interposer is an extension of the package substrate. The other is an IC-driven flow, where as you go along you have more TSVs and more IC-centric routers. But for both of them, 3D stacking is a combination of digital, custom (analog/mixed signal) and the package.”

A 2.5D stack. Source: STMicroelectronics and Cadence

Mentor Graphics likewise has been extremely active in 2.5D, with a long-range view of 3D stacking, focusing in particular on both test and manufacturability.

“Several factors need to be addressed,” said Steve Pateras, product marketing director for Mentor Graphics’ silicon test products. “One is known good die. How good is the testing before you put chips in a package? Most times you test chips after they’re already in the package, but with 2.5D and 3D the yield goes down as you increase the number of die.”

A second issue involves I/O testing—or more accurately, the lack of testing—which takes on new meaning in a stacked die. In stacked die, it’s imperative to test the I/O before the die are packaged because many times it will not be testable after they’re already in the package.

Pateras said one of the approaches being talked about is wafer on wafer stacking to reduce costs, but that makes it particularly hard to test. He said the better approach is die-to-wafer stacking, using a base wafer with everything else stacked on top for greater control and better yield. But that also creates another problem.

“When you stack heterogeneous die in a stack, there is no standard for communication between the die,” he noted. “We’ve solved one problem, which is memory stacked on logic. But we need to develop a 3D test standard and standards for embedded self test.”

On the manufacturing side, Mentor has modified its DFM tools for 2.5D and 3D verification. And most experts believe existing ESL models can be relatively easily tweaked.

What’s still needed
It’s easy to forget that 2.5D and 3D are evolutionary steps with possibly game-changing impacts. While some EDA tools have always been offered well in advance of the mainstream, they are typically behind the chip design teams working at the leading edge of Moore’s Law. At 20nm and beyond, the cost of making chips has become so enormous that leading-edge companies are building upward. And as they do so, they are finding some pieces are missing that will need to be filled in.

“The first thing that’s missing involves the temperature issue,” said Ghislain Kaiser, CEO of Docea Power. “When you stack die together you’re putting more power into a package, whether it’s 2.5D or 3D. You have to manage that. Many times there is no dissipation problem, but you need to have tools to make sure. You need to be able to analyze the dynamic power profile, and right now it’s impossible to make a link between the software and dissipation when you run actual software on the chip. The best you can do is a simple profile.”

One of the great benefits of stacked die, in addition to not having to move analog designs to the next process node, is increased flexibility and options for designers. Teams can stack different memories in different places and they can move functionality from one die to another to improve performance or lower power or both.

“With that freedom you need to do more exploration,” said Kaiser. “But you may have too many degrees of freedom. You need to be able to optimize different chips along price, performance and power. And you need more accuracy. The gate-level tools are not 100% accurate.”

That’s easier said than done, however. There are no standards in the IP world that would allow an accurate comparison between one piece of IP and another. Frequently they are not even measured the same way by different vendors. Moreover, they can vary significantly with different usage scenarios.

That’s typically where standards fit in. Cadence’s Bansal said the foundation to enable 2.5D and 3D is clear, but there needs to be a seamless and consistent way to integrate digital, AMS and the package. “If the routing is not optimized, for example, you may end up with several layers of interposer. That will make the chip much more expensive.”

By Ann Steffora Mutschler
Throwing out the term ‘application-driven power-aware design methodology’ may sound like gobbledygook to some, but this concept is keeping many technologists awake at night—especially considering video games that heat iPads to 100+ degrees centigrade (near melting). The problem is very real, and potentially painful in more ways than one.

The iPad example, along with others such as streaming video and heavy graphics in Facebook applications, which exercise the complete logic, SoC and memory access, along with high speed DDRs for displays and the display itself, show just how power hungry consumer applications are—and how much new thinking is needed to address the problems.

“If you have a GPU that is driven by high activity games, so-called power guys who are really driving the game industry, it can define the maximum power consumption limit. Instead of using the same GPU, which is doing multiple applications of low-activity movies or low-activity plain dialogue movies versus action movies versus streaming 1080P—one can think about creating GPUs that are specifically designed for those applications and optimized with respect to dynamic and leakage power,” suggested Vic Kulkarni, general manager and senior vice president of the RTL business group at Apache Design.

The alternative is creating different application processors and GPUs on multiple SoCs, including 3D stacks. “That’s another thing people are looking at very aggressively—how do we get logic on logic or logic on memory to manage power and heat,” he said. “Application-specific processing units may be better for power optimization as opposed to general purpose CPUs for different applications.”

Application-driven is really where things are headed, agreed Cary Chin, director of technical marketing for low-power solutions at Synopsys. “If you want to do the best possible optimization, one of the problems is that when you are doing the lower-level design, you don’t really know exactly what you are designing for. That’s been a dilemma for a long time. You have to make some decisions about what your target application is, and for the most part over the years we’ve gotten away with this idea of general purpose computing. You can write software to customize things, and then build the hardware however you need. The problem is when the big issue is power—as it has been for the last few years and apparently will continue to be for quite a long time—the optimizations that you need to do make a big difference at the hardware level, and for each particular application the requirements are different.”

But the amount of complexity that is being added into the mix is still on the rise.

“If you think about the amount of stuff that needs to happen—this idea of application-driven in terms of power efficiency is great, but the problem, like in most complicated problems, is that you can’t really do it top-down,” Chin said. “It would sure be nice if we could say, ‘Lets just make the applications aware,’ and everything works underneath that.”

At the heart of these designs are the highly skilled system architects, which to Chin seem analogous to good cooks. “A good cook very rarely has a recipe that they’re cooking from. They don’t say, ‘Here are all the requirements of what I need; I’m going to go get all this stuff.’ A really good cook looks at all the good stuff that’s available and creates things based on what’s available, and I think that’s what system architects do. An architect’s real job is to understand the technology, both on the hardware and the software side and maybe the application side, as well, in terms of how applications are created and distributed. The stuff that’s going on in the architect’s mind is that they start to create and formulate what kind of things can be made with the pieces that are coming together.”

Architects are thinking about customizing logic for particular very specific needs these days, he noted. “I think that’s what we’re going to start seeing because there are so many gates and so much silicon available. The idea we’ve designed around for the last 30 years or so, which is that we’re generating general-purpose silicon that basically does optimization based on re-use of the silicon for many functions, is exactly the opposite direction of the optimum for low power. To get the lowest power design you need to custom design a specific function that you need without having any other transitions in your device. If you could create custom logic for everything you would have an ultra low power device.”

Summing up the need for application-driven power-aware flows, William Ruby, senior director of RTL power product engineering at Apache Design explained, “If you look at software and hardware—these are the two basic parts of a system. Traditionally software has not been power-aware at all, and software is now being used to control the hardware. Software itself does not consume power, but it has a huge impact on how much the hardware is burning. What needs to happen is that you need to start thinking about realistic application scenarios.”

There is a huge amount of infrastructure in place to design for functionality, find functional bugs and identify corner cases. “But a lot of that infrastructure is simply not suited for any type of power analysis or power driven design work: you need something fundamentally different,” Ruby said. “If you look at how the application-driven flows will evolve, you start with the application and then you say, ‘How can I simulate, emulate or somehow replicate the effect of running that application on this hardware.’”

Regarding emulation, Qi Wang, technical marketing group director for low power and mixed signal at Cadence, explained that traditionally engineering teams have done power estimation by running some functional tests to get activities to drive power estimation. But those activities are for functional testing and have no way to represent the actual application. “This is the biggest disconnect right now and people now realize that, but there’s no technology to bridge the gap because this huge abstraction gap between system abstraction and silicon abstraction,” he said.

However, hardware can be mapped to the emulation box today and then system software and applications can be tested. Traditionally emulation boxes were used to verify system functionality used by software or application, but emulation is now being extended to do power estimation, as well.

“If you think about it, it’s a very natural extension because you run those applications anyway to verify the functionality,” Wang explained. “Why not at the same time take down the traces to record all the activities and send it to the power estimation tool to do the power estimation? That kind of bridges the gap between the software application and the actual hardware. And it’s not just for power estimation. We know that a lot of people doing advanced low power designs do power management and power gating.”

Overall, application-driven power-aware tools will need to both address the performance angle as well as model and abstract the design to higher levels able to run a system type of a power simulation, Ruby asserted. “These models need to be as accurate as possible. You need to start building a model chain all the way from silicon up to the power spec.”

It comes down to modeling and processing huge amounts of data, he concluded.

By Ed Sperling
Knowing when to signoff on an IC design has always been as much art as science, matching engineering experience with managed risk. As ICs become more complex, however, even the most advanced chip companies are getting things wrong.

Some of this can be fixed through software and some of it can be tweaked with programmable firmware. But some of it may have to be fixed in the next cycle of chips.

“We’re seeing three different scenarios unfolding as we push to lower power and higher performance,” said Arvind Shanmugavel, director of application engineering at Apache Design. One is operational, the second is time-based, and the third is event-based.”

The operational problems enter the picture when areas of the chip are switched on and off. The transitional current can be high enough to cause serious issues. The time-based concerns involve electromigration. Electrons over time damage metal interfaces, which must be minimized by controlling the amount of current flowing to interconnects and creating an accurate model of the temperature distribution across a die. The event-based issues stem from voltage and frequency scaling. Sufficient feedback about temperature is required to prevent wires from burning out.

“The event-based liability is ESD, which occurs regularly in high-performance ICs. But it generally is not discussed in EDA,” Shanmugavel said. “You need to know if there is a hit, how is the IC hit and whether you can reliably discharge an ample amount of current. We’ve had a 2 kilovolt standard for decades, but devices are getting smaller and they’re discharging the same amount of current. Designers need to do true simulation and characterization to avoid wire burnout. The wires are thinner, too, so even the same amount of current can cause problems.”

The laws of physics
Shrinkage brings other problems, as well. Metal spacing rules traditionally were driven by lithography, but physics has taken over.

“If the metal spacing is too small, the electrical field may become too intense,” said Ting-Sheng Ku, director of engineering at Nvdia. “The spacing rules increasingly are dominated by the electrical properties of the dielectric, not the lithography. At 28nm the industry saw some of that. At 20nm the spacing can become a real problem if the industry does not address it.”

Nvidia typically runs at the front edge of Moore’s Law, so the types of effects it is witnessing are brand new to the design industry. Ku said many of these had been predicted, so there is little surprise even though solving these new problems remains extremely difficult. But one area that is emerging is in the area of longevity of parts.

“Transistors get weaker as time goes on,” he noted. “You get impurities trapped in the system and they do physical damage. This is all physics-related, but as features get smaller this gets worse.”

He said more modeling is required for these kinds of effects over time to avoid future problems.

New types of errors in stacks
As if things weren’t hard enough, there are new types of errors being introduced into chips that didn’t exist in the past, particularly in stacked die.

“Just having extra processing steps can generate errors,” said Marc Greenberg, director of marketing for SoC Realization at Cadence. “There also are mechanical issues when you put die together, and you have additional annealing steps from TSVs.”

This is particularly troublesome for memory because DRAMs are somewhat delicate, he said.

And in extreme environments, single-event upsets caused by radioactive particles have always been a risk. But they become an even greater risk as features shrink and more gets packed together, either in planar or stacked configurations. At advanced nodes, margins can affect performance and power. But cutting margin means that if anything goes wrong, there isn’t a failover mechanism.

Verification and other challenges
Even without unexpected outside interference, just having confidence that issues have been fully addressed is a big issue. Verification coverage in a complex SoC is almost impossible to address in a reasonable market window.

“Verification is going non-linear in complexity,” said Aart de Geus, chairman and CEO of Synopsys. “Hardware and software interactions will continue to become more complex because the functionality is the hardware plus the software. In addition to that, we have to keep physics in check.”

The good news is at least tools makers are aware of the problems.

“We are getting this under control,” said Apache’s Shanmugavel. “But reliability has always been the stepchild of simulation. It has not been treated as a functional problem. That will have to change. We will need to use models to create probabilities and rely more on event-driven simulation—and then we will have to string it all together to see if we’re getting a voltage drop over time or a high peak current.”

And if none of these problems is insurmountable or unexpected at 20nm, there surely will be others that arise as companies begin testing chips at 14nm.

By Ann Steffora Mutschler
As design and manufacturing issues with true 3D design continue to be worked out, interim 2.5D technologies are moving ahead as engineering teams leverage this packaging-driven approach to manage heat, cost, area and yield.

Technologies such as Wide I/O memory support 2.5D, and when combined with logic they allow engineering teams to realize a performance increase, particularly for applications such as GPUs and gaming where there aren’t significant area constraints but there are performance and power demands.

“That’s where people are using Wide I/O memory and logic side by side in a 2.5D silicon interposer configuration,” observed Samta Bansal, senior product marketing manager for Silicon Realization at Cadence. Also, there is less of a heat management burden for 2.5D—another reason that engineering teams are looking at 2.5D now.

On the power side of 2.5D designs there are some extra issues that have to be considered during the design process, pointed out Steve Smith, senior director of 3D IC strategy and marketing at Synopsys. “For example, the die that you place on the interposer are bare die. They are not packaged. This is one of the issues that you have to think about. How do you drive the signal connections between each die which are relatively long? You could have relatively long wires feeding between a pair of die—maybe like in the case of Xilinx they talk about actually building special I/O drivers that are matched according to the power needed to drive the signal across a certain length of wire. They figured out based on the length of wire how big the drive strength should be and then modeled that and created a special I/O cell.”

Another power issue with 2.5D is how to get power reliably into the die from the interposer, he said. “The way it works with a silicon interposer is the power comes from outside of the package all the way back to the battery, basically up through the package I/O, up through the interposer through silicon vias (the metal connections from the front to the back of the interposer die) and then gets transferred up into the die themselves so the actual TSVs, the placement of them, the number of them have to be figured out to reliably get enough power up to the die. Then you also have to think in terms of the signals that cross between the die and make sure you have enough power to drive those as well.”

Thermally speaking, there are heat issues with 2.5D-stacked designs, but these are being modeled with traditional thermal tools that engineering teams are already using.

“At the moment, we’ve got an interposer and essentially flip chips sitting on top of them, so a lot of the modeling is happening at a macro level using traditional tools and current systems. I think it will start to change when we convert those simple flip chips—simple being a relative term—to being a true, active die that has through silicon vias in it, and then where it’s stacking multiple things up higher in there. I think that’s when we’ll see the next fracture of the methodologies,” noted Matthew Hogan, Calibre marketing engineer in the Design-to-Silicon division at Mentor Graphics.

Some challenges not technology-related
In addition to the thermal and power issues, there are also challenges related to how to best allocate the new tasks inherent in 2.5D design.

“Traditionally in the IC realm a lot of organizations are set up with a system architect that designs the chip and the chip gets broken up into little blocks. The teams then go away for 3 to 18 months, then come back and do final chip assembly,” Hogan said. “All of those jobs and tasks are very well identified and we have the tradition of who does what, where and when. Eventually we go into the package side of things. One of the things that we’re seeing is from a 2.5D and 3D IC perspective, we now have this concept that gets overlaid where we’ve got a system netlist, so it’s a system design where we’ve got our flip chips on top with our interposer.

But who actually owns the netlist isn’t always clear.

“If you take a traditional IC design flow then maybe you’d say the packaging guys did the assembly and the package and that sort of stuff—maybe it’s over there. If you have a look at the front of this whole system, you’ve got a system architect working in ESL and he doesn’t necessarily deal with the 128-bit data bus that’s got level shifting on it. He deals with, ‘I need a communication channel between this chip and that chip that does 3.5Mbps because this is the data stream that I want.’ Somewhere within the definition of the high-level architectural view of what the system needs to look like and the physical implementation there really needs to be ownership of this system netlist, which is a pin-accurate description of how these different devices and designs are going to be connected together. That’s what you use when you go and do your verification of the complete 3D assembly,” he said.

The result is that ‘traditional’ IC design and verification groups need to expand and look for either different resources or tweak what they consider their roles and responsibilities so they can handle this new system netlist. That way, when they verify the 2.5D or 3D stack they understand who owns what, where it comes from and how it was created.

“They’re doing these sorts of netlists already when they do their LVS verification and there’s a golden LVS netlist,” Hogan said. “But that guy’s dealing with one chip and a whole bunch of IP internally when you get out to the system of 2.5 and 3D stacks. It’s that system view that you need to create yet again—another golden system netlist.”

Are new tools required for 2.5D?
With any new technology, there is always a concern in the minds of engineers about whether they will have to add new tools to take advantage of what the new technology offers. With 2.5D, engineers can rest easy, for the most part.

Generally design teams are able to use a lot of the traditional techniques and tools that they’re currently using to really understand what’s happening from a power and thermal perspective in 2.5D.

Synopsys’ Smith pointed to the oft-quoted Xilinx stacking example and noted, “They’re claiming they started working on their interposer design eight years ago. At that time, there were no special tools for doing this, although strictly speaking you could regard 2.5D as kind of like a multi-chip module, which has been around for decades. It’s a packaging concept where you put different die on a package substrate like a mini circuit board. So that’s been there.”

Replacing package substrates with a silicon interposer results in the same kinds of issues, he noted. “You’ve got the close proximity of the die, they’re all going to be packaged together in the same package, so I think the thermal issues, for example, are very similar in that sense. I think the reason why companies are saying they’re managing is because this is very familiar to them. The people that work in the IC design companies usually have a separate packaging group/team from the design team, so the packaging team would be the ones that have the expertise in dealing with thermal issues with multiple die in a package. The advantage of an interposers is, because we’re not stacking active dies on top of one another there are no issues with die interfering directly with each other. If you did a true 3D IC, you’d be stacking active die on top of one another. Then you have a massive thermal issue.”

In 2.5D, the interposer has no transistors on it. It’s just wiring. And the tools that are used for thermal analysis of packages are equally applicable to 2.5D. While it is a rough analysis (because that’s all that’s needed for now), in 3D IC design the analysis is more complex because the areas in the silicon die with the higher temperatures must be identified as this impacts performance.

All of the big EDA vendors began addressing 3D design issues a few years ago and are well on their way. When the industry changed focus to 2.5D as an interim step driven by the foundries and packaging companies, the most complex issues were already identified.

From Synopsys’ perspective, the most dramatic impact to the 2D design flow to accommodate 2.5D has been the routing for the interposer, so the company added a more regular silicon routing system. At Cadence, Bansal noted that the company has been building up its 2.5D/3D flow most notably with STMicroelectronics; in addition to its inclusion in foundry reference flows. Mentor, as well, has extended a number of its tools to accommodate 2.5D/3D IC design and has established key relationships with foundries such as inclusion in reference flows.

At the end of the day, engineering teams can leverage the benefits of 2.5D now using existing tools as they prepare their organization and methodologies for the full step to 3D when the time comes.

By Ed Sperling
One of the consistent trends among successful companies, particularly in well-established industries, is that over time labor becomes specialized. No one can do everything well, and the more complex the systems the more pieces have to be outsourced.

This creates immediate benefits for companies putting together the overall systems. They can focus on designs and doing what they do best. And it creates new problems, because standards have to be created and updated so the pieces fit together exactly as planned. This is particularly difficult in complex SoCs, so rather than breaking pieces down to their most basic component level, they are partially re-aggregated into subsystems.

The automotive industry went through a similar transition. In the early 1900s, when cars were still basic and the industry was new, all the components came from the same companies. By the 1950s, there were suppliers of most of the components inside of cars, but gradually those aggregated into radios, seats, cooling systems, and more recently there are suppliers for wiring harnesses and the electronics that are replacing mechanical components.

From IP to subsystems
Subsystems are the likely follow-on to IP blocks inside of SoCs for several reasons. First, it gives vendors a way to capitalize on their success in the IP market—and to distance themselves from those companies that failed. Early adopters of third-party IP learned quickly that just because one IP block is priced lower than another doesn’t mean it will end up costing less in the long run.

It costs a lot, in terms of money and manpower, to fully characterize IP for complex SoCs. Even standard IP must fit into non-standard chip configurations with sensitivity to noise, heat and power.

Synopsys’ audio subsystem introduction last month is a case in point. Its decision to bundle its audio chip into a subsystem combined both internal IP and tools with the ARC processor and other IP it acquired from Virage Logic. “The goal was to create a drop-in audio solution that is fully configurable,” said Henk Hamoen, product marketing manager at Synopsys. “We took Virage’s audio codecs, Synopsys’ A-to-D capability, and we added system-level tools virtual prototyping and an assembler.”

That leads to reason two, faster integration. Synopsys’ top rival in this market is Tensilica, which has been developing its own audio subsystems and racking up a long list of codecs to fit into any possible scenario.

“If you were to build the entire thing out of state machines, you would need to lay down 5 million lines of code,” said Steve Roddy, vice president of marketing and business development at Tensilica. “Most successful subsystems have hardware and software and they’re programmable.”

The third reason involves competition. Integrated subsystems raise the barrier of entry for IP vendors to compete in this market. Small IP vendors have a tougher time competing with competitively priced, pre-integrated and verified subsystems—particularly if they can be customized. But there also are logical limits about what gets bundled.

“It may seem natural to an IP provider to put audio and video subsystems together, but no one is asking for it,” said Roddy. “There is a naturally occurring separation. The people who buy DSPs aren’t analog guys so they don’t always understand that side as well the IP vendors do.”

Preparing for stacked die
Subsystems are seen as a great way to speed time to market in complex SoCs, but they’re even more critical in stacked die. Memory subsystems, for example, will likely be entirely separate chips that are included inside the same package.

“The industry in general is looking at more and more integration,” said Vishal Kapoor, vice president of product management at Cadence. “We’ve moved from gate to IP to separate pieces of IP, and in general we’re looking at subsystems—although there is some debate about how to define a subsystem. Connectivity between products appears to benefit from pre-configuration or organizing things together.”

In 2.5D, at least, this is relatively straightforward. Subsystems created in one process may not need to be moved to the most advanced process, particularly when it comes to analog.

“If you have audio DACs (digital-to-analog converters), for example, and they work fine, there’s no need to build new ones” said Tensilica’s Roddy. “If you look at the typical catalog of a mixed signal company, they may have 2,000 to 3,000 parts. A lot of it is older technology, but you can take some of that and for $50,000 turn it into a custom part. You couldn’t do that if you integrated it on a die. This allows you to tweak the analog customer by customer, and to mix and match Legos.”

He said Tensilica has a couple dozen customers in the United States, Europe and Japan working on 2.5D chips, mixing and matching multiple analog parts. That’s can be particularly good news for subsystem vendors. “If you bundle multiple IPs together when it makes natural sense, then you get a multiplier effect for these chips.”

By Ed Sperling
Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion.

LPE: The supply chain needs to function almost like an extended IDM model, right?
Goodenough: Yes, but it’s not a new concept. All of this was done in the automotive industry 25 years ago. The semiconductor industry is transitioning there. People are trying to manage the risk of taking a product out, and they are dependent on a lot of moving parts. Their goal is to understand and manage the risks.
Butler: But it needs to come in a consistent way. You don’t want to be on a plane every week. You need to have an abstraction that gives you the visibility you need without having to have a VPN license.
Hand: You need to set up a hosted design chain for the customer. Everyone is working within that common collaborative environment so that when something goes wrong it can be quickly addressed. As there are new revisions, they automatically drop into that environment and the customer sees them. That’s a trend that’s happening now.
Butler: That might be true if you’re both working on parts of the SoC. But if you’re a systems house and you’re assembling, then it’s a different tool set.
Hand: That’s correct. But the trends in the microcosm of IP are beginning to move into that realm, as well. Once you get into a system context, the EDA/VIP world doesn’t really fit into a system environment with their supply chain. That’s a challenge we have to resolve.

LPE: How does that affect growth of IP?
Hand: It affects everything up and down in the stack. It goes down to integrating into the SoC with RF, RF-like technologies such as optical, data converters, analog—all of that is starting to come as IP instead of standalone chips. The software and firmware stacks are more of an IP area. And once that gets solved, the next thing is how you build that into the system level models and supply chain models that are required for that. But we’re at such a low level on the IP side that there’s a lot of integration that has to happen.
Goodenough: I just came from Linaro. When we look at the new IP, it’s the software IP and analog IP. It’s the next logical thing to do. It’s the up-and-coming thing where people are looking to reduce cost. It’s no longer a real differentiator, so you just outsource it. But then you have to look at managing those software communities. It’s open-source software communities and making sure the platform and the instruction set and the memory maps of the platform architecture are being consistently reflected up to the software community and the operating system guy, so that when you plug those things together they work.
Hand: And in some cases that IP may become standalone and part of a 3D stack, in which case you have to manage that whole supply chain. How do you get that integrated onto the stack? In some cases, because of cost, risk or performance, you may not want to integrate some of this IP natively into the SoC.

LPE: Analog is a classic example of that, right? In 2.5D, you may want a whole separate chip at an older process node.
Nandra: Yes. We do build stuff that integrates into more nodes, but we also have customers that would like to put their analog into a 65nm power management IC, including the rest of the interfaces, and then the rest of the SoC at 20nm or 14nm. At 65nm, the power management is leading-edge technology. There are still some design challenges, although they’re not so difficult if you’ve worked at that node before. The point about stacking and packaging is quite interesting. From a signal integrity perspective, a lot of these things become easier. You don’t have long wires or cables anymore. You just have some communication going through the software and a via. The challenge becomes thermal dissipation between the substrates. You have a substrate at 65nm and one that’s at a smaller node with very different thermal characteristics. Someone has to figure out how to widen the memory lines so they don’t fuse together.
Goodenough: It’s a new context. They’re just wires, but they’re wires done in a different way.
Hand: The other challenge is a business one. Who owns the risk? If you have Wide I/O and a Wide I/O memory chip, the memory chipmaker says this is a known good die but it couldn’t be tested out on the landing pads. So it gets thinned out, stacked on seven other dies and then you finally do a test of the whole stack. It doesn’t work. Who owns the problem? You’ve got eight memory chips and an SoC, and it’s packaged and pinned out. Who owns the cost?
Nandra: From a practical packaging perspective, all of these technologies in 3D IC and wide I/O are really expensive. We’ve had similar discussions on Wide I/O. It’s a throwback technology with significant performance, but you have to invest heavily in your package. When it comes down to high-volume parts, people aren’t going to pay the money for this.
Hand: It depends. It’s the overall cost of the system that’s important. If you can get the overall power down and performance up, companies will invest. We’ve got customers investing in this now because it’s a way of differentiating. If you’ve got smartphone SoC vendors and they can differentiate with better power and performance and win the socket, they’ll do what they have to.
Nandra: With Wide I/O, that roadmap has been pushed out as people try to make LPDDR meet that requirement. Today, JEDEC is looking at LPDDR 4. That will push out Wide I/O further. From a technical perspective I totally get why big companies are looking at this technology. They’re also looking at fully depleted SOI, for example. But it’s not going to make it into a tablet or smartphone.
Goodenough: It’s a question of when the cost is right.
Hand: For many customers, LPDDR 3 will solve their immediate problems. But if you look at the trend, this is already happening. To get terabit per second performance out of memory you have to go to stacks. It’s not a question of whether the cost equation will work for this. It’s just a matter of whether it’s next year or the year after that.

LPE: We’re looking at a complete bifurcation of the market—those who do massive volume versus those who work in lower volumes.
Goodenough: It’s not so much volume as how much you can recover from your investment in how you make your silicon. Whether that’s a micro on a board, a processor in an FPGA, a custom chip, all that matters is how much profit you’re recovering. If you can only recover a wafer-thin margin you’re not going to be investing in new technologies.
Hand: Then you need volumes of 50 million units a year to get your money back.

LPE: But this does play into subsystems, because you can integrate all the pieces and achieve much greater volume, right?
Goodenough: It’s no different than boards. You’re seeing that happening in SoCs and FPGAs. Whether it’s going onto a board, a hard block in an FPGA, a soft fabric in an FPGA or a custom ASIC, they’re all basically different compile points that end up as a piece of silicon with a different price and a different energy envelope. And if you go to China with a standard part, you can probably turn a board around in two or three days. That’s a big difference from spending 2.5 years doing a custom IC.
Hand: You’ll have much of what was on the board in an SoC itself. Whether that’s integrated into an SoC or a stack or just integrated parts, it depends.
Goodenough: But if I’m a customer I don’t really care about that. I only care about how much power does it use, how much does it cost and what’s the form factor.
Hand: There have been many chips in the telecom world that make no sense to manufacture if you measure them by consumer SoC metrics, such as how many units have shipped. But the value you get out of each of those means they can make the economics work. Going back to context, there’s an economic context that people building a system are operating in. If you’re providing IP, you have to provide the right deliverables in the economic as well as the technical context. That’s what will drive subsystems more than anything else, too—the economic context.

LPE: And time to market is part of that economic equation?
Hand: Yes. If most of your chip is good enough to get the job done and you can do it in a few months of integrating extra pieces, while assuming everything you didn’t touch works perfectly, that’s a compelling argument.
Nandra: We see that with smartphones and tablets. In China, customers are starting to get into the tier-two markets. They’re all about derivatives. The idea is that you do reduce the cost of the IP.
Goodenough: You have to maintain IP, though. The IP may be fixed but the context is evolving. You have to evolve your IP as that context changes from four-layer boards to two-layer boards, or 32nm to 14nm. IP has a long lifetime and you have to anticipate where it’s going to land.
Butler: What’s particularly interesting is the IP view of defect tracking. A defect in IP never really goes away. There’s always somebody using it somewhere, and you need to know. It’s different from software where the lifetime is project-based. What we need is something that tracks bugs in IPs that goes into a system context so you get all your dependencies.