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Posts Tagged ‘Chartered Semiconductor’

Intersection for Success: 1Ghz at 2 watts

Thursday, June 11th, 2009

By John Blyler
Mentor Graphics recently held their annual User-2-User conference in San Jose. The press was invited and – as usual – got along well with the users.

The day’s events were kicked-off by Simon Bloch, VP and GM for Mentor’s Design and Synthesis Division, who began his brief introduction by highlighting the new format for the U2U conference, namely, smaller and more targeted sessions that matched specific markets to specific regions of the country. This was why there were no sessions on PCB or FGPA board design in the San Jose session, since Silicon Valley is know for as the hip design mecca of the world. Accordingly, Mentor’s board level U2U show will be held on October 7th in Minneapolis, MN.

One thing remained the same was that all conferences would be free to attendees.

Bloch, as refreshingly succinct and direct as ever, closed his brief opening remarks by welcoming the keynote speaker: Charter Semiconductor’s Walter Ng, VP of Design Enablement Alliances.

Keynote Address

Ng’s background in both the design and foundry worlds gives him a comprehensive view of the direction of the EDA and semiconductor industry. While the message he delivered wasn’t new, its impact has become more evident as both industries push to lower process nodes.

Ng started with the basic question about the current push by leading-edge companies into the 32nm and 28nm process geometry nodes while capacity still exists in the higher nodes. The chief motivator for this downward push was the need to both differentiate while increasing the integration of SoC products in the mobile Internet market.

Some readers may recognize this push in the mobile Internet market as yet the latest incarnation of the continuing intersection of computation-communication technology, a subject which was previously manifested as the battle between 3G and Wi-Fi networks. (For example, see 2002 article: “Will 3G Have To Compete For The Wireless Future?

This time, however, the discussion is on power and performance, not which wireless connectivity approach is best. Specifically, performance-rich PC/Notebook devices must come down in power, while low-power mobile Internet devices like smart phones must come up in performance. Devices must run on lower power consumption so that longer battery life can be achieved. [See “…innovation in battery capacity stalled…,” Chip Designers Scramble for Low Power:

The winner of the race to achieve the optimal intersection of low-power and high performance will reap significant market share rewards. Ng estimated that there will be near 700 million mobile Internet devices by 2012. High performance is defined as at least 1 GHz of computational speed in a mobile device with total average power consumption of 2 watts. Remember those intersect coordinates: 1GHz speed at 2 watts total power, since they represent the minimum requirement for mobile devices to compete with their computational brethren.

Achieving this goal in mobile devices is non-trivial. The traditional silicon solution of merely scaling down the transistor size to a smaller node will not work. While lower process nodes – e.g., 45nm, 32nm and 28nm – do provide higher performance at low power levels, transistors at this geometric size leak current at high rate. What is needed now more than ever, explained Ng, was innovation. “One technical innovation that foundries have developed is High-k Metal Gate (HKMG) technology which allows 1 Ghz performance at smaller (at 32 nm) geometries.”

The story on the PC market side (processors) is similar, but with the emphasis on lowering power instead of improving performance. Here, the innovation has been multicore technology, where a single core at 45nm becomes a dual core at 32 nm. Ng believed that further integration, such as quad-cores, will lead to PC-compatible performance with ultra low power (less than 2W).

Staggering Costs

The biggest obstacle to achieve the required 1GHz performance at 2watts or less may be cost. Not the cost of the end-product, but the cost of the foundry to manufacture the chips. As Ng pointed out, fab costs along (not including process research and development (R&D), design and mask costs) are about $3billion at 45nm and $4 to $10 billion at 32 nm. These staggering costs are one reason why traditional IDMs, like Texas Instruments, are exiting the foundry business beyond 45nm.

Ng emphasized that strong R&D is a must to achieve need power and performance numbers. In other words, the benefits for CMOS scaling to lower process nodes now comes at a much higher price. That price is paid by greater innovations, for example, new wiring technology, transistor improvements, creation of CMOS FinFETs and others. All of these innovations take an ever increasing investment in time and money. [For more on FinFets, see: Pain Points At 22nm And Beyond,

High K Metal Gate technology is a good example of the time and cost involved in researching and developing new technologies. Chartered is just now bringing HKMG process to market, in conjunction with the IBM and the Common Platform Alliance, explained Ng. “Research in material science properties for HKMB started late in the 1990s for IBM.” He noted that such a huge strategic investment in R&D requires a very stable business model, such as those only available to the large IDMs like IBM or Intel – not the foundries. Since that time, all the major fabs have formed partnerships – like Charter’s with IBM – to gain access to material science research, among other things.

In addition to gaining access to technological innovations, there is a strong business case for such partnerships. In the past, the time difference or delta time between the adoption of leading edge technology by the general consumer was about 1 year after the acceptance of such technology by early adopters. Today, however, that delta time period has increased, which means the return of investment (ROI) for the foundries and the rest of the supply chain is stretched out. In general, most foundries don’t recover their investment on a new node until production runs for the general consumers. If that return is delayed, then the foundries face a quandary. Do they invest in the leading edge technology node at the beginning of the cycle or wait until the general consumers have adopted the technology? By and large, the top-tier foundries support the leading edge, while the other fabs find it more cost effect to focus on a niche strategy, notes Ng.

But investing late or early, the challenge today is to meet power and performance demands through innovation, not simply process scaling. Innovation requires R&D investment, which in turn means that strategic partnerships are essential, such as those between Chartered, IBM and Mentor.

That is a good message to deliver for the designers at this year’s user group meeting.