By Ann Steffora Mutschler
It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2.

But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most efficient way through the design flow.

If power is not implemented in the most efficient way, meaning if it isn’t optimized and reduced to the bare minimum, then what’s the purpose of designing it?

“Whatever the power ends up becoming, it is what it is, and in many traditional designs this has been the approach,” said Shabtay Matalon, ESL market development manager at Mentor Graphics. “There wasn’t in mind an objective to say, ‘Let me design it such that the power will be minimized.’ The power conservation and reducing the power is the primary objective.”

Most tools that address power today begin at the RTL, but there is an increasing consensus that this may not be early enough. “The percentage of gates or transistors in a design that can be exercised at the same time is shrinking and shrinking,” said Matalon. “On one hand we get this huge capacity to put billions of transistors on silicon. On the other hand, the power is [holding back] the percentage of the resources that we put on the chip that can be exercised. There is a need for this intelligence that is usually in the software. I’m sorry to offend anybody on the hardware side, but the intelligence is really in the software that is running the application—the software that understands the application context to play a role in reducing the power in the environment. Obviously, the hardware needs to be below the infrastructure and that’s why RTL might be too late.”

Design-for-power is not just analysis at the RTL. It is design for optimizing power. Some define a design-for-power methodology as having a gate-level representation, running some analysis, then predicting the power. Predicting the power accurately at RTL is highly questionable, though, unless you really run the device in the same operating conditions that you will actually use it.

“But there is not even a doubt that when you are doing this analysis at RTL down, that you lost your possibility to optimize,” said Matalon. “Design-for-power is not just analysis. It is the reduction of power.”

Example of a power methodology. (Source: Mentor Graphics)

Larry Hudepohl, VP of hardware engineering at MIPS, agrees. He said the importance of power as a design metric is one of the first and foremost criteria, not just an afterthought when putting the final chip together. “In the same way that the analysis of performance has moved much earlier in the design flow in advance of RTL, I see that same trend happening on the power side too. Earlier estimation of power, especially in a complex SoC where there are multiple devices driving multiple complex interfaces so the modeling of that—the power dissipation characteristics of the full chip under different operating conditions, under different power management modes—can really be assisted by modeling in a stage earlier than RTL.”

On the other hand, Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions, stressed that RTL is indeed early enough for a DFP (design-for-power) methodology. “Design for power must be done at the design level of abstraction, and for hardware design this means RTL. Anything after RTL is either automatic optimization (e.g. synthesis) or implementation, which in the case of the digital flow is also automated (i.e. place and route).”

Apache’s view is that a key part of a DFP methodology is power debug and power efficiency analysis, and the benefit of doing these at the RTL is a significant improvement in productivity (and corresponding turnaround time reduction) compared to traditional gate-level flows.

The cost of power-saving techniques
When designing an SoC or a multicore platform, there are a lot of architecture decisions that are clearly set before RTL is written and which must be considered in a design-for-power methodology, said Pete Hardee, director of solutions marketing at Cadence. “There are a lot of decisions that affect power that are already set in concrete before you are coding in RTL. Usually when a device like this is being designed, there is a lot of reuse going on. The rule of thumb is typically 70% to 80% re-use and 20% to 30% new design.”

There are some blocks that are being re-used that have already been characterized for power or known from previous use, or that can be recalculated if moving a design into a new node.

“What needs looking at is the cost of implementing the power saving techniques,” said Hardee. “We’ve got various techniques going on—power shut-off, including state retention. Some people call that power gating. What we are doing is splitting the design into various power domains and doing different things with those power domains, either switching them off and working out which registers need to hold value to come back on quicker or running from multiple supply voltages. There is a cost in implementing all of those techniques. Every time I split something into power domains, for every signal that crosses a power domain that I’m switching differently I need either isolation or level shifters or both. For every register that I need to hold a value during power off, I need a state retention register in there, which is roughly double the size of a regular register. Also, in normal operating mode, it takes greater power, there’s greater leakage due to the state retention registers compared with the normal registers. All of these decisions — how many power domains I’m splitting up into, how I’m switching those power domains — they have a cost and that cost can be assessed before RTL.”

Source: Cadence

Today, those costs are typically tracked by the power architect in a large Excel spreadsheet that contains all of the components that will be re-used in the platform. The architect tries to work out how many components need to be added for the power scheme in the new design, which are generally pre-RTL decisions. Of course, in a spreadsheet it is very difficult to work out for all of the combinations of domains being on and off as to what’s happening.

In lieu of the spreadsheet approach, there are a small number of commercial modeling frameworks available today from Cadence, Mentor and Docea Power, a French start-up.
This is also where things get interesting. A modeling framework captures the static power techniques, which need to be balanced with some kind of dynamic idea.

Above RTL that means simulation, Hardee pointed out. “This is where virtual platforms come into play and allow engineering teams to start exploring with running some software with a model of the platform and start to bring in a time element…the closer to the real operating environment, the better idea the simulation can give for whether the power architecture is sufficient or if changes need to be made to the power specification. Above RTL, I think most people’s goal is to relatively rank various candidate architectures. It’s a relative thing. What you are really trying to do as a power architect is at least get the ranking right to know if one architecture is better or worse compared with another.”

Obviously, the RTL tools can’t be abandoned because that’s where a lot of the detail design is done.

“It’s where most of the microarchitectures for the blocks being implemented are decided during the RTL coding phase,” Hardee said. “High-level synthesis is interesting because it can allow you to do better exploration of those microarchitectures before RTL. As soon as you start coding, you fix the microarchitectures. But RTL is still a very critical area. It’s really the first abstraction level that you can accurately verify the power architecture.”

The future of DFP
Looking at design-for-power from a high level, Cary Chin, director of technical marketing for low power solutions at Synopsys observed, “Advanced low-power optimization has come a long way in the past few years but clearly, we’re not done. There is much more to be done at a high level, looking at new methodologies and better ways of optimizing for power. It’s been a theory of mine that as we go forward, power becomes one of these things that we are designing around and it’s really something that is going to be a requirement and one of the fundamental keys to design going forward. I think we’ll see methodologies evolve even more going forward where, from the very high level, one of the main things you’ll want to consider is going to be power all the way through the design flow.”

And in future designs, the alternatives may be much less attractive.

By Ann Steffora Mutschler
Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design techniques are utilized?

As Massimo Sivilotti, chief scientist at Tanner EDA pointed out, “These questions are complex, and there is no universally accepted answer to any of them.”

In general though, low-power designs involve both architectural and circuit design components and issues such as sub-threshold leakage currents, upsets due to substrate- and power-supply-coupled noise. Device parameter variations due to statistical process factors for deep-submicron devices become more acute as power levels fall. As such, state-of-the-art device models, up-to-date model parameters from foundries, and data-driven noise calculations become essential.

From Intel Corp.’s perspective reliability is more an attribute of the nature (or use model) of an application – whether it is low power or not. “For example, a low power smart phone application would define ‘reliability,’ both from device and user perspective, very differently than an equally low-power battery-powered medical device that administers medicines to critically ill patients,” said Pranav Mehta, chief technologist for Intel’s Embedded Communications Group. “Having said that, low-power designs do offer special challenges to designers. Balancing the need to lower the operating voltage to reduce power while trying to achieve competitive performance provides significant challenges in terms of process technology recipe, architectural tradeoffs, as well as design tool chain and methodology selections.”

The core of the problem
Diving down, technically speaking, Srikanth Jadcherla, group director of R&D for Synopsys Inc.’s Verification Group, noted that reliability in low-power design goes back to the fundamentals – avoiding permanent or temporary dysfunction of the device due to physical effects such as electromigration, self heating and rail/signal integrity failures. While these might have been overlooked before, the causes of the failures or in some cases the magnitude of certain phenomena can no longer be ignored.

“Some of these cause IC designers to adopt a certain power mitigation (or current mitigation) technique,” Jadcherla said. “Some of these are caused by what is done for power reduction. So, it cuts both ways. Specifically, as the industry heads into nanometer designs, current magnitudes are rising while wire cross sections are shrinking – increasing current density dramatically. This puts a lot more stress on the wires from an electromigration point of view and also from a heating standpoint. Ditto for leakage, which increases the average amount of current flowing through the wires irrespective of activity. This issue didn’t exist before. To combat these issues, IC designers have adopted aggressive techniques such as power gating and voltage scaling to opportunistically reduce the current draw.”

Docea Power, based in Moirans, France, looks at reliability in low-power design from the system perspective. CEO and co-founder Ghislain Kaiser said high power consumption affects reliability of electronic systems due to thermal dissipation and electrical issues induced by high-density currents.

There are multiple reliability issues related to high temperature including physical stress on the package, especially on die-attached material; transistor and interconnect deterioration; alteration of transistor switching time, hence timing hazards; thermal runaway risk when leakage current becomes significant; and high temperature that may require cooling systems such as a fan, which increase the risk of reliability if a failure occurs in the cooling system.

But, Kaiser noted, high-density currents alter electrical properties by causing such issues as electromigration of metals atoms along conductors; crosstalk, which degrades signal integrity; or a voltage drop along resistive wires. “This last point is particularly important when a low-power approach like voltage scaling is used. Lowering voltage allows you to reduce power consumption, but it increases the risk of going below the working point of transistors. The design work involves correctly sizing the voltage margin regarding the use cases,” he said.

Jameel Hussein, Technical Marketing Manager for Xilinx Inc.’s Power and Configuration Solutions reiterated that consideration must be given to thermal management at both the component and system levels to ensure that all devices are operating within their specified temperature range and to maximize overall system reliability.

“The device’s operating (junction) temperature is a function of the device power, its ability to transfer the resultant heat to the surrounding environment via the component packaging, and the ambient temperature of the system,” Hussein said. “Reducing the device power consumption, therefore, has two significant benefits. First, it lowers the system cost by enabling the use of less expensive thermal solutions to keep the device in its intended operating range. Second, reduced power means lower operating temperatures, which directly translates into improved component and system reliability.”

Added Hussein: “The temperature is a function of the power so if you can lower the power, you can lower the temperature of the actual device and its surrounding parts. Equation 2 is based on the acceleration factors between the two different devices in this example. If it is a difference of 10 degrees, in junction temperature, the equation shows that a device that runs 10 degrees less on a junction temperature will last twice as long as one running 10 degrees hotter,” Hussein explained.

Actel, which has been the low-power leader in the FPGA space, has focused part of its reliability argument around on-chip memory. Unlike other FPGAs, Actel’s use flash memory, which is less susceptible to single-event upsets caused by either terrestrial or cosmic radiation. And while that’s of obvious importance in aerospace applications, it’s also considered important in critical functions such as automobile powertrains because upsets often affect multiple bits at increased densities. That may be enough to shut down a chip permanently.

There are workarounds in circuitry and software for these kinds of problems, but they add more area to the circuitry and raise the overall power consumption to make sure there are no problems.

New techniques impact low-power design
With designs today utilizing techniques such as power modeling and complete coverage verification there are pros and cons as to the impact on the design.