By Ed Sperling
Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry.

To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with later in the design process, and at 28nm it has become an essential part of the architecture. But as battery life, mobility, and energy costs even for plugged-in devices become overriding concerns, power now needs to be considered at full system level, which could mean everything from a rack of servers to an automobile.

Much of this is being driven from the chip level, and in the software that manages chips and interactions between chips. There are at least a half dozen new standards efforts under way or on the drawing board. Most heavily leverage the expertise of chipmaker and where they have encountered or expect to encounter pain in designs, most notably in stacked die or in planar SoCs below 20nm, or from tools vendors that have gained expertise in a specific area.

Si2 currently has one standard in legal review for system-level power modeling. The standard is called “atomic” power modeling, based on the assumption that the model cannot be broken down into smaller pieces, although it can be used at various levels of abstraction.

Also in the works is a standard for co-design, which is one of the most difficult challenges facing design today. While hardware engineers are well versed in how to build an energy-efficient chip, that engineering effort can be wasted if the software running on an SoC isn’t energy-efficient, as well.

“The first step is to get there with the architectural ESL level,” said Steve Schulz, president and CEO of Si2. “Then, we will look at how the software runs and develop a bridge. You will never get the software community to adopt the hardware approach to design. That community is 20 to 30 times larger than hardware engineers and they have their own tool flows. We have to think about a minimally intrusive solution. We’ve called it a bridge to the software world, and if it’s not intrusive then the software teams will use it. Most of them will never understand concurrency and how to get to a GDS II stream, but there are characteristics that are reasonable proxies of the details. You don’t simulate all the code, but you do generate enough discrete choices so everyone can get on the right track for power.”

A first step in that direction is finding data objects that can be passed back and forth between the software and hardware teams. From there a power model will need to be created across both. The power-flow group within Si2 has been reactivated to develop a source for the power model. “The focus this year will be hardware,” said Schulz. “In 2013 we will turn our attention to understand the data objects stored.”

That puts the likely adoption timeframe a of a co-design framework for power in the 2015 time frame—roughly at the 14nm process node and at a time when 2.5D stacking is expected to be mainstream and 3D stacking will become more commonplace.

Stacking effects
“There are two new requirements for design,” said Andrew Yang, president of Apache Design. “The first is a 3D IC flow. The second is an RTL-to-gate power methodology.”

Included in the 3D requirements is the need for multi-die thermal and stress analysis. Yang said the key is the amount of current a design can sustain without failure over time, and it gets worse at advanced nodes and sometimes in stacked configurations because wire handling capability is decreasing, power density is increasing, and electromigration is increasing.

“This can be a safety issue,” he said. “You need to make sure the metal topology is handled correctly. Electromigration is affected by heat. The hotter it gets, the less current a metal wire can sustain. The electromigration rules are increasing, which is why GlobalFoundries, Intel and TSMC are all coming up with complex electromigration rules.”

Front to back, back to front
Being able to get a chip out the door at all is a challenge, which is why there are more standards being dictated from the foundries these days. In addition to process variation, continually shrinking geometries is making it harder to obtain adequate yields as quickly as in the past. That has led to more rules for place and route, test, IP, and layered across all of those is power.

“We’re seeing it in the available sizes, speeds, memory and logic cell sizes,” said Chris Rowen, CTO at Tensilica. “That’s what we target—area, power and process compatibilities. Whether that’s stacked or conventional die is affected only subtly. But with die stacking you will see significantly higher bandwidth and less latency, which will have an effect on modeling of the system. It’s not a qualitative change, but it is a quantitative change. It won’t change how one DSP communicates with another, but it will change how DSPs communicate with memory.”

How much of that will be standards promoted by standards bodies versus de facto standards from the largest foundries remains is unknown. Also missing are good open standards for on-chip debug and trace, said Rowen.

ESL standards
One of the most glaring holes in all of this is at the ESL level, where standards for power models are non-existent. While this isn’t a big problem in a single vertically integrated company, it’s a huge problem in a disaggregated supply chain where various companies work on designs—something that will become even more pronounced in stacked die where subsystems at different process geometries need to be integrated with other subsystems.

“What’s missing is something that allows companies to exchange power models, especially for IP-based designs” said Ghislain Kaiser, CEO of Docea Power. “In an ideal flow you would be able to take the IP from the IP suppliers and put together a power model and assess the power impact on the underlying hardware. But you also need to have interoperability between suppliers and customers that goes beyond the semiconductor level. It has to be optimized at each level—the SoC, the chip set, the PCB and above. So there won’t be only one number.”

The accuracy of those power models also will shift throughout the design. At the beginning a model may be only 40% accurate, but at the end it may need to be accurate to plus or minus 5%, Kaiser said.

Other pieces are missing, as well. Kiran Vittal, senior director of product marketing at Atrenta. “Right now, when a designer uses memory they don’t realize the code they are writing is not optimized for power. When you read memory you get a redundant read. The controller code isn’t optimized for memory. And all of that has to be networked, because you may have as many as 2,000 memories in a design. If you do it right you can save about 20% of the memories and the power needed to run them.”

To show just how bad this can get, a large systems house was designing a chip was required to give an early indication of its power budget to the OEM. The OEM used that estimate for calculating its own power budget and came up with a spreadsheet that represented the total design. The problem was that the spreadsheet ultimately was off by 100% in its power estimate, which in turn caused problems with the final device and greatly increased the amount of time it took to successfully bring a product to market.

“A lot of the ESL tools today know performance and area, but they don’t have a clue about power,” said Vittal. “This is fertile ground for innovation.”

Low-Power Engineering discusses what’s missing from the ESL tool chain with Ghislain Kaiser, CEO of Docea Power.

By Ed Sperling
Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die.

While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—they can be very different from a design standpoint. Each can be affected by the other, and each needs to be modeled as part of a holistic design, but system power budgets may be too high to be acceptable and still low enough not to cause thermal issues. Nevertheless, the number of power issues that can result from stacking die can be far greater simply because there are more possible permutations, and so far there is little information about how to solve this.

The reasons for the dearth of knowledge in this area stem partly from the fact that some of these devices are just now being built—the best knowledge about design always comes from experience and history—and partly because power can vary greatly from one system to the next, from one user to another, and sometimes from one chip to another even within the same design. In a stacked die, all of these come into play in the same package, often with unexpected results. That makes it difficult to model power accurately enough up front, and equally difficult to deal with as the design progresses.

“We’re seeing some complex power management schemes emerging,” said Mike Gianfagna, vice president of marketing at Atrenta. “The problem is that if you have an error, you automatically generate incorrect power management circuitry. The opportunity is to enhance much more complex verification schemes to deal with this.”

He noted that many large chipmakers have their own homegrown version of power modeling, but it will take time—and standards—before there is a systematic way of dealing with it.

What needs to be addressed where
There are several distinct points where power needs to be addressed in a design. The first is at the architectural level, where modeling will be inaccurate. But it can be accurate enough to get an idea of which IP, including processor cores, to choose, which memory, various interconnect schemes, and I/O preferences. Each of those has a different effect on power, and together they have a cumulative effect.

“As you go down in the design flow you refine the power models and the software,” said Ghislain Kaiser, CEO of Docea Power. “But your accuracy depends heavily on the IP. For some IP, if you have an error of more than 20%, it will impact decisions later on. For IP that is small and not power-hungry, an error of that size may not cause any problems. But you do have to think about the global impact of the power, especially in a stacked die.”

While this is complicated enough in a planar SoC, it becomes even more complex in a stacked die because not all of the pieces are necessarily built at the same time. In addition, IP blocks and even entire subsystems can interact in unforeseen ways, sometimes decreasing power consumption as with Wide I/O, and at other times generating more power than anticipated because of unexpected proximity and other physical effects such as increased temperature.

“There are lots of things going on,” said Andrew Yang, president of Apache Design. “The voltage is fluctuating, so you’ve got on-chip voltage regulators to stabilize the power supply and back biasing to further reduce leakage power. At 20nm, reliability is becoming a key driver. Electromigration and electrostatic discharge are now mandatory for robust volume manufacturing. And we’re not just dealing with IR drop. In a platform solution, IR drop is one small item. You have to consider a full-chip power model.”

No simple answers
In addition to understanding power throughout the flow, Apache has been a strong advocate of understanding power over time, a necessary perspective that further complicates the design process with a fourth dimension. Power can be affected by a number of factors over time—even small increments of time from one die to the next.

“Die-to-die interactions are a form of variability,” said Riko Radojcic, director of design for silicon initiatives at Qualcomm. “You need a timer that understands thermal gradients and the impact of thermal gradients on time. There is a gap there right now.”

How to solve this problem is a big unknown, particularly when it comes to power. Power models and power numbers are dynamic rather than fixed, needing adjustments and tweaking throughout the life of the design and even beyond.

The general consensus is that none of this will ever be automated beyond a certain point, and no single tool will handle all of the power issues—even in 2D designs. In 2.5D and 3D, the number of options and possible interactions increases non-linearly. As the industry progresses into the next dimension, one of the biggest challenges will just be grasping all of the possibilities—and all of the subsequent effects that go along with those options.

By Ed Sperling
The move toward stacking of die has always been a series of disconnected pieces and vague promises for the future, but in the past few months the scenario has changed radically—and so has the commentary.

All three of the Big Three EDA vendors now have at least some of the pieces in place for 2.5D stacking and are working on a full 3D flow. Two of the biggest FPGA vendors, Altera and Xilinx, have rolled out 2.5D prototypes. The big foundries have developed processes and interposer technology. And IP vendors are beginning to talk about how IP will have to be characterized to work effectively in stacked-die configurations.

Unanimous vote of confidence
Possibly the most dramatic change has been at Synopsys, which has been vague about stacked die for the past couple of years as it tried to sort out where the issues were and where the opportunities will be.

“For some time, the situation has been very foggy,” said Marco Casale-Rossi, product marketing manager for implementation platforms at Synopsys. “We decided to let things settle to understand the main directions, and believe that over the last 18 months we have understood where mainstream will be—2.5D with an interposer. It will be a number of die, side by side, communicating through an interposer and with the outside world through a TSV.”

Synopsys has decided to focus in three areas: a complete solution for implementation and verification; an evolutionary 2.5D to 3D flow that builds on what already exists; and an R&D commitment with customers and research groups to solve whatever problems may come up in the future.

“Extraction will be very important,” Casale-Rossi said. “We need to take into account a number of new elements such as microbumps, TSVs and interposers. And historically, EDA tools have been designed to deal with one process technology at a time. Now we’ve got bricks manufactured using different process technologies and the rules are different depending on the die.”

EDA’s next big thing
Synopsys isn’t alone in trying to predict where the pain points and the opportunities will be. Both Cadence and Mentor Graphics threw their support behind stacked die over the past couple of years, and Cadence has been working on system-in-package since the beginning of the millennium. So far it appears that the opportunity is large enough and broad enough that there isn’t much overlap.

Cadence has built its 2.5D suite from its SiP tools, which were introduced in in 2007 at a time when the market was still focused on planar ASIC solutions. At that point, the company was divided over whether stacked die would really be an opportunity going forward. There is far less doubt these days that it was the right choice.

“The big question as we got into 3D was whether we build separate tools or use the same tools,” said Samta Bansal, senior product marketing for SoC Realization at Cadence. “We did need new layout tools because of the new electrical features—TSVs and microbumps. The analysis tools also have to be able to comprehend the new constraints, which are thermal and mechanical. And we needed new models and tools with respect to microbumps, and had to make sure the current tools understand the new dimensions.”

She said TSVs are similar to vias, but still different enough to require changes in the tools. And floor-planning requires understanding of placement in a stack to optimize behavior. But she noted that what customers discovered they really needed were tools for packaging.

“Customers that are developing 2.5D are looking at this one of two ways,” she said. “One is a package-driven flow, where the interposer is an extension of the package substrate. The other is an IC-driven flow, where as you go along you have more TSVs and more IC-centric routers. But for both of them, 3D stacking is a combination of digital, custom (analog/mixed signal) and the package.”

Mentor Graphics likewise has been extremely active in 2.5D, with a long-range view of 3D stacking, focusing in particular on both test and manufacturability.

“Several factors need to be addressed,” said Steve Pateras, product marketing director for Mentor Graphics’ silicon test products. “One is known good die. How good is the testing before you put chips in a package? Most times you test chips after they’re already in the package, but with 2.5D and 3D the yield goes down as you increase the number of die.”

A second issue involves I/O testing—or more accurately, the lack of testing—which takes on new meaning in a stacked die. In stacked die, it’s imperative to test the I/O before the die are packaged because many times it will not be testable after they’re already in the package.

Pateras said one of the approaches being talked about is wafer on wafer stacking to reduce costs, but that makes it particularly hard to test. He said the better approach is die-to-wafer stacking, using a base wafer with everything else stacked on top for greater control and better yield. But that also creates another problem.

“When you stack heterogeneous die in a stack, there is no standard for communication between the die,” he noted. “We’ve solved one problem, which is memory stacked on logic. But we need to develop a 3D test standard and standards for embedded self test.”

On the manufacturing side, Mentor has modified its DFM tools for 2.5D and 3D verification. And most experts believe existing ESL models can be relatively easily tweaked.

What’s still needed
It’s easy to forget that 2.5D and 3D are evolutionary steps with possibly game-changing impacts. While some EDA tools have always been offered well in advance of the mainstream, they are typically behind the chip design teams working at the leading edge of Moore’s Law. At 20nm and beyond, the cost of making chips has become so enormous that leading-edge companies are building upward. And as they do so, they are finding some pieces are missing that will need to be filled in.

“The first thing that’s missing involves the temperature issue,” said Ghislain Kaiser, CEO of Docea Power. “When you stack die together you’re putting more power into a package, whether it’s 2.5D or 3D. You have to manage that. Many times there is no dissipation problem, but you need to have tools to make sure. You need to be able to analyze the dynamic power profile, and right now it’s impossible to make a link between the software and dissipation when you run actual software on the chip. The best you can do is a simple profile.”

One of the great benefits of stacked die, in addition to not having to move analog designs to the next process node, is increased flexibility and options for designers. Teams can stack different memories in different places and they can move functionality from one die to another to improve performance or lower power or both.

“With that freedom you need to do more exploration,” said Kaiser. “But you may have too many degrees of freedom. You need to be able to optimize different chips along price, performance and power. And you need more accuracy. The gate-level tools are not 100% accurate.”

That’s easier said than done, however. There are no standards in the IP world that would allow an accurate comparison between one piece of IP and another. Frequently they are not even measured the same way by different vendors. Moreover, they can vary significantly with different usage scenarios.

That’s typically where standards fit in. Cadence’s Bansal said the foundation to enable 2.5D and 3D is clear, but there needs to be a seamless and consistent way to integrate digital, AMS and the package. “If the routing is not optimized, for example, you may end up with several layers of interposer. That will make the chip much more expensive.”

By Ed Sperling
Talk with any large systems vendor about power modeling and, with very few exceptions, they’re still using a mix of spreadsheets and lower-level models—no matter how far along they are in ESL adoption and in modeling other parts of an IC.

Power has crept up on even the biggest companies, which have never really figured out how to implement it into their design flows. For one thing, the tools are still evolving. But so is an understanding of how to effectively deal with it.

Smaller companies, meanwhile, are just getting a taste of how challenging this can be as 65nm and 40nm become mainstream process nodes. Density, shrinkage, and competitive requirements have made power a critical issue, and while many are used to dealing with power gating and multiple power domains, the complexity of multiple voltage islands, multiple states between on and off and different strategies for maximizing energy efficiency add a mind-boggling array of choices and complexity to designs.

It’s well known among companies in the mobile IC market—those that have the greatest history of dealing with power issues—that power has to be dealt with at the architectural level. What is less well known is that it requires adjustments throughout the design cycle, and the tools even the most advanced companies are using are a direct reflection of that.

“The only reliable level for measuring power has been the gate level,” said Barry Pangrle, a solutions architect for low-power design at Mentor Graphics. “Above that it’s a relative measure. But to take advantage of the 80% impact on power that you can have at the architectural level you want to take advantage of everything you can. For that most customers are still using spreadsheets.”

This approach has worked fine so far. Modeling can be done on spreadsheets as well as being automated. The problem is that it can’t be updated easily, and there’s no way of testing that the numbers are realistic as the design progresses. “You really want a sanity check throughout the flow,” Pangrle noted. “You estimated the block and you need to make sure it’s right.”

What if…
The lack of automation causes other problems, as well. Because most flows are automated to some extent, being able to update various parts throughout the design process are critical. Virtual models, for example, allow changes in software to be reflected in hardware. But updating models manually with a spreadsheet is cumbersome, made worse by the fact that the amount of data that needs to be added and updated on a regular basis is ballooning. Some libraries are now measured in terabytes.

“At 28nm and 20nm, you’ve got to start dealing with electromigration and other effects caused by heat,” said Aveek Sarkar, vice president of product engineering and support at Apache Design. “You need to create models to capture all of these effects, but these models also have to be consistent and they have to replicate what’s really going on at the electrical or mechanical level. You need to understand the parasitics using linear and non-linear models, and then abstract from there.”

Getting those models right is no simple task. And what happens when an IP block is replaced with another IP block, or a signal is rerouted from one memory to another?

“You need chip models that create power models,” said Sarkar. “That’s one of the top integration focus areas according to feedback we’ve received from system design houses.”

Power everywhere
But is one power model really enough? Power is a global issue, and it affects everything from the software that’s written to a virtual platform to the IP blocks that are being integrated into a design. There are two diverging issues. One is that the classic divide-and-conquer strategy is essential for being able to design and verify complex chips. The second is that power budgets need to be fixed, and they can be affected by everything from those individual blocks to the way they are integrated and used.

“Power modeling is key,” said Philippe Magarshack, group vice president for technology R&D at STMicroelectronics. “Otherwise we will never be able to tackle designs going forward.”

He noted that ST has been using dynamic voltage scaling for several process nodes, along with dynamic voltage frequency scaling. Power islands are well understood, as well. But automating the power remains a challenge.

“There are no standards for this,” noted Ghislain Kaiser, CEO of Docea Power. “This is a problem because we need a common way to capture this data and have the same kind of modeling. The most important thing is to get power models into the design flow.”

And because power generates heat, primarily through leakage, thermal models need to be developed in sync with those power models—something that will become critical as stacking of die becomes more mainstream over the next few years.

But internally developed spreadsheets have reached their limit for adding new data. There literally are no rows and columns left for more data. And existing TLM 2.0 models are too far removed from the power/heat to be useful.

“An accurate power model should have no more than a 5% error,” said Kaiser. “That way it can be used to speed up the debug of power management software.”

Power continuity
Another reason for automating power goes well beyond just the technical capabilities of the tools. It has to do with the way designs are created. Designs have become so complex that even the best and brightest engineers can no longer comprehend the whole design.

“What this means is that you may have an issue in power and not even know about it,” said Qi Wang, technical marketing group director for low power and mixed signal at Cadence. “Verification will become a very big challenge in the future. We’re used to doing functional verification. But power verification to measure power consumption needs to be considered, as well.”

In addition, he said that each step along the way of a design, starting with placement, clock tree and routing, need to be optimized for power. That, in turn, needs to be reflected back into other models that have been developed because the changes can affect all parts of the design.

By Ed Sperling
There are many ways to measure power and heat in an IC, and each one of them adds tremendous value to a design. But there are still holes, and those holes are just beginning to get filled.

Power and heat have emerged as two of the most persistent problems in advanced designs, and there is no single or simple way to tackle either of them. Nevertheless, there is at least progress on this front.

“Power is a side of complexity that has many, many dimensions,” said Aart de Geus, chairman and CEO of Synopsys. “We have multiple power domains and we now have states between on and off. How do you deal with that with ones and zeros?”

At the highest level, high-level synthesis can be used to provide generalizations about whether one processor versus another, or one piece of IP versus another will save power. The challenge there is to link those HLS models with other models to make them useful. This has been an ongoing challenge for startups such as Calypto and Forte Design Systems, as well as Synopsys and Cadence. (Mentor Graphics spun off its Catapult C platform to Calypto last year.)

At the lowest level, starting with RTL and even down to the gate, measurements are extremely accurate and useful. The problem is that once RTL code is written, it’s more difficult to change. Providing that kind of information early, and in context, has been a major challenge. Apache Design has created an RTL Power model, for example, as well as an RTL power flow and a chip-package-system model and flow to extract that information early enough to include it in the RTL.

The big missing piece, however, has been even earlier in the design process. What happens, for example, if a processor from one vendor is substituted for a processor from another vendor? Or what if signal traffic is routed one way in a design versus another? These are important tradeoffs at the architectural level, and there has been only scattered progress in this area. That’s partly because most of the complex thermal and power modeling for advanced is still being done with spreadsheets rather than with automation tools.

Docea Power jumped into the market this week with what should be an interesting first step. Its new AceThermalModeler software is aimed at architectural-level exploration and analysis for heat and power. The focus is on early system floorplanning or partitioning, system packaging, integration architectures and power management policies. It’s a certainty there will be other entrants into this space of the next year or two. All of the major EDA companies and their customers have been talking about the need for this kind of technology since designs reached 40nm.

But Docea CEO Ghislain Kaiser said the spreadsheets literally have run out of room at advanced nodes. They cannot handle any more data. What’s needed now is a way of raising the level of abstraction with accuracy, and he says there is an opportunity between the complex algorithmic approaches used for signoff and the packaging data sheets that are too far from reality. It remains to be seen just how quickly this market will ramp up as a result of that, because the next challenge will be to integrate this kind of information—all of it, from the high level to the pathfinding architectural models—into existing flows. That includes companies designing chips, as well as the ESL flows that are created by the Big Three EDA vendors, and the modeling standards groups such as OSCI, which developed TLM 2.0.

All of this will take time, of course. Standards groups move cautiously and large companies don’t make rapid changes to flows that work. Still, the need for more analysis that can be integrated throughout the design process is clearly needed.

By Ann Steffora Mutschler
It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2.

But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most efficient way through the design flow.

If power is not implemented in the most efficient way, meaning if it isn’t optimized and reduced to the bare minimum, then what’s the purpose of designing it?

“Whatever the power ends up becoming, it is what it is, and in many traditional designs this has been the approach,” said Shabtay Matalon, ESL market development manager at Mentor Graphics. “There wasn’t in mind an objective to say, ‘Let me design it such that the power will be minimized.’ The power conservation and reducing the power is the primary objective.”

Most tools that address power today begin at the RTL, but there is an increasing consensus that this may not be early enough. “The percentage of gates or transistors in a design that can be exercised at the same time is shrinking and shrinking,” said Matalon. “On one hand we get this huge capacity to put billions of transistors on silicon. On the other hand, the power is [holding back] the percentage of the resources that we put on the chip that can be exercised. There is a need for this intelligence that is usually in the software. I’m sorry to offend anybody on the hardware side, but the intelligence is really in the software that is running the application—the software that understands the application context to play a role in reducing the power in the environment. Obviously, the hardware needs to be below the infrastructure and that’s why RTL might be too late.”

Design-for-power is not just analysis at the RTL. It is design for optimizing power. Some define a design-for-power methodology as having a gate-level representation, running some analysis, then predicting the power. Predicting the power accurately at RTL is highly questionable, though, unless you really run the device in the same operating conditions that you will actually use it.

“But there is not even a doubt that when you are doing this analysis at RTL down, that you lost your possibility to optimize,” said Matalon. “Design-for-power is not just analysis. It is the reduction of power.”

Larry Hudepohl, VP of hardware engineering at MIPS, agrees. He said the importance of power as a design metric is one of the first and foremost criteria, not just an afterthought when putting the final chip together. “In the same way that the analysis of performance has moved much earlier in the design flow in advance of RTL, I see that same trend happening on the power side too. Earlier estimation of power, especially in a complex SoC where there are multiple devices driving multiple complex interfaces so the modeling of that—the power dissipation characteristics of the full chip under different operating conditions, under different power management modes—can really be assisted by modeling in a stage earlier than RTL.”

On the other hand, Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions, stressed that RTL is indeed early enough for a DFP (design-for-power) methodology. “Design for power must be done at the design level of abstraction, and for hardware design this means RTL. Anything after RTL is either automatic optimization (e.g. synthesis) or implementation, which in the case of the digital flow is also automated (i.e. place and route).”

Apache’s view is that a key part of a DFP methodology is power debug and power efficiency analysis, and the benefit of doing these at the RTL is a significant improvement in productivity (and corresponding turnaround time reduction) compared to traditional gate-level flows.

The cost of power-saving techniques
When designing an SoC or a multicore platform, there are a lot of architecture decisions that are clearly set before RTL is written and which must be considered in a design-for-power methodology, said Pete Hardee, director of solutions marketing at Cadence. “There are a lot of decisions that affect power that are already set in concrete before you are coding in RTL. Usually when a device like this is being designed, there is a lot of reuse going on. The rule of thumb is typically 70% to 80% re-use and 20% to 30% new design.”

There are some blocks that are being re-used that have already been characterized for power or known from previous use, or that can be recalculated if moving a design into a new node.

“What needs looking at is the cost of implementing the power saving techniques,” said Hardee. “We’ve got various techniques going on—power shut-off, including state retention. Some people call that power gating. What we are doing is splitting the design into various power domains and doing different things with those power domains, either switching them off and working out which registers need to hold value to come back on quicker or running from multiple supply voltages. There is a cost in implementing all of those techniques. Every time I split something into power domains, for every signal that crosses a power domain that I’m switching differently I need either isolation or level shifters or both. For every register that I need to hold a value during power off, I need a state retention register in there, which is roughly double the size of a regular register. Also, in normal operating mode, it takes greater power, there’s greater leakage due to the state retention registers compared with the normal registers. All of these decisions — how many power domains I’m splitting up into, how I’m switching those power domains — they have a cost and that cost can be assessed before RTL.”

Today, those costs are typically tracked by the power architect in a large Excel spreadsheet that contains all of the components that will be re-used in the platform. The architect tries to work out how many components need to be added for the power scheme in the new design, which are generally pre-RTL decisions. Of course, in a spreadsheet it is very difficult to work out for all of the combinations of domains being on and off as to what’s happening.

In lieu of the spreadsheet approach, there are a small number of commercial modeling frameworks available today from Cadence, Mentor and Docea Power, a French start-up.
This is also where things get interesting. A modeling framework captures the static power techniques, which need to be balanced with some kind of dynamic idea.

Above RTL that means simulation, Hardee pointed out. “This is where virtual platforms come into play and allow engineering teams to start exploring with running some software with a model of the platform and start to bring in a time element…the closer to the real operating environment, the better idea the simulation can give for whether the power architecture is sufficient or if changes need to be made to the power specification. Above RTL, I think most people’s goal is to relatively rank various candidate architectures. It’s a relative thing. What you are really trying to do as a power architect is at least get the ranking right to know if one architecture is better or worse compared with another.”

Obviously, the RTL tools can’t be abandoned because that’s where a lot of the detail design is done.

“It’s where most of the microarchitectures for the blocks being implemented are decided during the RTL coding phase,” Hardee said. “High-level synthesis is interesting because it can allow you to do better exploration of those microarchitectures before RTL. As soon as you start coding, you fix the microarchitectures. But RTL is still a very critical area. It’s really the first abstraction level that you can accurately verify the power architecture.”

The future of DFP
Looking at design-for-power from a high level, Cary Chin, director of technical marketing for low power solutions at Synopsys observed, “Advanced low-power optimization has come a long way in the past few years but clearly, we’re not done. There is much more to be done at a high level, looking at new methodologies and better ways of optimizing for power. It’s been a theory of mine that as we go forward, power becomes one of these things that we are designing around and it’s really something that is going to be a requirement and one of the fundamental keys to design going forward. I think we’ll see methodologies evolve even more going forward where, from the very high level, one of the main things you’ll want to consider is going to be power all the way through the design flow.”

And in future designs, the alternatives may be much less attractive.

By Ann Steffora Mutschler
Having a clear understanding of what reliability means for a particular low-power application can make a significant difference when it comes to communicating with engineering team members and customers. Is reliability simply a question of how long a device can run without errors? And what happens to reliability when power modeling, verification and other design techniques are utilized?

As Massimo Sivilotti, chief scientist at Tanner EDA pointed out, “These questions are complex, and there is no universally accepted answer to any of them.”

In general though, low-power designs involve both architectural and circuit design components and issues such as sub-threshold leakage currents, upsets due to substrate- and power-supply-coupled noise. Device parameter variations due to statistical process factors for deep-submicron devices become more acute as power levels fall. As such, state-of-the-art device models, up-to-date model parameters from foundries, and data-driven noise calculations become essential.

From Intel Corp.’s perspective reliability is more an attribute of the nature (or use model) of an application – whether it is low power or not. “For example, a low power smart phone application would define ‘reliability,’ both from device and user perspective, very differently than an equally low-power battery-powered medical device that administers medicines to critically ill patients,” said Pranav Mehta, chief technologist for Intel’s Embedded Communications Group. “Having said that, low-power designs do offer special challenges to designers. Balancing the need to lower the operating voltage to reduce power while trying to achieve competitive performance provides significant challenges in terms of process technology recipe, architectural tradeoffs, as well as design tool chain and methodology selections.”

The core of the problem
Diving down, technically speaking, Srikanth Jadcherla, group director of R&D for Synopsys Inc.’s Verification Group, noted that reliability in low-power design goes back to the fundamentals – avoiding permanent or temporary dysfunction of the device due to physical effects such as electromigration, self heating and rail/signal integrity failures. While these might have been overlooked before, the causes of the failures or in some cases the magnitude of certain phenomena can no longer be ignored.

“Some of these cause IC designers to adopt a certain power mitigation (or current mitigation) technique,” Jadcherla said. “Some of these are caused by what is done for power reduction. So, it cuts both ways. Specifically, as the industry heads into nanometer designs, current magnitudes are rising while wire cross sections are shrinking – increasing current density dramatically. This puts a lot more stress on the wires from an electromigration point of view and also from a heating standpoint. Ditto for leakage, which increases the average amount of current flowing through the wires irrespective of activity. This issue didn’t exist before. To combat these issues, IC designers have adopted aggressive techniques such as power gating and voltage scaling to opportunistically reduce the current draw.”

Docea Power, based in Moirans, France, looks at reliability in low-power design from the system perspective. CEO and co-founder Ghislain Kaiser said high power consumption affects reliability of electronic systems due to thermal dissipation and electrical issues induced by high-density currents.

There are multiple reliability issues related to high temperature including physical stress on the package, especially on die-attached material; transistor and interconnect deterioration; alteration of transistor switching time, hence timing hazards; thermal runaway risk when leakage current becomes significant; and high temperature that may require cooling systems such as a fan, which increase the risk of reliability if a failure occurs in the cooling system.

But, Kaiser noted, high-density currents alter electrical properties by causing such issues as electromigration of metals atoms along conductors; crosstalk, which degrades signal integrity; or a voltage drop along resistive wires. “This last point is particularly important when a low-power approach like voltage scaling is used. Lowering voltage allows you to reduce power consumption, but it increases the risk of going below the working point of transistors. The design work involves correctly sizing the voltage margin regarding the use cases,” he said.

Jameel Hussein, Technical Marketing Manager for Xilinx Inc.’s Power and Configuration Solutions reiterated that consideration must be given to thermal management at both the component and system levels to ensure that all devices are operating within their specified temperature range and to maximize overall system reliability.

“The device’s operating (junction) temperature is a function of the device power, its ability to transfer the resultant heat to the surrounding environment via the component packaging, and the ambient temperature of the system,” Hussein said. “Reducing the device power consumption, therefore, has two significant benefits. First, it lowers the system cost by enabling the use of less expensive thermal solutions to keep the device in its intended operating range. Second, reduced power means lower operating temperatures, which directly translates into improved component and system reliability.”

Added Hussein: “The temperature is a function of the power so if you can lower the power, you can lower the temperature of the actual device and its surrounding parts. Equation 2 is based on the acceleration factors between the two different devices in this example. If it is a difference of 10 degrees, in junction temperature, the equation shows that a device that runs 10 degrees less on a junction temperature will last twice as long as one running 10 degrees hotter,” Hussein explained.

Actel, which has been the low-power leader in the FPGA space, has focused part of its reliability argument around on-chip memory. Unlike other FPGAs, Actel’s use flash memory, which is less susceptible to single-event upsets caused by either terrestrial or cosmic radiation. And while that’s of obvious importance in aerospace applications, it’s also considered important in critical functions such as automobile powertrains because upsets often affect multiple bits at increased densities. That may be enough to shut down a chip permanently.

There are workarounds in circuitry and software for these kinds of problems, but they add more area to the circuitry and raise the overall power consumption to make sure there are no problems.

New techniques impact low-power design
With designs today utilizing techniques such as power modeling and complete coverage verification there are pros and cons as to the impact on the design.

“Power modeling and advanced verification techniques have definitely improved the ability to hit the projected performance/power curve for a specific design. However, at the end of the day, it still comes down to understanding the target application usage model and using the modeling techniques to tune the design appropriately. Without it, one may still come up with an impressive looking data sheet that really doesn’t cut muster in real application,” said Intel’s Mehta.

In addition, Synopsys’ Jadcherla explained, some of the techniques adopted such as power gating and voltage scaling themselves cause new problems. “First, IC designers really need to now analyze each physical region (island) by itself independently, unlike the entirety of the chip. And they need to do this across all the temporal situations (aka states and transitions) that are likely to occur. Second, the very act of moving voltages adds new irritants into the integrity of rails and signals – the collapse of either can cause temporary failures or permanent device breakdown.”

Another consideration of using advanced techniques is that the architecture team has to model and evaluate the benefits of various low power techniques regarding the use cases targeted by the final application. This leads to defining the various voltage and clock domains, Docea’s Kaiser said.

Finally, a new entrant into this drama has been temperature, Jadcherla said. “Cross die variations are exacerbated by low power designs. Perhaps one part of the chip is mostly off (cool) and another is mostly on (hot). There is very little data on die-level effects, though my suspicion is that field failures haven’t been studied enough. People just can’t wait to get rid of their older model consumer device. At the system level, however, temperature or rather failure to manage temperature of SoCs has caused enough embarrassing failures – devices exploding, devices locking up thermal runaway, and laptops hot enough to boil water.”

Pallab Chatterjee & Ed Sperling

A French startup has a new angle on power analysis, targeting the solution to the design task of energy in an electronic system as a systematic binding element rather than just a static parametric element.

 

The founders bring experience from the wireless, semiconductor and software arenas to the task of “energy management” for electronic design. This takes the form of both power and thermal design analysis and planning. Their methodology is based around a proprietary product they have created called ACEplorer, which is an Abstract Concept of Energy exploration tool.”  

 

Basically, the flow requires the designer only to have a concept of the power state flow for their design (on state, off state, sleep state, power down state, video off state, etc.). They do not have to have any detailed RTL. Using a VCD interface, and a traditional XML data format, a designer can describe the models of the IP blocks of the system and the design functions for each of the power states and create an appropriate UPF model that incorporates all relevant energy information. This includes active power, passive power, thermal power and the power associated with the drivers connected to the external load/package/cable. The resulting compact models are then appropriately temperature modified and used in power simulations to determine the device level power performance and spectrum of the product.

 

For new devices, high-level XML-based traditional models are used and input, and the new UPF model are created. The methodology can be also used for characterization of existing devices as well as for migration and spec creation for derivative IP.  For the derivative flows (typically on similar technologies such as a G process to an L process) the flow would be to create a detailed characterization model, run the power simulation (SPICE level), then modify the values to in the model to reach the new goal and create the spec for the new block RTL.

 

Unlike some of the other tools on the market, as the models are high level, and work up at the power state, it does not matter the if the blocks are digital, memory, I/O, analog, display, board level, power regulation or SIP.  This method allows for the detection of thermal run-away, prior to it being a disruptive event in an incompatible set of state changes.

 

Started as a spinoff from the Grenoble ecosystem project, which has since evolved largely into an STMicro ecosystem, DOCEA founder and CEO Ghislain Kaiser said the real advantage is to be able to do power analysis that takes into account more parameters up front to make estimates more accurate.

 

“What these tools allow you to do is make estimates that are more accurate and explore an architecture that will be optimum,” said Ghislain. “That decreases the need for

additional margin.”

 

As it is a new paradigm, it will be interesting to watch and see the adoption cycle in the mainstream semiconductor industry. DOCEA rolled out the first version of its product at the end of last year and says it has several customers already and has received positive adoption of the methodology from several key clients in the portable design space.