The idea of developing software and hardware simultaneously isn’t new, but it has taken on renewed urgency in IC design because of growing complexity, including power and proximity issues. Low-Power Engineering captures the perspective of executives at four companies working in this market: Marco Brambilla of STMicroelectronics; Charlie Janac of Arteris; Mike Gianfagna of Atrenta, and Javier DeLaCruz of eSilicon.

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

LPE: What is concurrent design and how has the definition changed?
DeLaCruz: This is a legacy we created for ourselves because physical design teams can operate separately from CAD tool developers and packaging and everyone throws what they’ve finished over the wall. Concurrent design is a way of undoing the damage we’ve driven into our culture. We can do this by creating CAD tools that allow concurrent work on the same thing. Cadence, Synopsys and Mentor are all trying to create tools for this. Another way of doing this is by getting your people to talk together more effectively. That’s difficult because people have been told they should work in different departments, not talk to each other because things get messy that way and take too much time.
Gianfagna: There are two things that caused the problem. One is that we used to do things sequentially. You did placement, you did routing, and then you’d tweak the placement and timing would be closed and everyone would be happy. You can’t do that anymore. Now when you change placement you break timing. When you fix timing you mess up clock synchronization. When you fix clock synchronization you mess up power. And they’re all related. One breaks the other. So there’s a need to simultaneously optimize. Beyond that is an even bigger problem. The supply chain is now spread out. You’re dealing with a separate packaging company, a separate substrate company, and five or six IP developers.
Brambilla: There’s another level of complexity. My team does turnkey designs and ASICs. When it’s turnkey it’s easy. When it’s an ASIC you also have a huge separation between the customer doing the RTL and us doing the rest. There’s a big discontinuity. When people want to go to the next node, sometimes they’re approaching it with a software mentality and don’t realize that a forward loop becomes a million gates. Once upon a time we did software-hardware co-design. Now you have separate entities who say that’s your job and this is my job, and we have to cross-educate them.
Janac: You’re taking a serial design and that serial design has gotten longer, and now you’re trying to make it parallel. The parallelization of that process cuts the time. The answer is that you have to consciously create islands where this parallelization works and then have very well defined communication between those islands. Let’s take this problem of the RTL designer and physical layout separation. If the physical layout guys can get the constraints up front into the RTL, then the physical layout people will not get junk from the RTL designer. There needs to be a well-defined set of interfaces between those islands.

LPE: But this is all getting more complicated, right, and not just within a single block or subsystem? You have proximity effects because of density, you have electrostatic discharge issue, power issues, heat issues, software that may or may not work across the whole thing, and version-control issues on IP.
Janac: Within these islands you have to take into account an increasing number of constraints.
Gianfagna: We’re hearing it with timing constraints. The front-end guy needs to worry about timing constraints more. What we hear is that’s a back-end problem. It’s hard-wired into everyone’s brain that it’s a back-end issue, but that’s wrong. Is there a human issue here? As an industry we don’t have a great track record of changing quickly.
Janac: Atrenta had an advertising slogan that I liked, which is that timing closure begins above RTL. The earlier you solve some of these problems the cheaper it is to solve them.
Gianfagna: Intuitively that makes sense. When it comes down to the real world that isn’t always the case. People don’t always approach it that way.
Janac: But then their chips don’t come out. It’s hard to tell an RTL designer they have to worry about congestion. But if you give them a capability to eliminate that congestion, such as cutting wires in half, then they’ll use it. But if you tell someone they should speak French it’s not going to happen unless you teach them to speak French.
Brambilla: There are several issues here. I wish we could still work in islands. The islands are getting blurred, or they require more people from different functions to work in them.
Janac: You need to build bridges between the islands.
Brambilla: But you also need to populate those islands. They’re no longer homogeneous. We have started on 28nm devices. These are 17 x 17 or 18 x 18 mm. You’re talking in excess of 100 million gates for non-repeating logic. The graphics guys are doing 100 million gates but it’s copies of the same thing. There is still a problem of validation, but from a design point of view it requires a different amount of resources. When we’re doing a communication ASIC of 100 million gates, that’s all random logic. You have people putting 4x more gates in the same area with greater productivity. They don’t have time to worry about congestion. And they’re moving up, up, up in terms of higher-level coding languages. If I want to port to double the frequency I might have to change my bus width rather than just doubling the clock.
Gianfagna: That’s a microarchitecture change.
Brambilla: But you can’t do that in Verilog. At that point you’re talking to a software person or an algorithm person, not to a designer. Try to explain to that person what the structures are that can cause congestion. Sometimes I have trouble explaining memories to a designer. They don’t get it. There are Verilog designers who don’t understand what their Verilog becomes in gates. How do we ask them to be more proactive?
DeLaCruz: We’re victims of the way we used to be organized. I keep hearing this term ‘islands.’ I think it’s a big crutch. We’re just putting Band-Aids on this. These islands need to be moved. Within eSilicon, rather than the physical design team creating something that can cause problems with packaging, and packaging causing problems with PCB design, we moved the line. We overlap physical design significantly. The packaging team does floor planning, pad ring layout, and all the SSO operations on the die. By the time it’s gotten to packaging we know it’s done properly. All of our packaging personnel are mixed in with our physical design team. That’s blurring the line. The islands aren’t being kept separate. As we go to through-silicon vias, is that interconnect a packaging issue or a design issue? You can’t have the delineation anymore.
Janac: Why not give them the tools that isolate them from the complexity?
DeLaCruz: Let’s say you have a chip design that can be a certain die size, in round numbers 4 x 4. The physical design team wants to add more signals. If you go to 28nm, you’ve got all these signals and your die has to grow. They don’t know about all these things like silicon interposers, which would translate that 4 x 4mm die into an 8 x 8mm die.
Janac: You can have an interconnect that contains all the wires. Do you put all those wires on one die or on another die? You’re giving them the tools to deal with that.
DeLaCruz: You have to cross-train because 3D silicon is not a physical design issue. It’s a packaging issue. There’s a methodology in physical design. There’s an issue in packaging. It’s a little bit of each, and you can’t have different people doing each.
Janac: It’s a combination of training and methodology. You have to train your designers and tell them that a 3D toolkit is part of the methodology they have. And then you have to give them the tools to successfully implement their technology.
Gianfagna: You can come up with the tools. We in EDA can come up with the vision. But it doesn’t mean anything unless there’s a mandate from the top down that this is the way things are going to work.

By Ed Sperling
Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation.

LPE: Is a fully integrated IP platform an effective way of dealing with power?
McCanny: There are a lot of issues that we’re still trying to get our arms around. A lot of the tools we’re using were not designed with power in mind. We’ve adapted them. We’re using different constructs to handle power constructs. As an industry we haven’t designed from the bottom up for how power is managed and modeled. Platforms may help, but that won’t be a complete solution. There are still a lot of complex issues to be worked out, such as predictably modeling power. We also need pre-set rules for IP for what you can and cannot do with it. We need to know, for example, ‘This is how IP will behave when you power it up and power it down, and when you go from this voltage to another voltage.’ Right now we’re tweaking as we go along. You don’t know what the IR drop will be or how it will affect the IP block. You have no control over how the power supply is connected to that piece.
Rajendiran: We start somewhere in the middle. There are high-level system-design tools, and meanwhile there has been an explosion of nuances on the physical side. System-level design can be perfect, but then somebody has to map it to a physical and implementable device. If I had a set of functions I want to implement, I could choose hard IP from Supplier A and Supplier B. Each will have a different implication for power. Even where you put it will have different implications. One may cause a different IR drop than the other one. System design has not taken off because you need to know all the possibilities. There are gaps in between.
Gianfagna: Gaps are the enemy. You need everything to be implementation-aware all the way through the process. If you look at the high-level ESL companies that don’t exist anymore it’s because of those gaps.
Brock: A well-defined piece of IP differentiates on power, performance and area. But it also has to be usable. In the case of memory, you have to have a mesh across the whole thing so when you tack on the power you don’t get an IR drop all the way on the other side. If it’s from a reputable vendor you may not have to look inside because you know what it will do whereas if it’s coming from someone else you might have to poke around inside. The only way you know if something can be dropped in from outside the box is by making a lot of mistakes and coming up with something that has been tested over the years and that you know you can trust. So Vendor A may be thinking about all of these little details.
McCanny: There is a lot of IP that’s a black box. To some extent you want a black box, but when something doesn’t work out there’s very little information to determine what the problem is. Knowing which things have been checked out and which things have not is essential to know. You get the numbers but no information about where this data came from. The IP vendor doesn’t want all their secrets stolen, but if the customer uses it in the wrong way there’s no information about why his model doesn’t match transistor-level simulations or his silicon, which is even worse.

LPE: As we move into 3D stacking that becomes even more critical, right? You have proximity effects in multiple directions. How big will this problem be and will it affect 3D’s adoption?
Gianfagna: 3D will change the market. Now you’re not just selling hard or soft IP. Now you can start to think about selling pre-characterized slices in the stack. That could be a memory supplier or an FPGA supplier. It will expand the market. But there’s a new set of analyses. The early analysis of the stack before you place IP becomes much more difficult. You’ve got placement problems and thermal and mechanical issues that didn’t exist before. Making silicon paper-thin and then punching holes through it and seeing if it still works isn’t simple. Beyond that, there’s a whole separate issue on sourcing and building the stack. Who’s going to be the general contractor? Who’s going to take the yield risk and the inventory management risk of the heterogeneous stack of silicon, put it together and ship it to an end customer. The end customer won’t take that risk in every case.

LPE: How much of the content changes in a 3D stacked die and does it come from more or fewer vendors?
Rajendiran: The first place it will really be adopted is in the memory space. The industry is waiting for some standardization of the interface from companies like Micron. Once that happens it’s really going to take off. Meanwhile, whether it is TSV-based or SiP-based, the inventory management issues are the same. We have a customer looking at the SiP package, bringing their die and their partner’s die and we’re putting them together.
Brock: We’re still putting everything together, the foundation IP with memories and high-speed interfaces. We have an analog component, processor component, cells and MDM, so the natural outbreak is to come up with IP subsystems. If a company needs an analog front end for a high-definition TV, we have all this stuff that can go into that. That’s going to be the natural outgrowth of collaboration. At Virage we had a processor, memory and logic, which is what you need to build a core. You can characterize that, add some software stacks and you can start growing them. But you also have to be very cautious about how you build those. You have to be sure there’s a market.
McCanny: When you put all these blocks together you get one big block.
Brock: Or a collection of blocks that can be, ‘Slot A, tab B.’
Gianfagna: The derivatives are a good argument for an IP company being part of an EDA company. You have to have the ability to do customization. A large EDA company can do that. A small IP company cannot. You need infrastructure to do that right.
Brock: There are places for small IP companies. Most of them started as design services companies.
Rajendiran: And most of them still are design services companies. If you look at the IP industry the biggest one is ARM, the next biggest is Synopsys, and after that it’s MIPS. After that, I can’t think of who’s fourth. On the one hand, everyone is a design services company. When this began the only master they served was an OEM company. When it became a completely open market one design served 100,000 companies, so you had 100,000 masters. The IP industry takes the easy way out by remaining small.
Brock: But there are a lot of unique collaborations going on.

LPE: Don’t all the fabless companies become IP companies?
Gianfagna: Is it IP aggregator or creator?
Rajendiran: They do create their own IP that becomes part of the chip.
McCanny: Over time, will the small guys wither away? Will end companies still use the IP from these companies if the IP isn’t completely validated?
Gianfagna: If we can come up with a language for how to do that, then we will use their IP. Validating a piece of IP generally is easier than building it from scratch. If nothing else, you’re on the back of the 10 guys who came before you. The problem is there is no way to validate the quality, the deliverables, the use model, the scope of use and the integration risks.
Brock: Very often it’s a bunch of guys in a garage with a great idea. But it’s how you build it and the methodology. The kind of people like things done and if it’s not done in a certain way they get upset. You need a bunch of those people.
Gianfagna: Strong, rigid methodology pays off in IP.
Brock: It’s this discipline that has to go in step by step. The gotcha is when you skip a step. You may not find out about that for a couple of generations. You need tools to go in and understand what’s really there.
Rajendiran: A lot of people leave companies and that step you skipped a couple generations ago no one remembers. If you can build tools that can probe the IP who’s going to let that happen?
Gianfagna: There are a couple of 900-pound gorillas that could make it work. The end customers also can demand it. The IP providers won’t wake up tomorrow and say they’re open to criticism and change. It’s not just the syntax of the IP, though. It’s power, the clock and other things that do affect the implementation. What they’re trying to do is to dig deep enough to tell their customers what’s good and what isn’t.

By Ed Sperling
Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation.

LPE: Who’s going to be able to play in the IP market?
Brock: As we get to smaller geometries it becomes a rich man’s game. It’s like Larry Ellison and America’s Cup; 28nm is very much like that. Tapeouts are expensive, variability is up, and you need consistency. Being able to have the IP that’s made in a consistent fashion is essential. Standards are driving some of that. Having the Liberty TAB, CPF and UPF are important. But how much verification do we really run before it’s done? How big is your SPICE farm? And customers are saying that rather than going to a large number of IP providers, they’d rather go to one. It’s one throat to choke.
Gianfagna: We’ve been selling Spyglass for years, but half of what it’s being used for recently doesn’t have anything to do with design. It’s for discovering what’s in IP that has been bought and trying to figure out what’s wrong with it and how to fix it. It’s discovery and improvement. If you have a tool that can optimize a design it also can tell you what’s wrong with it. That’s a new application. If you can figure out ways to better assess the quality of IP, it may be a trigger for how the industry can grow. That may help the small companies play in this market, too.
McCanny: Most of our efforts are focused on standard cells. There is a myriad of things you can do and you can’t do them all, but what is the best choice? It would be bad for the industry if we killed the innovation of the little guys. A lot of these little guys can become the big guys later on.

LPE: Is the future the little guys, or is it platforms of re-usable and integrated IP?
Gianfagna: It’s both. The market resists being homogenized. The more you get standardized platforms—and you will, because the complexity is going up and the number of tapeouts is going down—the more the market will provide differentiation. One change is that the startups will be more software-oriented rather than hardware-oriented.
Rajendiran: If you have a chip and 90% is standardized, there is less chance for differentiation. That’s one of the reasons software is taking off, but you also can’t do everything in software. Verifying the software is actually more complex than if you have well-defined operating and power modes in hardware. So hardware is still important and the IP is important. But to a large extent, the off-the-shelf part needs to be addressed by the big companies. The smaller companies need to come up with whiz-bang innovation. We still need small companies, but they have a challenge with the foundries on one side and the customers on the other if all they’re doing is the same stuff as the big companies. There’s a place for everyone, but to be successful they have to play their role. Even TSMC tried to do IP because they thought they would have better control if they did it themselves. That wasn’t the case.
Gianfagna: It’s an ecosystem, so everyone has to play their role and there has to be glue between these roles. For a long time, EDA has played a role of enabler for the end product for someone else. They’ve been a silent partner. EDA can be an enabler for business. If we’re right about the need for better validation and better incoming inspection of IP, whether it’s at the transistor-polygon level or the synthesizable RTL level, then EDA can become an enabler for the IP industry and collaboration across the ecosystem. It’s EDA providing value at a different level.
Brock: That’s correct. People are now using Spyglass to look into the black boxes. They used to build the black boxes before and it was good for that. If 70% or 80% of an IP on a chip is bought, it’s a different use. As an IP provider, we’re seeing that in different areas. There are natural places for standardized interfaces. There’s a committee that defines the standards, and you’re not going to differentiate by doing USB 2.0 or 3.0. You just have to have it. That’s a very natural place to play in the IP industry. What we’re seeing now is more of the vertical integration—what we’re calling IP subsystems. If someone needs an analog front end for a digital TV, you’ll have cells and memory but you also need a processor that does audio and soft codecs. But sometimes you also a hard analog codec. That’s where a lot of innovation happens. This can be done by small companies and they can become very successful.
McCanny: TSMC tried IP and they still have it, although they’re de-emphasizing it. EDA has picked up the baton. But do you think that’s the right place for IP? Is it so complex that you need to have the collaboration with the tools supplier to build it and validate it, or are we still in a world where IP and EDA are separate?
Brock: We used to be pure-play IP (at Virage Logic, now part of Synopsys). Now, working with all the EDA vendors and supporting mixed flows, I see a better need for collaboration. We need to be able to see into modeling. For the validation part, being able to pound on the IP for more corners and stress corners is important. But it still has to work with mixed flows.

LPE: Is an integrated EDA/IP company better?
Rajendiran: The EDA companies can have unlimited access to verification tools, whereas an IP company needs to buy the tools. But that doesn’t solve the problem. You have to work smarter. When you’re verifying something, how do you know you’re verifying the functionality correctly and have the right use mode? An IP company and an EDA company combination don’t make a product company. That domain knowledge needs to happen on a larger scale.
Gianfagna: It’s a good thing IP is migrating into EDA because you do have access to the tools. An IP release is a combination of careful program management, validation, ensuring all the parts are there. That’s all good. There’s a bad part of this, too. The IP industry has been able to have higher multiples than EDA and sell at a higher value. Let’s hope that EDA doesn’t mess up the IP industry and that IP can teach the EDA industry. The EDA industry is not known for its ability to get value from its investment.
McCanny: There is also the danger that because the multiples are so much higher in IP that EDA margins will shrink further because it will be packaged with IP.
Rajendiran: Give or take a half-billion dollars, the EDA has remained at $4 billion for a long time. The semiconductor industry is about $300 billion. If the married IP plus EDA can get even 2% of that, it’s a lot more than what’s available now. IP becomes part of the chip and it ships for many years, so you can deliver the IP and get a piece of that. With EDA, for all the hard work that goes into the tools, after tapeout there’s no more interaction.

LPE: Don’t the dynamics change? In the future you won’t be able to separate out the IP, the software and the hardware. The market may be bigger.
Gianfagna: It will definitely be bigger, and EDA companies can get a lot bigger along with that if they participate in that larger market.
Brock: That will be even greater if we get involved in the application software, the EDA, the IP and the software enabling the technology to make it all happen.
Gianfagna: They all become part of the mix. More of the differentiation will be in software and that’s going to require careful design and marriage to the hardware. That’s a new model. Right now we build a chip, throw it over the wall and say, ‘Make it work.’
Brock: That’s where a lot of the processors are making that easier.
Gianfagna: They’re enabling that model.
Brock: With a smart phone you’ll have one ARM core running the baseband processors, but there might be four or five ARC processors running the surround sound and the audio and a lot of these smaller applications. These are lightweight embedded cores that are buried on an SoC that can be programmed.
Gianfagna: The other opportunity is the platform. It’s a collection of IP that works together in a certain way and which can be modified predictably. There’s a lot of EDA in that. So is there a way that EDA companies can collaborate with semiconductor companies on the back end to make all of this happen? It’s a whole different model for EDA, which is in my opinion a healthier model.

By Ed Sperling
Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation.

LPE: What is the big issue in IP these days?
Brock: Quality, quality and quality. There are people wanting to use it out of the box and it has to save them a significant amount of time and effort, or else they can build it themselves. It has to follow the function and specification that’s there, and it has to be robust. We don’t live in a perfect world, of course. The silicon does have variation, and it’s getting worse at every node. Getting something to work the first time and everytime is a challenge. That’s the big issue.
Rajendiran: Quality is obviously important, but the high-level issue is the disconnect between the users of IP and the builders of IP. Customers want a certain thing from a technical or a business perspective and suppliers want it a different way. The fact that market cycles are becoming shorter has aggravated that situation even more.
There has been a lot of consolidation over the past two years, which has actually helped things. But disaggregation means that everyone wants to start their own IP company, and they all try to go too broad, so quality suffers. That is really the big issue.
Gianfagna: We could have had this discussion 15 years ago. In the 1990s IP re-use was a big problem. This problem has been around a long time, but somehow in the past year or two it’s hit an inflection point and it’s now more serious.

LPE: Is that because more companies are using off-the-shelf IP?
Gianfagna: It’s more than that. A tipping point happened in the last year or two. We went from chip designs being original work with some IP integrated to a chip design being 90% IP, and hopefully you pick it right. Now the IP quality issues really start to bite you. If you pick bad bricks to build the building it falls down.
Brock: The timing you picked is right. Something changed in the past 24 months. Wafer shipments went to about a third of what they were. Everything dried up. But a lot of the people running the fabless companies and the IDMs needed to scale back. They began to really consider outsourcing the IP they had been talking about for 10 years because that wasn’t their value add.
Gianfagna: Our industry always changes in the bad times.
McCanny: Those points are valid. There’s also shrinking time to market and low power. People can live with the methodology they had for IP re-use. It wasn’t perfect but they could make it work. But with low power coming along in all the portable devices they can’t do that anymore. People need their IP models in a certain way at a certain voltage. Voltage is not linear or predictable, like timing is. Power effects are non-linear. So all of a sudden people are demanding all these different views and corners, and it’s impossible for the IP provider to ensure quality across such a wide range that customers want these days. It used to be a chip had a single voltage. Now you want to play around with voltages depending on the application. Those have made the problem more acute than what it has been in the past.

LPE: IP has to be both power-aware and proximity-aware. How do you deal with that?
Brock: That’s true. And on top of that there are many different ways of doing things. Smart phones get hung up all the time. You have to take out the battery and then start it again. It doesn’t know what power mode it’s supposed to be in. At least ‘off’ is a known state. All the other states have to be simulated and retained in the models we create.
McCanny: The compelling vision of IP was that it was a black box. You didn’t need to know all the details about it. You could plug it in and it would work. You didn’t have to have core expertise with an interface, for example. Now it may work under a certain set of environmental conditions, but it might not work if it’s next to this. Or maybe it will only work at this voltage if it isn’t switching over from another voltage. All of that brings pressure on the acquirers of IP to become experts in the IP they’re getting. So will the pendulum start swinging the other way?
Gianfagna: That raises an interesting point about whether the little guy is destined to fail. If I have a piece of IP checked out for a certain set of applications, voltage domains, frequency and configuration, the IP provider says it works here and therefore it should work everywhere. It doesn’t work everywhere, and that’s a problem. So are people going to demand from their IP supplier that it be checked and validated across a broad set of applications and certified by someone—most likely the supplier of the IP? If that happens there will be a few very large, multinational, multibillion-dollar suppliers of IP. It takes a lot of resources to stand behind something with that much validation. It’s not easy to do.
Rajendiran: Even if it’s a big company with a lot of resources, they still have to pick the first few customers and make sure all the use cases are addressed. They can’t address the broad market because of economical reasons and bandwidth. And the one they support initially won’t allow them to support everyone else because they’ll lose their competitive edge. So there’s a built-in conflicting requirement. I don’t think everyone will try to build it all themselves. There’s a ceiling on the cost, and by taking on everything yourself the only way to do that is to increase your resources. The market won’t allow that to happen. Collaboration will be the key. And it won’t just be two companies. With the soft IP you want to collaborate with the end customer. With the hard IP you want to work with someone who tapes out designs. They need to understand all the IP blocks from different vendors. The ones implementing that day in and day out are the ones who understand that best.

LPE: All of this depends on a much more tightly integrated supply chain. How realistic is that and who’s going to drive it?
Rajendiran: As we go through these cycles, one thing that has consistently gone in one direction is the focus on performance, area, and now power. There are various ways to address that. If 3D stacking takes off, people are going to leave certain blocks at 40nm because they know it works. You get the benefits of cost and you can integrate it quickly. We have gotten so much more performance out of these chips we don’t need anymore. There are several things changing to make this happen. One is consolidation. The second is the TSV (through-silicon via). And the third is that if you mess up at 28nm it’s a much bigger deal than in the past. Collaboration will happen.
McCanny: The large IP companies can only collaborate with so many of their customers. One of the perceived advantages of small companies is that they have a particular expertise in a small area, so they get 90% of the IP from other companies and add their own expertise. We’d all like to see that. We’ve seen some small startup chip companies get picked up by companies like Apple. It would be bad for the industry if we couldn’t serve that market. But there are definitely challenges because until you get to a certain size you can’t get enough collaboration. Our initial mission was to build models for IP providers. Now we’re starting to go more with IP users. They say, ‘I’ve got these models from different sources. I don’t know how to put them together, but at least I can run a tool to help me understand whether these models make sense for the process and voltage I’m using.’ That requires more cost on their side and to get more in depth with the IP to understand why certain anomalies occur and why things only work at certain voltages. It’s not easy and the problem is getting more difficult rather than simpler.

Low-Power Engineering takes a poll of the big problem with IP and how to solve it from Ken Brock, senior staff product marketing manager at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Jim McCanny, CEO of Altos Design.

By Ed Sperling
ARM took a new tack in its war with Intel. The company is working on a Green Cloud Services project using the ARM architecture in conjunction with Nokia, IMEC, EPFL and the University of Cypress to create a 3D package with low-power processing. This is particularly interesting in light of gamers using Intel Atom-based servers.

Along the same power-saving lines, Actel introduced its power management solution for its SmartFusion mixed signal FPGA, complete with a reference design and a configurator for power sequencing and trimming. Given Actel’s focus on low power in its other chips, this isn’t all that surprising.

Also on the low-power front, Virage Logic introduced a big update of the open source GNU and Linux toolchains for its ARC processors, which will soon belong to Synopsys. That puts Synopsys firmly into the open source world, as well, with interesting implications.

Arteris joined forces with other EDA and IP vendors supporting TSMC Reference Flow 11, this time with network on chip interconnect IP. This is more like networking the industry on chip.

eSilicon will provide logistics services and production operations to Ember and Pixim. This is an interesting extension of supply chain expertise.

Mentor Graphics rolled out its commercial embedded Linux platform for Freescale, building on a strategic alliance the two had signed in April.

Mentor also won a couple deals with Mindtree for its Questa functional verification and with Autoliv for machine programming.

Both Synopsys and Cadence trumpeted successes with their products. Cadence global services enabled a 65nm TD-LTE baseband chip from Innofidei, a company with operations in Taiwan and Beijing. Synopsys, meanwhile, demonstrated interoperability between DesignWare IP for PCI Express 3.0. The company also awarded the Tenzing Norgay interoperability achievement award to IEEE-ISTO. We’re not sure what the famed Sherpa had to do with interoperability, but congrats.

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: How do complexity and all the different levels of the flow affect signoff?
Buric: Signoff is necessary at every level. Signoff at the DRC level and the DFM level and the gate level will stay forever. However, what’s different is that if you don’t sign off at a high enough level you cannot get to the next gate.
Gianfagna: It used to be that you could leave it to the end and clean it up. You used to be able to leave OPC (optical proximity correction) to the end and fix the litho hot spots. You can’t do that anymore. There are too many hotspots. The tool will find them all but you can’t fix them all. That’s an opportunity for EDA to add more value further upstream so you don’t have to find all the problems at the back end. There are tons of examples like that with power, test, area and routing congestion where you have got to start earlier or you get crunched in the funnel at the back end.

LPE: Engineers have been postponing using power islands and clock gating as long as possible. They seem to have run out of options, even at even mainstream process nodes. Do they understand the difference of what’s needed vs. what’s not?
Levia: There are definitely companies that know what they need and which are very good at educating their suppliers. They’re very good partners for us. If you work with them, they have a very clear road map about what they’re going to do and they are very articulate in communicating what they’re going to need, when they’re going to need it and why. Sometimes they can even tell you how much they’ll need. But unfortunately there are not many companies in this category. More fall into the ‘need to be evangelized to’ category. ‘Let me tell you why you’re going to need power islands.’ Or, ‘Let me tell you why verification is different with power islands.’ So there are two distinct camps.
Rajendiran: The one thing that has changed from a market application perspective is more and more people are buying consumer parts. More people are buying a phone. If you’re a businessperson, you’re going to be using it equally for e-mail and phone. If you’re a teenager you’re going to be using it for texting. Some of them are so good they can text without even seeing a keyboard. So depending upon who it is, power consumption is going to be driven by the application. It’s not so much how much power you can put in, it’s now driven by the usage model. That’s a big change from 10 years ago when you worried about a processor that was 50% faster or one that consumed 20% less power. Those were the two slides you took to a VC to get funded. Now it’s usage. Even if you’re looking at infrastructure, it’s the green initiatives that are driving it. Intel changed five years ago when they went to multicore and power conservation. Bigger companies do a better job figuring this out and marketing it. Smaller companies are still struggling with it.
Gianfagna: Natural selection will weed out those companies.
Rajendiran: Yes, and it’s already happening.
Buric: There are a few customers—a minority—who understand what it takes. What we’re seeing as an alternative is coming from companies like TSMC with a reference flow. With the reference flow is a list of the tools needed to get you through the reference flow, which helps their business.

LPE: So they give the choice to their customers?
Buric: They’re not even choosing. They’re working with a few leading customers to learn what they need and then they have to decide whether customers can afford it or not.

LPE: Is GlobalFoundries doing that, as well?
Buric: Not yet but they will catch up. It’s a must. You cannot explain to most companies what they will need.
Gianfagna: There are a handful of customers who know what they need and drive the strategy. We all kind of work with the same customers. What’s different is the ‘have nots’ at least know what questions to ask and are looking at outsourcing more. They’re looking to understand the process better. It’s improving. The need to work differently is becoming a competitive advantage. There are some who don’t get it. You won’t see them in a year or two. That’s the opportunity for EDA. There’s a better-educated consumer base for what will bite them. You don’t think about some of this stuff at the gate level. You think about it way earlier when you have an architecture in mind, or even before. What processor will you use? What power domains? What throughput? These are high-level decisions, and it takes tools and IP. That’s the opportunity for us.

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: Where is the most activity? What node?
Rajendiran: Over the last three years it has undergone a transition. At 180nm everyone looked to 130nm and then they were all looking at 90nm. The foundries started introducing processes sooner and sooner. It used to be about three years between nodes. Then it became two years. Between 90nm and 65nm it was really only a year. It confused everyone because the expense was going up. The IP companies had issues. Then the economic downturn hit. We saw a resurgence of a lot of designs going to 130nm again instead of 90nm and 65nm. There are companies that have chips and are thinking about taking what they have and combining them into an MCM (multi-chip module). It may not even be their own chip. They may be combining it with another company’s chip.

LPE: So it’s going in two directions?
Rajendiran: Yes. Some companies are looking at MCMs. Others are looking at 40nm and 28nm. There is a lot more risk, so people are really thinking out of the box.
Levia: Everyone looks at it from their perspective, but that can be really different depending upon the market they’re in, the size of their company, the geography they’re in. The economy comes into play whether you’re in China or the United States or Canada. What you’re trying to accomplish is very different.

LPE: In the past, when we pushed to the most advanced nodes, you were dealing with one or two problems. Now you’re dealing with all of them at each new node. How does the cost equation affect everything?
Levia: Fabless companies and IDMs, whether they’re moving to the next node or staying at existing nodes, haven’t always figured out up front what the compounded complexity will be. That may be in the form of verification or the design or integration or packaging, functionality, reliability or DFM. The demand that puts on the EDA industry is to come up with very quick solutions to second- and third-level integration problems. It also puts pressure on the cost function. We are expected to participate in that cost reduction. The problem has exploded, but the price of the phone has gone down and the revenue to the chip provider has gone down slightly, so you’re expected to take a haircut. It’s a problem, but it’s an opportunity for the companies that can automate difficult steps. These steps may be very mundane. It may be power estimate at the right time, or power-aware debugging at the right time. It may be DFM or DRC at the right time. You need to understand what is taking a lot of time and whether you can automate it. It’s shifting ground, though.
Gianfagna: The synthesis place and route flow is getting less interesting. Will you have a better product because you use synthesis place and route from Cadence vs. Synopsys? I don’t think so. Will you have a successful product because you chose the right IP or number of processors? Yes. The value for differentiation is moving up the stack, past the synthesis place and route flow to better IP reuse, better debug and better planning. There is a shift to put more effort on the front end because if you spend $1 on the front end you can save $3 on the back end. If you can eliminate a two-week place and route, that’s worth a lot. You also don’t need as many tools, but that’s a secondary benefit.
Rajendiran: At every handoff point you need certain things. But the industry has undergone so much pressure they don’t always think this through. You need clean deliverables at each point. There is value at every step to help with the cost of ownership. You may put a heat spreader into the package, but that may cause more harm than good. People don’t necessarily think that way, though. Given everything you’re doing, is that the right solution? Some companies are better at understanding the big picture. When you have a customer and they’ve established a methodology that they really think through, that’s usually better than a startup at understanding it. It isn’t the tools, the IP or the package. At the end of the day the product has to come out on time.
Buric: For most customers to move to signoff from the spec and all the way down is not always possible. I have seen designs people have finished and missed off spec by a few percent and they had to throw it away because it was designed to be on a PC board. There was no room for error. It doesn’t matter whether it comes from process, bad calculation or bad estimation. The industry is moving to very accurate analysis and signoff on an architectural level, and then at each level try to meet those specs. We are spending more and more on accurate modeling, and EDA companies are taking more spreadsheet functions to make high-level analysis as accurate as possible. On top of that, you can’t afford to move from a plastic package to a ceramic package because it costs too much. From the other side, I’m seeing more and more end users or system houses to provide a spec without getting involved in the design at all. They don’t see the value of design. They see the value of the box.
Gianfagna: That’s a perfect distillation of the process. The signoff need is unquestioned. There’s a long checklist of timing closure and design processes and electrical rules check for the gate-level netlist. That’s moving upstream. You want rigorous signoff earlier and earlier. The ultimate is a spec-level signoff, which will take awhile.
Levia: Let me inject a little bit of reality into this. Calibre is still not done at any high level—definitely not at RTL. But Calibre is signoff and it is doing quite well. The reality is that it’s only successful because it is offering a step that is absolutely necessary and is incapable of being accomplished any other way. You cannot do it by hand. At 28nm and 22nm, there are more rules but it’s still more complicated. There are 3D effects and the tools are conditional.
Buric: That started at 65nm.

Low-Power Engineering sat down to discuss what’s essential and what isn’t in EDA with Brani Buric, executive vice president at Virage Logic; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta, and Oz Levia, vice president of marketing and business development at Springsoft. What follows are excerpts of that conversation.

LPE: What are companies trying to do now that they didn’t do in the past?
Gianfagna: The whole mantra that you can’t close a design without better tools and without better accuracy and that complexity is an imperative isn’t new. We’ve been saying that for 20 years. But what has changed in the past two years is that it’s gone from marketing hype to reality. Complexity is so high these days that no one would dream of handing off a design without routing estimation, power estimation, architectural focus and paranoia on meeting timing budgets. Complexity is driving need to have for better up-front planning, better IP re-use, more things like verification IP and standards interfaces. That’s all continuity. Discontinuity will come from 3D. I defy anyone to say they can iterate on a 3D stack by implementing four chips, deciding it’s not right and then re-implementing the four chips until they get the partitioning right. You can’t get there from here.
Buric: A single failure on advanced process nodes will cost six months of re-doing the design. And then it will cost another $3 million to $4 million. You spend much less money purchasing all the EDA that’s needed, including the training and implementation, whether you’re doing it yourself or going to a service partner. Nobody who is doing complex chips has a question anymore about whether EDA is needed or not. The only question is whether you have the tool you need that is fully supported so that you can use it. But it’s not a question of purchasing a tool. It’s too expensive to fail.
Gianfagna: That’s been a battle cry for EDA. If you’re late to the market it will cost you this much money. It’s intuitively obvious, but a lot of companies sat there patiently and said it’s a self-serving message. Now if you don’t get it right it’s game over because you don’t have enough money to do it over again.
Buric: As a point of reference, at 40nm the average cost of a mask set is higher than the cost of the IP on a design.
Levia: For a product or methodology to be a must-have it has to satisfy two criteria. One is that it enables a step—transformation, verification, or whatever the step is—that is essential. Not all steps are essential. Getting to GDSII is essential, however you get there. The second criteria is that the tool has to automate or enable something in a way that is incapable of being done manually—or practically manually. So if you have a one- or two-person startup and they have a complicated problem, and the choice for them is an expensive tool or a bunch of pizzas and people working 16 hours a day, the tool is not a must-have. But if you have a large verification organization of 30 to 50 people and an investment in customer orders and the good will you have with many suppliers and consumers of your product, then it is a must have. What is a luxury to someone else is something you cannot afford to go without. You can still incentivize people to work 16 hours a day, but the economies don’t work anymore. If you can have a team of 50 people instead of 80 people, it’s a no-brainer. You buy the tool. In addition, all customers are not the same. Reliability might be paramount for the military and automotive, while time to market is more essential for a consumer electronics design that has to do with Bluetooth.

LPE: What’s the user perspective?
Rajendiran: We look at it from a business practicality perspective. What’s needed to get a chip out the door? If you go to a market where labor costs are lower, you need more people to get something done because the expertise level is lower there. The efficiency isn’t there. In the U.S., because labor is more expensive, we’ve always focused on using tools to get the product out. Not all tools have been adopted at the same rate, though. High-level synthesis has been talked about for 20 years. Functional verification and high-level synthesis are now taking root because things are so complex, but how do you close the gap and do the correlation? You can have great tools but still not get the chip out the door. The reason the IP industry is there is to ease that problem. We have been talking more about a multi-chip module, which never really caught on in the past, but maybe it is coming to a head. Do you really have to migrate a chip to 28nm or do you just leave it alone because you know it’s functioning and put a smaller chip at 28nm and tie it together. What we need isn’t just the newest and best tool. We have to combine that with a business perspective. You may need point tools to get over a hurdle, but don’t just change everything over. Why not leverage more IP or MCMs?

LPE: Are all companies moving forward to the next node?
Levia: We see a lot of demand for 40nm, 28nm and a road map into 22nm. Are there many people using 28nm? No. Are your tools viable if you don’t have a road map down to 22nm? No. I don’t think people are sitting back anymore and saying 65nm is enough. Silicon is cheap, but it’s not free. People are still looking for ways to improve the cost and they’re looking for ways to integrate, both in custom design and in digital.
Gianfagnia: As an EDA supplier, by definition your biggest demand and your biggest customers will always be from the leading edge. They don’t need any new tools, but maybe they’ll renew and they’ll always be the ones to push the limits. From our point of view, our tools are very front-end loaded. If you’re doing a simple chip, you don’t need it. But in a design where a back-end synthesis/place-and-route iteration is two weeks or three weeks, you can’t iterate there. That’s where we’re seeing a pronounced change. There’s a growing demand for beating the RTL in every different direction or you don’t trust it. You’re afraid of those back-end loops. The cost and the time to get it closed are changing. What used to be ‘nice to have’ is now ‘need to have.’
Buric: We see a lot of unexpected activity at 40nm in this early stage process. We already have about 40 customers. At 65nm, it was not adopted so fast. We are seeing a lot of activity at 28nm, but 40nm will be a node where you will see a decline in the number of customers moving to a new process node. People aren’t moving for performance purposes as much anymore. They’re moving there because they can put more functionality in a single chip. But in the future there will be too many applications at this process node. At the same time, we are seeing customers and foundries are investing a lot in mature process nodes. Starting from 180nm, we are seeing new generations of processes including low leakage. There is a trend to actively use a wide spectrum of nodes. From a user perspective, it will be less expensive to do older designs in-house. We are seeing a big disconnect at 65nm, 45nm and below. Owning the design at those nodes is too expensive for most companies. It’s not a question of working through the night. It’s a question of whether you can afford the design or not.