By John Blyler
Low-Power Engineering sat down to discuss trends in FPGA design and related IP subsystem aggregation with Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research. What follows are excerpts of that conversation.

LPE: Let’s start by talking about the trends in design starts in the FPGA. Is there anything new?
Wawrzyniak: Tracking actual design starts in the programmable logic space is full of quirks, compared to ASIC starts. The problem is that the majority of programmable logic design starts come from some guy playing around at his desk. While this is important information, such designs starts seldom go further than just exploration. This activity occurs at such a granular level that it’s very difficult to know what the desktop designer is actually doing. The other problem in tracking this data comes from the way people view prototyping and designing with FPGAs. For example, you might be using 5 to 10 FPGAs to mirror one ASIC. Are each one of those FPGA instances a design start? If not, what ratio of them does represent a design state? Who knows? Nevertheless, I do have track programmable logic design start data from 71 end applications. This chart (Fig. 1) indentifies FPGA design starts by market segment.

LPE: Most areas are seeing increases.
Wawrzyniak: They are increasing, although others may disagree. Unfortunately, whether specific groups see design starts increasing or decreasing depends upon their comfort level and their affiliation. For example, EDA would like to say that design starts are going down because their revenues are flat to down. Conversely, IP vendors would like to say the opposite, namely, that design starts are on the rise. Each group can support their viewpoint. The EDA companies justify decreases in design starts by not counting derivative designs in an SoC project. By derivative design I mean that you design the most complex family member first, then add or remove features or functions to suit the market needs for other family member products.

LPE: Don’t shuttle test runs and respins add to the confusion about what constitutes a design start?
Wawrzyniak: Test shuttle runs can be a problem, depending upon how involved they become.
I do count respins as design starts since they represent (to me) a new design. I know this may seem like I’m splitting hairs. But what all of the interested parties—EDA and IP vendors to fabless companies and foundries—ultimately want to know is the number of designs that are going to production. I agree that the answer to this question is very important. But my approach is to determine the level of design activity in the market. I feel that this is a better metric of what is actually going on. It reflects the true competitiveness of the silicon. For example, you may have 10,000 design starts but only one of those goes to product. That tells you that something is going on. Rather than focus on the designs that go to production, I look at the activity. What is preventing or enabling more design starts to go into production?

LPE: Do you consider an FPGA to be an SoC?
Wawrzyniak: I define an SoC in terms of IP. If the design includes internally re-used or third-party IP, then it’s an SoC. If it doesn’t, then it isn’t a SoC.

LPE: Traditionally, isn’t an SoC defined as a system that includes at least a processor, memory and interface circuits?
Wawrzyniak: There are several parameters that I have created to define whether it’s an SoC or not. It doesn’t necessary have to have all of them. For example, if I remember correctly, Sharp had a line of micro-peripherals that didn’t have a CPU core. But they used third-party IP to incorporate other functionality into the SoC. Well, you better count that instead of not counting it. It just isn’t the way that people are used to conceptualizing an SoC (Fig. 2). The way I conceived of these new definitions, new looks at FPGAs, is based around interconnect and IP subsystems.

IP subsystems refers to an aggregation of lots of related functional blocks. There aren’t a lot of products in the market yet. IP subsystems have evolved to handle the increasing complexity of SoCs. In order to keep pumping out these complex designs, vendors have had to integrate lots of IP. The reason is that it is almost impossible to manage 100 discrete IP blocks. It can be done, but it’s costing more money, time and resources. The answer is the aggregation of certain IP blocks around particular core functionality, such as security, communication and multimedia. Further, these aggregated blocks are given their own interconnect (in the FPGA fabric) to turn the individual block to work better together, e.g., for better performance and low power. For example, Xilinx has been developing IP subsystems for the last year or so.

LPE: Are these IP subsystems coming from several different third party vendors or from just one IP company?
Wawrzyniak: At the moment, it’s mostly from the IDMs. This isn’t surprising, given the history of the semiconductor industry. Once these IDMs prove out a good idea, then everyone is going it. This approach is at the heart of the trends that drive the semiconductor industry – evolution and integration. It doesn’t make sense to say that the forces of integration only apply to silicon. It’s going to apply to IP. That is what this is a reflection of—it is the next iteration, the next twist in the road for IP.

The whole point of an FPGA is flexibility. We could also mention integration and say instead that the whole point of an FPGA is flexibility and integration. But then there is cost savings. So the whole point of an FPGA is flexibility, integration and cost savings. Yet there is also power reduction. And then there’s security…

All these advantages (and others besides) have made FPGAs very popular over the years. Engineers like the flexibility, space and power reduction and integration that FPGAs provide. So it stands to reason that adding more flexibility, more integration and more cost and space savings would be a good thing.

Actel’s new family of SmartFusion chips takes all the traditional advantages of FPGAs and combines them with equally flexible analog circuitry and the world’s most popular embedded processor. It’s all rolled up in one package, and all under your control. It’s a single “super chip” that could very probably be the only chip in your system. How’s that for space, time, power and cost savings?

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By John Blyler

Believe it or not, low power is not always a driving concern in chip design, especially when it comes to prototyping portions of a System-on-Chip (SoC). That is the finding of a recent survey conducted by Chip Design magazine. The survey quantified a variety of trends in the use of FPGA-based ASIC and ASSP prototyping.

Here’s the question that was asked concerning prototyping priorities: What was the leading decision in selecting your prototyping system? Almost a third of the respondents cited “flexibility and expandability” as their primary concerns in selecting an FPGA-based prototyping system (see chart below). Also high on the list of concerns was the completeness of the solution, lowest cost and best throughput performance. But lower power was not a big concern to most prototypers.

Is this surprising? Not really. Most engineers use SoC prototyping in FPGAs to reduce the number of chip re-spins due to functional and verification problems. Indeed, that “low power” even made the list is somewhat surprising. Believe it or not.

By Brian Fuller

In the storied history of semiconductors, each era finds vendors generally attaching their strategy to a trendy application segment to differentiate themselves. For years, IC vendors were “computer companies.” Then they were in the “communications” business and more recently they were all about “consumer.”

But the evolution of technology has forced a re-assessment not only of technology but of positioning – to the point where most vendors are attaching themselves to low-power, which spans application segments. Nowhere is this truer than in the programmable logic industry, which for years was seen as a power-hogging alternative to ASICs. In recent years, however, market pressures and product churn have prompted FPGA vendors not only to deliver more features and functionality but lower power, as power-consumption issues bedevil not only consumer applications but take on more global significance as the world worries about dwindling energy resources.

For FPGA vendors, the battle is now joined all the way from their R&D departments and foundry partners to their marketing armies. The available market for low-power programmable logic devices (targeting, for example, battery-based or power-sensitive designs) is estimated to be $670 million next year, rising to $855 million in 2012 or roughly 18% of the total programmable logic market, according to Rich Wawrzyniak, market analyst at Semico Research.

“There is a tremendous amount of interest in low-power FPGAs,” Wawrzyniak says. “The low-power phenomenon is something people are going to embrace, assuming they have the right price point and the right performance.”

Different approaches, same message

While the technology positioning may differ in vast and subtle ways, the approach among vendors really doesn’t: Just throw the kitchen sink at power consumption and find any way to sand down power, cork leakage and optimize architectures.

Three of the smaller FPGA vendors make an overt show of their low-power strategy: Actel, Silicon Blue, and Abound Technology (formerly M2000).

Silicon Blue, which unveiled its low-power iCE technology a year ago at Computex in Taiwan, focuses on the consumer market where low power and small form factor are paramount design considerations. Its non-volatile CMOS-based SRAM FPGA families claim to draw as little as 3 micro amps in sleep current and 3 milliamps of dynamic current. The iCE Mobile FPGA family, built in 65nm CMOS, also claims not to scrimp on size to achieve power goals with versions ranging from 100,000 to 800,000 FPGA system gates.

Silicon Blue compares its family to Altera’s Cyclone or Xilinx’s Spartan devices “except we’re optimized for power,” said Denny Steele, director of marketing and applications at Silicon Blue.

Because Silicon Blue is a startup, “Every time we have a design choice to make, we could optimize for low power. We didn’t have any legacy to consider” as older FPGA vendors do, he added.

At Actel, the differentiation comes at the technology level. Its flash-based FPGAs differ from SRAM-based alternatives from Silicon Blue, Altera and Xilinx. SRAM-based devices experience power spikes at boot-up, which can drain batteries. Flash-based devices do not require an external configuration device to support device programming, Actel notes. That can cut system power by as much as 70%, according to Christian Plante, director of product marketing at Actel.

“You use one chip, not two chips,” Plante says. An architectural feature Actel calls Flash Freeze can drop standby draw to as little as 2 microwatts, he says.

For an increasing number of battery-powered electronics applications, this can be a key differentiator as the flash technology helps reduce leakage at standby.

The low-power challenge is a bit more complicated at the larger, older FPGA vendors, Altera and Xilinx, which spent their early years bulking up on performance and functionality while attacking each other’s market share and nibbling away at the low-end of the ASIC market. The relatively new low-power mandate has forced them to attack the problem in myriad ways.

Xilinx began really attacking the power problem five years ago this month when it introduced its triple oxide process for the Virtex 4 family, says Matt Klein, a member of Xilinx’s technical marketing team who has focused on low-power issues for several years. Thin oxides are key to higher performance, but as they shrink to a dozen angstroms or so in thickness, electrons tunnel away and leakage soars. Xilinx and UMC offered three different thicknesses of the insulating gate oxide layers to lower both static and dynamic power by as much as 50%. Designers could trade off thickness in places where they had to have high performance transistors and places where they needed to optimize and lower leakage.

Since then, the company has taken a holistic view toward static, dynamic and i/o power issues. These includes offering four different transistors at 40nm (low leakage to high performance) for designer tradeoffs; more direct metal connections to cut capacitance and draw less dynamic power; adding mid-level clock gating to allow users to toggle clock trees on an off to manage power draw; making termination for memory interfaces dynamically switchable to select high performance or low power.

These and other steps—including process shrinks— have helped reduce power consumption significantly depending on product, sometimes up to 70%.

Altera first began to attack the problem through software, specifically its Quartus design environment. It implemented programmable power technology that allowed Quartus to bunch up high-speed paths together into logic array blocks (LAB).

“Then what Quartus is free to do is put some LABs into the normal high speed mode, some in low power mode and some can be turned off, so there’s no static power consumption,” notes Umar Mughal, manager for low-cost products at Altera.

In addition, the company has adopted similar tactics to rival Xilinx by focusing on power-hungry memory interfaces, which are getting wider and faster. The company has implemented resistors required for termination onto the chip itself, eliminating the need for extra circuitry. It can save power by as much as 20%, Mughal says.

Power’s future

The advances FPGA vendors have made in recent years have helped them expand into markets their former power-hogging ways once would have found closed. John Birkner, an FPGA industry veteran who is now vice president of strategic marketing for Silicon Blue, says net PCs are one hot application for low-power FPGAs because the electronics architecture and some standards are still evolving.

Few vendors are willing to tip their power-optimization strategies at this point. Leakage issues will only increase in ultra-deep submicron nodes where process variability will soar. Some surprisingly long-life, low-cost, small form factor battery technology could emerge to save the day, but don’t bet on it. FPGA vendors aren’t.

In preparing for the 32nm manufacturing node, Xilinx has assembled a cross-functional team from IC design to technical marketing to manufacturing which has identified no fewer than 30 concepts for reducing power at that future node.

“We’re pushing these ideas into the IC design group, and a number of them have already been accepted,” Klein says.

For Actel, “the keyword is integration,” says Plante. “Another way to put it is system partitioning will be one knob we’ll give to the end user to decide how to solve their power problems.”

Though once a novelty, electronic devices are now ubiquitous and a necessary part of every day life. From the boardroom to the operating room to the classroom, demand is up for electronic devices that help us work faster and more efficiently. The drive toward miniaturization and integration is transforming electronic devices into consumer commodities at an alarming rate. Gadgets we once placed on a desk or carried in a briefcase now fit comfortably in a shirt pocket. Even industrial, medical, and military markets, which have previously been low-volume, are shifting to the consumer-based model: higher volume production of smaller systems that perform better and cost less.

Demand for everything from cell phones to printers, insulin infusion pumps to hand-held GPS units, is on the rise. And complicating the market is the growing demand in more recently developed countries for the digital life style. Increased consumer spending power in countries like China, India, and Brazil is driving development, innovation, and customization in many electronic systems markets. Manufacturers have almost insurmountable challenges in meeting market demand and competition for new technology.

The perfect storm of consumer demand converging with design constraints is on the horizon. More demand for electronic devices means more demand for semiconductors. Time to market for high-demand products must be slashed. Design lead times have met the same fate. Design teams are squeezed between a rapidly changing market and the inherent limitations of their design processes. They are reaching the limits of current technology with no clear alternative.

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By Ed Sperling

Low-Power Design sat down to discuss green technology and the future of low-power design with Rich Kapusta, Actel vice president of marketing and business development; Tom Quan, TSMC senior director of EDA and design service marketing, and Brani Buric, Virage Logic executive vice president of marketing and sales. What follows are excerpts of that conversation.

By Ed Sperling

Low-Power Design sat down to discuss green technology and the future of low-power design with Rich Kapusta, Actel vice president of marketing and business development; Tom Quan, TSMC senior director of EDA and design service marketing, and Brani Buric, Virage Logic executive vice president of marketing and sales. What follows are excerpts of that conversation.

LPD: Green is a term that’s been thrown around loosely, overhyped and frequently overused. What does it really mean?

Tom Quan: When we talk about green we think of lower energy devices, and from our perspective it’s silicon-based devices. If you look at the amount of energy consumed by the consumer, computer and communications industries and you calculate how many kilowatts are consumed every day, our goal is to reduce that energy. There’s also the concept of how much carbon dioxide we’re producing and how many trees we need to plant to counteract that, but that’s farther from what we are working on. For TSMC, green also means less silicon waste. If you don’t have good yield, you throw away a lot of die.

Rich Kapusta: As a company, we’re fabless so we’re not actually building chips. But at the end of the day, we can make our customers’ products greener by reducing their energy consumption. We can provide devices to them that are similar to other product in the industry but which use less energy.

Brani Buric: We are down the food chain where we provide IP to people designing ICs. Our role is to enable greener devices that can reduce power consumption in the ecosystem—more devices for more efficient conversion from one energy type to another.

LPD: But really what we’re talking about is low-power, not green, right?

Buric: Low power is one of the enablers for green, but not green per se. There are a lot of ways to have long-lasting portable devices that have power conversion efficiencies of 10x and which expend more power to enable work. That’s different than creating native energy preservation. If you look at the whole concept of moving from high-performance single-threaded processors to multiprocessing, the first time you expend more silicon. But ultimately you create a greener environment once you know how to do that.

LPD: So how do we get there?

Quan: One thing we look at is the amount of devices in each segment. The computer sector is the largest energy consumer. It works out to about 1 trillion watt/hours per day. Communications uses only about 10 billion watt/hours per day. Consumer devices are harder to classify because it includes everything from remote controls to TVs. We also need to distinguish between silicon-based devices and silicon-enabled devices like washing machines and cars. The effect of silicon-enabled devices might be big, because you can control the amount of energy that goes into a building. If you save 1 watt in a device, that’s good, but with a silicon-enabled device you can control 10 kilowatts.

LPD: What is the big hurdle in slicing energy consumption?

Kapusta: At the IC level, we have to take advantage of technology that’s already available. Most of us don’t have our own fabs and we don’t develop our own IP and software, so we’re limited by what we get from our foundries and IP partners. We have to work together to deliver low-power chips. The industry is heading in that direction, but at Actel we’re using an approach that is different from the mainstream. We’re using a flash-based technology instead of SRAM. Outside of Actel, there isn’t as much investment being put into the low-power side. We’d like to see more standby and dynamic current taken out of the process so we can build bigger chips that burn less power.

LPD: How much effect does IP have on this?

Buric: From specification to yield, carefully designed IP—if it is designed with low power in mind and if the guys building the system blocks understand what can be achieved with IP—will have a different implementation. If you have a robust implementation, typically it will go through three re-spins to get it done right. Robust IP can help reduce re-spins, and well-designed IP will increase the mobility of the design. It has evolved from specification to optimization to yield.

LPD: What is the common number of re-spins?

Quan: If you look at mixed signal RF, there are a lot—probably 8 to 10, or more. Digital chips, two to three. If you’re talking about SoCs, probably a few more than that. If you use silicon-proven IP, the number of re-spins goes down. With re-spins you throw away a lot of wafers and masks, and all of that adds to waste. If you can improve that, it’s much greener.

LPD: How often do FPGA designs need re-spins?

Kapusta: It varies by product lines. With the pure digital stuff that’s flash-based, two or three spins. Some of those aren’t full spins. We may need some changes to the mask. Mixed signal is more difficult because you’re dealing with analog and you’re not sure exactly how it’s going to work.

LPD: So given all of this, how do we get fewer re-spins and better designs?

Buric: From a broader perspective, what this means is you have to work more closely with your partners from spec to yield. If you start with your spec without knowing what is out there, you begin with assumptions that may not be optimal. It has to achieve manufacturability in the time frame the customer can live with. This is upside down from years ago, when Carver Mead made the design independent of the manufacturing so you could go up abstraction levels to define your intent. Now we need to work together very closely.

Kapusta: We still see quite a bit of opportunity to do more. We’re trying to optimize the technology where the IP and the process technology aren’t available. We have to do a lot of our own IP and EDA tool development with our foundry partner, which is UMC. But we’re leading the charge on low power and that platform will get us there quicker than using what’s available in the mainstream.

Quan: We invest heavily in the high performance and low-power processes. Recently we’ve been leading with the low power process and the retrofitting it for high performance. Low power is always on everyone’s mind. We had to collaborate with EDA and IP partners to come up with tools and flows and techniques. Now almost every chip employs some low power techniques, and a lot of chips go even further and modify the logic in their design to put more intelligence into the circuits so they can turn on and off blocks. In a cell phone, 90% of the circuits are asleep most of the time. There are only a few active circuits in there.

LPD: Is there much room for improvement?

Quan: People are building in a lot of margins to make sure that what comes out works. But the more margin you have, the more waste you have. It may not be as efficient, there is a lot of timing slack in the design that you don’t need and a lot of time it is overly designed to make sure the spec is met. Collaboration will help.

LPD: Is there more margin because no one is doing everything themselves?

Quan: The processes have variability in terms of the lithography. We capture that in a SPICE model. Now the question is how the designer uses that baseline data to meet the spec. You know the device will change at certain rates. That’s where the margin starts changing because you want that variability. As you build to the IP, the margin gets even bigger. When you’re going up the chain you’re not sure where the variation will be.

Buric: It’s also a fundamental issue of design philosophy that requires margin. Every level of abstraction that you add to your design is essentially a compromise of accuracy of how you present your data. If you were able to simulate your millions of transistors with SPICE then your margin would go down, but you can’t afford that. So you add static timing analysis. At each step, you bring in margins because of uncertainty. If you were to do everything in-house and optimize to the last transistor then you would smaller designs, less margins—and you would be about three years late and you would spent infinitely more energy.

Kapusta: It’s no different for us. We do a lot of work on the simulation and tool side ourselves to help us tweak the IP and rules to tweak the corners. But we’re always limited by the rules, the IP and the margins built into the building blocks.  

By Brian Fuller

Rising demand for mobile products and the march of Moore’s Law have created conditions for a perfect storm that threatens to swamp electronics designs and the market growth those designs target.

The catalyst for that storm is leakage, which worsens the smaller devices become. Even in an “off” state, systems can leak like poorly insulated houses. But as the nation thinks about energy usage on a large—making homes and buildings more energy efficient—the electronics industry also grapples with the best energy-efficient design tools and techniques.

Leakage wasn’t a huge consideration until recent years, with electronics designs not only enabling mobile phone market growth but also bringing mobility and smaller form factors into a host other markets as well, including smart meters, medical devices, and the like. Most of those need to be miserly with power because they’re battery operated. And if they’re not, a greater sensitivity to the impact electronics has on the overall power grid and our national energy consumption is an important consideration.

“Leakage is a huge problem for the industry, and it’s worse as we scale,” says Ted Speers, head of product architecture and planning and fellow at FPGA vendor Actel Corp.

And designer concern is scaling just as quickly. “The (concern) has gone from a 10% problem to a 60% problem in the past four years,” said Steve Carlson a vice president in Cadence’s R&D organization. He is referring to customer-feedback studies that rate the importance of various design issues, such as power, leakage, performance and timing.

There are different types of leakage and scores of methods, tools and technologies to minimize it. We’ll narrow the focus for the purpose of this article to device leakage, and a few ways companies are trying minimize the power drain.

Dr. Leaky, I Presume

 Leakage happens in capacitors as a small amount of current inevitably drains away in an off mode to transistors or diodes. Imperfections in the dielectric material insulating capacitors—which can occur in manufacturing—can contribute to the problem, discharging the capacitor. While the leakage is generally in the micro-ampere range, over time it will drain a portable device’s battery, rendering it useless until it’s recharged.

Leakage increases exponentially the thinner the insulator becomes. Electrons can also leak across semiconductor junctions between heavily doped P-type and N-type semiconductors—the tunneling effect. And they also can leak between the source and drain, when the device should be off—the sub-threshold leakage problem.

To lower threshold voltages, designers squeeze oxides thinner and thinner, but the thinner the oxide, the higher the sub-threshold leakage. Often leakage can be more than half of total power consumption. Some experts have estimated that each process generation increases leakage current by a factor of 10.

Given these physical challenges, it’s a wonder advanced portable devices have any battery life at all. But they do. Battles are waged every day from the transistor level up through system-optimization, each contributing its part to the war on leakage.

Fighting the good fight

Every company has a solution or a methodology to tackle their particular part of the leakage problem, all honed within the context of design tradeoffs. Some approach the problem from an architectural standpoint, some from a materials standpoint, others from a design-optimization standpoint.

“Power is never by itself. It’s part of a larger context,” says Cadence’s Carlson. “There’s a strong interrelationship with performance. To be energy efficient, you have to understand where you are with performance. If you’re meeting performance with margin, you’re wasting energy.”

On the leakage front, he notes, there aren’t “that many” weapons used: Body biasing, and voltage thresholding, among them. Body biasing is one relatively affordable approach to tackling leakage—changing the bias voltage to shift the V_T level.

“You’re not using an ion implant; you’re shifting a voltage domain into another region. There is an area overhead, and it’s more complex to verify,” he said.

Another area of innovative is in the process itself—using different dielectric value metal gates in the process to control.

“You get a combination of different materials at different layers that can dramatically reduced leakage,” Carlson said. “That’s a big boon to design community.” But at the same time, “You can’t count on that because there are manufacturability issues.”

Research done by NEC has found that body biasing can reduce sub-threshold leakage by an order of magnitude and that certain high-k gate dielectric materials can cut standby power consumption by up to 80 percent.

The Material World

Materials play a key role in managing leakage at the device level. One of the emerging players (and choices) in the leakage battle is silicon-on-insulator (SOI), an alternative to bulk silicon. At 45nm and 32nm, features within the device are both very tiny and can be subject to manufacturing anomalies, at least when using bulk silicon.

“The definition of the poly line that defines the gate gets rough. You get points where it’s narrower than you intended,” says Horacio Mendez, a former design engineer with Freescale and Motorola, who now heads the 26-member SOI Consortium, in Austin, Texas.

Using bulk silicon, while less costly as a material than SOI, can force designers to implant their transistors at the channel and under the gate to control leakage, and that adds cost to the design.

But SOI has a different charging mechanism than bulk silicon and therefore has better properties to manage leakage, Mendez said.

“At 180 and 130nm, SOI was used for high-frequency applications. IBM used it for servers,” Mendez said. “Then as technology shrunk more, people wanted to trade that frequency for lowering power, because power was becoming more of a problem than frequency. So you have less leakage, and that allows you to get higher drive current.” And higher drive current allows a designer to reduce power.

A Look from the Architectural Level

As SOI tries to become a more attractive and cost-effective option for a broad range of companies (Mendez sees price-parity with bulk at the 22nm node), other companies are addressing device leakage at the architecture level.

Actel has positioned itself in recent years as a low-power provider by marketing the flash-based nature of its programmable-logic devices. The FPGA market is generally divided into SRAM-based architectures and flash-based architectures. With the former approach, SRAMs are laden with transistors and therefore more prone to the leakage issues earlier discussed, such quantum tunneling and sub-threshold leakage.

The benefit of the SRAM architecture is it’s a less expensive process than the flash-based architectures, and the end device can be faster. If a vendor is targeting a market that’s not sensitive to power, say an industrial application that is always on, that approach might be beneficial.

FPGAs that contain a nonvolatile FPGA array can have significantly lower static power than SRAM-based solutions, making them an attractive alternative for power-sensitive applications. In fact, in some modes, such FPGAs consume as little as 5 μW. 

“The real pressure is coming from the Qualcomms and people making processors and stuff for cell phones,” Actel’s Speers says. “My impression with talking with major cell phones guys is that power is secondary after cost. But there are guys really thinking about the phone and trying to manage every microwatt in a cell phone.”

So the battle is being waged on all fronts by everyone in the semiconductor design chain, from device physicists to architects to materials and equipment vendors to system designers. Ultimately, optimization at the system level can deliver the biggest power improvement bang for the buck, but it all starts at the bottom.

“If we said we’re going to make hardware-software tradeoffs to come up with an optimal energy profile for a device, you can’t do it without the bottom up data,” Cadence’s Carlson says. “In terms of baseline analysis capabilities and techniques, on a scale of one to 10, we’re a six or a seven. The infrastructure is there”