By Ed Sperling
For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change.

Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signals. The issue seemed to die down after that. But at 32nm it has shown up again, driven this time by a multitude of problems—some new, some old, and all of them made worse because there are fewer alternatives.

“The problem has always been there,” said Navraj Nandra, director of analog/mixed signal marketing at Synopsys. “But it has suddenly gotten worse because of the design interfaces at higher speeds. At 40nm and 28nm transistors switch faster. We also have 8 Gbps PCI Express [generation] 3 and DDR3. You have multiple lane configurations with PCI Express. Graphics cards use eight lanes. We’re connecting by 16s. But PCI can use 96 lanes.”

That’s a lot of noise on an advanced chip, where the wires are thinner and thinner at each node and components are packed together more tightly. If a single atom of deposition can change the functionality of a transistor, imagine what can happen when you start adding in parasitics and electromigration.

Power corrupts
If the only thing that changed in an SoC was the manufacturing process—doubling the number of transistors on a piece of silicon for every rev of Moore’s Law—then lowering the voltage would actually improve signal integrity. It isn’t that simple, however.

Adding in multiple voltage supplies increases the noise level on the chip. “At 28nm and beyond we’re seeing 800 millivolt supply voltages and threshold voltages of 300 millivolts,” said Aveek Sarkar, vice president of support at Apache Design Solutions. “Not only is the noise on the supply voltage increasing at each node, but the sensitivity is also magnified.”

The current is faster, the drive strength is higher, and voltage noise is higher. And the problem gets worse as you add in power gating and multiple power islands, all turning on and off unpredictably and intermittently in close proximity to each other.

It also gets worse when you bring the voltage regulators onto the chip from the PCB.
“That becomes a problem if you want multiple power domains on a chip,” said Qi Wang, technology marketing group director at Cadence. “The regulator is analog and noise becomes a problem. You’ve got big digital areas that generate noise. That can be a big issue, especially for the voltage regulator. People are now overdesigning chips and that’s creating more of a problem as more and more analog is put on the die.”

What’s in the package?
At least part of what will have to change in many designs is the package, which frequently is an afterthought for the total design and most often based on price rather than its effect on the operation of an SoC.

“People want to put in a cost-effective package to cut their costs, but that kind of package was not designed to handle high-speed I/O,” said Synopsys’ Nandra.

That can create a huge problem for signal integrity. But packaging is typically the victim of a silo effect. It’s not part of the up-front architectural decision and it’s not part of the SoC model being created.

“The focus is on the semi design, but the package design is just as important,” said Apache’s Sarkar. “There are no so many different packages that it’s confusing. You have to worry about whether it’s four layers or two layers, and if you have 80 different power domains the package can get very complex. We’re seeing wireless chip packages now that are not uniform.”

Living in a material world
The substrate material is equally important in signal integrity. CMOS has been getting mixed reviews, in part because it’s a proven low-cost material with excellent conductivity. But it’s not especially good for mixed-signal applications at advanced nodes. So while Intel may get away with using it for a predominantly digital processor, an SoC has completely different needs—and different economics.

Materials such as silicon on insulator and gallium nitride do improve signal integrity, but that improvement comes at a price. SoI is the less expensive of the alternatives, and has been proven to work in designs since 65nm by IBM, AMD, and some of the partners in the Common Platform ecosystem.

The problem is that architects and designers don’t necessarily know what kind of substrate or package they will need up front because the IP they buy from third parties doesn’t include information about noise.

“IP vendors need to provide enough data constraints in their libraries to say how the IP can be used properly,” said Cadence’s Wang. “You need to know, for example, ‘For this ping it can be this close to a digital component,’ or ‘Do you put this within this distance of I/O.’

He noted this is an important new wrinkle in IP integration. “’We need a holistic solution for the ecosystem of IP providers. We need a better model, and we need EDA tools that are better and faster at noise analysis.”

3D stacking
What has many experts particularly worried is the effect of 3D stacking on signal integrity. While most of the focus has been on thermal effects—hot spots caused by putting two or more chips together—there is a magnified effect for noise.

Vendors such as Qualcomm, Freescale and IBM expect 3D stacking to begin rolling out in late 2011 or early 2012—roughly one year from now. From there the approach is expected to grow rapidly, in large part because it shortens the distances that signals need to travel, which in turn boosts performance while lowering the power needed to drive those signals.

But moving the mass SoC market in this direction compounds many of the issues for signal integrity that exist with packaging, substrates and proximity—while adding new ones.

“With a through-silicon via, the power noise is much worse,” said Apache’s Sarkar. “TSVs brings signals closer together, but the silicon substrate is not stacked in terms of coupling with the TSV. So how do you model this?”

Synopsys’ Nandra noted that 3D shifts the problem from the packaging inside the SoC. “With a stack die you’re communicating inside the die, so the I/O problem is less,” he said. “But within the die now you have interactions between platforms. Basically you’ve just shifted the problem.”

Conclusions
None of this has been lost on the tools vendors. Many are scrambling to bring new tools to market that can analyze noise, heat, IP integration problems, as well as the ability to model all of it.

But these are complex issues. There is no single tool that can do everything, and so far these are well outside of existing design flows. Moreover, there are no standards that effectively address the dynamics of using IP in a high-density, highly noisy environment that includes voltage changes, rapid power-up and power-down modes, SerDes and high-speed I/O, and the effects of packaging and substrates.

These are challenging problems that have to be deal with up front and together, both by design teams and by ecosystems that include IP vendors and foundries. And so far, semiconductor makers have merely scratched the surface.

By Ed Sperling
Andes Technology, a Taiwanese maker of SoCs and processor IP, adopted Cadence’s digital front-end low-power design flow, which is based on the Common Power Format. Score one for CPF.

Toshiba Information Systems expanded its adoption and deployment of Mentor’s Catapult C for high-level synthesis. What’s interesting about this deal is Toshiba’s shift to untimed C++ and System C from an RTL-based design, which the company says is unproductive.

Synopsys completed its acquisition of Virage Logic, greatly expanding Synopsys’ IP portfolio from standard interfaces to everything from memory to processor cores and logic libraries.

GlobalFoundries held its first conference, which was largely a coming-out party for the combined company that includes pieces from AMD and Chartered Semiconductor. There were several themes of note. First, GlobalFoundries is gate-first high k/metal gate, while TSMC and Intel use gate last. For most customers, that means it becomes even harder to move from one foundry to another. Second, GlobalFoundries sees this as a strong ecosystem play. It has lined up ARM—which is playing across both foundries—as well as Freescale for its 90nm flash memory.
And finally, the company introduced a 28nm analog-mixed signal flow development kit.

In the memory space, memory resistors, aka memristors, are gaining attention. The technology is considered faster than flash while also drawing low power. Solid state memory already lowers the amount of power being used because there are no moving parts, but memristor reportedly uses as little as one tenth the power of flash. HP is teaming up with Hynix to develop what it calls ReRAM, which should put a big dent into the DRAM market.

By John Blyler
Low-Power Engineering sat down with key members of the Power.Org Power Architecture community to discuss today’s leading processor issues. Power Architecture is the general term that denotes all “Performance Optimization With Enhanced RISC” (POWER), PowerPC and Cell processor technologies. The Power.Org interviews included: Kaveh Massoudian, CTO of Power.org Strategic Alliance at IBM; Vinay Ravuri, vice president and general manager of the processor business unit for Applied Micro (formerly AMCC); Dac Pham, fellow and director of Power Architecture cores and platforms at Freescale; and Christina Rodriguez, director of multicore software at LSI. What follows are excerpts from those interviews.

LPE: This is the era of multicore processors. How is that changing both single- and multi-threaded code developments?
Pham: Single-threaded performance is still important for all of the legacy code that cannot be parallelized. If you have more than about 10% of sequential code in your program, then Amdahl’s Law shows us that anything over eight cores has diminishing value. Still, when you design a symmetrical multicore system, you have to make both the sequential and parallel sides happy. In the networking world, this divides rough into data- and control-plane applications. Switching, such as packet forwarding, is performed in the data plane. Routing of packets is performed in the control plane. The data plane lends itself more to parallelism while the control plane tends to be more sequential.
Ravuri: From a high-level, application-space viewpoint, multicore systems are the future. The industry will not go back to single-core devices. I see potentially multiple threads across multiple cores. For example, consider two cores, where each core could have two threads. This would give you four threads in two cores, which is something new in the embedded space.
Massoudian: In 2000 Power Architecture was the first true multicore platform—dual core on the same die—on the market with the Power4. Today, IBM’s Power7 brought the first eight-core chip into the industry. But multicore itself isn’t as important as multithreading and simultaneous multithreading. Each core in an eight-core Power7 can simultaneously run four independent threads. This means that each core is effectively four cores. Intel’s Nehalem can only handle two simultaneous threads per core. Multithreading introduces many challenges in both the system software (operating-system kernel and device drivers) and higher-level application programs. Multithreading is a challenge for programming in general. Multicore technology just extends the multithreading problem to multiple cores. It is really still the same problem. How do you parallelize software? Algorithm architects and software programmers are all human, which means that they tend to think in a serial fashion. That is why all software tends to be sequential.

LPE: How does Power Architecture enable the implementation of different processor types, from basic embedded to hybrid servers, full servers, and high-end mainframe systems?
Ravuri: Some clarification is needed here, since “server” is a big, generic term. Power Architecture has an embedded instruction-set specification known as Book 3E. Similarly, Book 3X is a server specification used by companies like IBM. It is possible to take the embedded specification and produce a server chip, although that chip would not be strong enough to work as a server. The requirements between an embedded computer and a server are quite different from a power, performance and price perspective. You could not make embedded devices and then say that they would work seamlessly in the server market. Power Architecture companies like Freescale, LSI, and Applied Micro are in the embedded market.
Massoudian: A hybrid server usually refers to a general-purpose computer that has been augmented with accelerator co-processors for different applications ranging from security for encryption and decryption, Java engines, XML parsing, vector instructions, graphics or networking offloaded functions, deep packet inspections, etc. Many things become possible if you process with a dedicated hardware-accelerator engine versus software that runs on a general-purpose processor. This is typically what is meant by a hybrid server. We don’t think that any one processor architecture can really be optimized for every workload. That is why we are proponents of heterogeneity in the data center as well as in computing in general. Power Architecture was a leader in hybrid computing in the early 1990s when Motorola, followed by Freescale, introduced vector unit and co-processors in a multicore approach. In terms of heterogeneity, the Power Architecture-based Cell Broadband Engine was jointly developed by IBM, Toshiba, and Sony. The Cell greatly accelerated multimedia- and vector-processing applications. Recently, IBM announced the world’s first supercomputer to break the petaflop performance mark. This supercomputer combined AMD’s Opteron processor with a Cell, which was an example of the heterogeneity and hybrid type of architecture working together.
Pham: General-purpose processors are used for networking tasks like acceleration. This is one area where Power Architecture has dominated the market. Networking systems are supported by a variety of operating systems (OSs) including proprietary ones like Cisco’s Internetworking OS (IOS), which is used for their routers and switches. A significant design challenge involves matching the right type of performance accelerators to the right applications. While accelerators may present additional coding challenges, they also improve power performance. The most optimized accelerators are hardwired into the chip’s gates by a designer who really understands the target application. A more programmable approach would be software (microcode) written to a small processor engine that can handle micro-programs with a lot of big libraries tailored to a particular type of acceleration. People do that in graphics, security, and packet processing in the wireless baseband architecture.

LPE: Competitors in the processor market are aggressive regarding virtualization. How do you view virtualization in both the server and embedded spaces?
Ravuri: Virtualization is important. Data centers are fully virtualized, which focuses mainly on the server market. However, we are seeing the same virtualization trend in the embedded-appliance space. Virtualization allows you to run multiple OSes, partition resources, and segment-segregated users. There are multiple ways to implement virtualization ranging from software- and hardware-based methods to power-based and pure virtualization. The Power Architecture specification supports virtualization through hypervisor technology.
Rodriguez: We have made the Power Architecture part of our virtual-pipeline platform. The virtual pipeline is a set of on-chip interconnects that links all of the cores. It is a message-passing architecture that provides a logical-layer link and controls the movement of data packets. In essence, it allows designers to have a flexible data pipeline anywhere on the chip. Data packets can be processed by the Power Architecture cores, our processing engines, or hardware accelerators. The idea of the virtual pipeline is a very fast path, so it doesn’t become a gatekeeper between the cores.

LPE: What do you see as the trends for embedded low-power and software design?
Massoudian: In the embedded space, everyone is doing clock and power gating to lower power consumption. Power Architecture is also doing a lot of dynamic power management using voltage and frequency scaling. Software is used to automatically monitor the chip to achieve the best possible performance while using the least amount of power.
Ravuri: There is a huge code base that has been written for various processor architectures. In the consumer market, that code base is written for ARM processors. In the enterprise-telecommunications industry, PowerPC processors are dominant. That code base is a big plus for PowerPC because you have large network companies like Cisco with huge amounts of legacy code written around proprietary OSes. These companies don’t want to disturb that code base. But PowerPC needs to embrace newer trends, such as Google’s Android, which is an open-source OS for cell phones, netbooks, tablets, and other devices. In the future, these trends will migrate to other devices that will become the new growth vectors for the embedded market. To embrace these trends will require a processing architecture that is flexible and supports a growing ecosystem. In the short term, it means the Power Architecture must continue to provide a port for Android to compete with non-Power Architecture processors. By port, I mean an optimized, high-performance hardware platform to run Android. Of course, the compiler and related software-development tools must also be available.

By Ed Sperling
ARM took a new tack in its war with Intel. The company is working on a Green Cloud Services project using the ARM architecture in conjunction with Nokia, IMEC, EPFL and the University of Cypress to create a 3D package with low-power processing. This is particularly interesting in light of gamers using Intel Atom-based servers.

Along the same power-saving lines, Actel introduced its power management solution for its SmartFusion mixed signal FPGA, complete with a reference design and a configurator for power sequencing and trimming. Given Actel’s focus on low power in its other chips, this isn’t all that surprising.

Also on the low-power front, Virage Logic introduced a big update of the open source GNU and Linux toolchains for its ARC processors, which will soon belong to Synopsys. That puts Synopsys firmly into the open source world, as well, with interesting implications.

Arteris joined forces with other EDA and IP vendors supporting TSMC Reference Flow 11, this time with network on chip interconnect IP. This is more like networking the industry on chip.

eSilicon will provide logistics services and production operations to Ember and Pixim. This is an interesting extension of supply chain expertise.

Mentor Graphics rolled out its commercial embedded Linux platform for Freescale, building on a strategic alliance the two had signed in April.

Mentor also won a couple deals with Mindtree for its Questa functional verification and with Autoliv for machine programming.

Both Synopsys and Cadence trumpeted successes with their products. Cadence global services enabled a 65nm TD-LTE baseband chip from Innofidei, a company with operations in Taiwan and Beijing. Synopsys, meanwhile, demonstrated interoperability between DesignWare IP for PCI Express 3.0. The company also awarded the Tenzing Norgay interoperability achievement award to IEEE-ISTO. We’re not sure what the famed Sherpa had to do with interoperability, but congrats.

By Ed Sperling
ARM, Freescale, IBM, Samsung, ST-Ericsson and Texas Instruments teamed up to create “Linaro,” an open-source software engineering company. The stated goal is to speed the development of Linux tools and foundation software. While this is great for large processors, the real question is just how much Linux technology will be scaled down. In many applications, size matters, and being able to work with open source software in a smaller footprint is a big plus when it comes to power issues.

MIPS added symmetric multiprocessing support for the Android platform using multicore MIPS SoCs. This gets particularly interesting because in addition to multi-threaded applications, there is a trend to dedicate specific functions for cores. The possibilities are enormous, both in terms of functionality and more efficient power utilization.

Mentor Graphics updated its verification lineup just in time for DAC. The company rolled out version 3 of its O-In formal verification, adding better support for mixed language design and tighter integration with its Questa platform. The company also released a O-In CDC update for clock-domain crossing verification. While these are interesting releases in their own right, it looks particularly interesting for SiP and 3D stacking.

Synopsys, meanwhile, rolled out high-level synthesis support for Xilinx’s Virtex-6 FPGAs. Design of FPGAs used to be relatively straightforward, but at advanced process nodes they encounter the same headaches that SoCs do—area, power, performance and verification.

Sound quality may be the next big selling point in the PC and netbook space, along with battery life and I/O speed. ASUS is betting the bank on Virage Logic’s Sonic Focus as a differentiator, complete with new enhancements. So much for the tinny-sounding speakers that make it next to impossible to understand anything.

This just in: A low-power transmission of NBC’s Washington, D.C., broadcast via TV translators is going away. Residents in Virginia received a notice from Qualcomm—which specializes in low-power chips—that the service interferes with new wireless services. Thank the Northern Virginia Daily for reporting this one.

Freescale has jumped into the gallium arsenide world with four chips optimized for base-station equipment. Yes, it really is true. Bulk CMOS is running out of steam for many applications at advanced nodes.

Apple’s iPad reportedly is getting a memory boost. AppleInsider reports that at the heart of the device is an ARM processor. That explains the 10 hours of battery life.

By Ed Sperling

The addition of multiple cores inside of computers has created an enormous opportunity for virtualization. Instead of running one operating system or one application, a single server or multicore PC can run multiple virtualized OSes on a single machine at the same time.

From the standpoint of energy efficiency, this has been a huge gain in data centers and the corporate enterprise. With most servers averaging 10% to 15% utilization, rather than the recommended 80%, one multicore serer running a virtualization layer could replace as many as eight less efficient single-core servers. That means less power to run applications, less power consumption by the new machines, and less power needed to cool server racks.

From an economic standpoint, this all makes sense. But that’s not the end of the road for virtualization. By the end of this year, that same technology will show up in smart phone prototypes, with products using this technology expected to hit the shelves in 2011.

“Our strategy has been that, over a period of time, mobile products would have a mobile interface,” said Srinivas Krishnamurti, director of product management and market development at VMware. “The goal is not just to shrink our existing technology to a mobile PC.”

Much of this has been under tight wraps since VMware bought Trango Virtual Processors in 2008. There has been much speculation in the mobile world about what all this means and how it will unfold, but little information. Details are now starting to emerge.

Krishnamurti said one use is allowing non-standard devices like the iPhone or Android device to be supported by corporate IT departments by using one of the cores for connecting to the enterprise. When that core is in use, access to other cores is restricted. But the next phases of development become far more interesting from a power-management standpoint.

Following the data center
Within the enterprise data center, one of the newer applications of virtualization technology is the ability to move processing onto machines, or even cores, that are underutilized and shut down any processors that are not in use. Entire regions of the data center can be shut down on weekends, for example, and loads concentrated where power is already being used. For a large company, that can result in savings of tens of millions of dollars annually.

In a mobile Internet device, that same strategy can be used to save battery. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the ability to partition for Linux and proprietary real-time operating systems opens up all sorts of possibilities for improving power management—particularly as more cores are added into the processors in these devices.

“Whatever we do at the infrastructure level will get down to the device level,” Su said. “We will see it on consumer devices soon.”

Taking full advantage of virtual machines in mobile Internet devices, however, requires that much of the power management be built into the software. A graphics-intensive application such as a game, for example, needs far more power than instant messaging. While those types of applications can be hard-wired into different sizes of cores with different voltages, allowing thyem to take advantage of whatever core becomes available with a virtual machine requires flexibility in the voltage supplied to the virtual machine running that application, regardless of what core it’s running on. There may be a fixed number of possibilities, or there may be a range of possibilities. So far, none of that has been fully worked out.

Also not fully worked out is how to verify the systems using this kind of technology. While virtualization has thrived in the enterprise, where machines are plugged into the power grid, handheld devices have had to rely on much more creative and painful techniques such as power gating, power islands and various on-off states. How virtualization will work with those states, and how devices will be verified, remains to be seen. For example, will virtualization supplant power islands altogether or be part of the strategy for turning parts of the chip on and off? And will virtualization ultimately require more power than power islands and right-sized cores with tightly coupled software?

Krishnamurti said VMware has been spending a lot of time on slimming down the hypervisor level in the virtualization layer, as well. The current layer for servers takes up about 32 megabytes of storage. In mobile phones, the new layer is expected to take up only 20 to 30 kilobytes. He declined to discuss more details, saying that VMware has a number of patents pending in this field.

“But from all the testing we’ve done so far, the power overhead is not significant,” he said. “The biggest drain on these devices is still the display.”

By Ed Sperling
Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago.

Perhaps even more astounding is the price drop on these devices. A basic cell phone five years ago cost hundreds of dollars. Add to that an MP3 player for a few hundred dollars, a GPS system for a few hundred more, and portable gaming systems fore even more. All of that now runs on a single chip, often at the most advanced process nodes where real estate is plentiful.

But getting to this point, and moving further is showing pain points across the supply chain—particularly as power becomes a critical part of every facet of the design. What used to be a simple tradeoff between area and performance is now tilted heavily in favor of power. Software that used to be written independently of the hardware now must be written in conjunction with the hardware—even at the application level.

All semiconductors begin with the architecture and the design. But devices like a mobile Internet device begin in reverse—they gauge user demand, weigh the cost of development, and develop the spec that feeds into the supply chain all the way down to the semiconductor.

No pain, no gain
What’s interesting is just how many pain points are scattered throughout the supply chain that are affected by power. At the uppermost level, the biggest issues are business context and time to market. The Blackberry, made by Research In Motion, developed a killer application for corporate e-mail that allowed it to initially sew up the corporate market. The Apple iPhone added a slew of other applications, with e-mail initially almost a secondary issue.

But what plagued both devices, at least initially, was the limited battery life. Those issues are improving, thanks to some enormous leaps in engineering in every facet of the devices. Even PCs can now last most of the day, depending upon the applications being used.

Sandwiched between the high-resolution screens and the lithium-ion batteries, though, those gains haven’t come easily—and they may be significantly tougher to achieve at each future rev of the components inside those devices.

“Our biggest challenge isn’t even in the engineering,” said Nick Ilyadis, chief technology officer for Broadcom’s enterprise networking group. “It’s customer requirements changing on the fly. OEMs come in and change the features very late in the design cycle—sometimes right before tapeout. They’re developing Brand Y and they see Brand X change their product at the last minute.”

One solution is being agile—making changes whenever possible in firmware or software. A second is being aware of the market trends. “Our customers tell us what they want to tell us, but their holding back can create a problem,” Ilyadis said. “Our solution has been to talk to the end user. We need to get to the end user to be pre-emptive.”

On mobile platforms, Broadcom has developed its own power management capabilities. It also has been working with power islands for several generations, allowing changes in performance and power on a per-cell basis.

But at each node, there is more to put on the chip—and a far greater number of issues such as leakage and mixed-signal integration and verification. Lisa Su, senior vice president and general manager of Freescale’s networking and multimedia division, said the big challenge in her organization is how to put a base station on a chip.

“Integration is the problem,” she said. “Multicore communications processors are quite different from a PC. You’ve got up to eight cores and some of them are used for accelerating the other cores. So you’ve got to integrate those accelerators. The question is how do you optimize the processing performance and the acceleration without adding more power. You can put eight cores on a piece of silicon, but the challenge is to get eight times the performance.”

Su said that the challenge is figuring out what to integrate and what not to ingegrate. “How do you get 24 hours of battery life,” she said. “There’s a very complex tradeoff between hard wired and programmable. For this, hardware-software co-optimization is critical, and there’s a lot of momentum in this area. We’ve grown by leaps and bounds in this area. If you take the same piece of hardware and software and you optimize the software, you can increase battery life by two times.”

Doing more with less
The problems felt at the board-level and the SoC-level are only magnified as you move down a couple of notches into the blocks and technologies that reside on a piece of silicon.

“Low power touches on everything you do, from the logic through the physical process and up into the software,” said George Zafiropoulos, vice president of solutions marketing at Synopsys. “You can do everything to make the hardware efficient, but power efficiency also now depends on the behavior of the software.”

Zafiropoulos noted that even at the top of the product development cycle, power is now a major consideration. “It’s often a question of cost and the difficulty of implementation vs. the benefit of low power,” he said. “To make a chip with 30% less power is great, but if you leave the iPhone modem on you’re going to blow the power budget. You have to address this at the system and the software level as well as the component level.”

Chipmakers also have to bring together teams of hardware and software developers to work in tandem rather than independently, which is not something that comes easily to them. Broadcom has created what it calls “chip leads,” who are engineers that can bridge the gap between the hardware and software engineers. They basically work as translators back and forth between the teams as they move down the line toward tapeout.

Zafiropoulos said that has been a big barrier for some companies. “Power is forcing conversations between software and hardware development teams,” he said. “This started on the process side with CMOS. Then it moved to logic. In the last 10 years, the design circuit was gate clocked. The next wave will be software. The problem is that every time you push the limit on power, the response from engineers is to guard band. They over-engineer, which takes more power.”

Connection overload
Part of what has made devices so power hungry also is a result of the I/O—the connection to the outside world. Every device needs to be connected, and the more bandwidth the less wait time for downloading everything from text to videos.

“One of the grand challenges we’re facing is layer one in these devices—the radio receiver and transmitter,” said Chris Rowen, Tensilica’s CTO. “Bandwidth is an order of magnitude higher, but the power budget is 50% lower. How do you get a factor of 15 in energy efficiency and still include the supporting standards.”

He said this is particularly troublesome with LTE, which holds the promise for lower power but so far has never been implemented. “The challenge is how you get there in the first place, how you get there quickly, and how you get there within the power envelope.”

Part of the challenge is also in the basic wiring structure. Charles Janac, chairman and CEO of network-on-chip vendor Arteris, said that from a physical design standpoint there simply are too many wires. “That’s causing congestion points and problems with timing closure,” Janac said. “Then we’re stuffing hundreds of thousands of transactions per second down those wires.”

Those wires also get thinner at each new process node. Janac said the solution is a single point-to-point connection rather than a multiple wire mesh structure. While the mesh bus structure sufficed at older process nodes, it doesn’t have the speed or the flexibility if changes need to be made to the design—which they often do.

Hot spots
One issue few people are talking about—but which many companies are watching, somewhat warily—is what happens when there are too many connections. Connections internally are problematic, but the ones outside the chip generate heat.

“Down the road, there are still serious concerns about temperature,” said Jim Davis, vice president of software and systems engineering at Actel. “The parts are getting bigger and bigger because we’re basically getting gates for free, but the I/O’s don’t scale with the gates.”

Add to that static power leakage, which is becoming worse at each new process node, and the amount of heat that needs to be dealt with can cause serious problems.

Some of these problems, most notably the analog design portions of a chip, are actually better dealt with at older process geometries. In fact, there is almost no advantage to doing analog at advanced process nodes except to keep it on the same piece of silicon. That has prompted a variety of different responses—everything from programmable analog on an FPGA to high-speed interconnects between chips and research into 3D stacking.

The low-power crystal ball
The list of pain points goes on and on. But what is becoming clear to more people—and companies like IBM have been preaching this for most of the decade—is that design needs to become more holistic. That’s easier at an integrated device manufacturer like IBM or Intel, however, than in a disaggregated commercial chip development world.

“Low power has to be dealt with in a holistic manner,” said Nizar Abdallah, Actel’s director of engineering. “You need to deal with all possible angles at the same time, starting with the technology and the process. Then you have to look at the features, fabric and modes.”

For fabless companies, this requires coordination not only of internal hardware and software teams, but with the architectural teams of all companies in the supply chain and all the tools vendors that service the supply chain—something that points firmly toward an industry filled with more standards.

“In the beginning of chip development, the only people who could attack the problem were the ones who could design from scratch,” said Cary Chin, director of technical marketing for low power solutions at Synopsys. “Standards allowed more companies to create chips. Low power is headed in that direction. And what is successful is not always at the bleeding edge.”

By Cheryl Ajluni
Power conversion is a general term that refers to a system or device producing an output that is different than its input. It can assume many forms—everything from an inverter to an isolated power supply, uninterruptable power supply (UPS), or AC/DC converter. Power conversion, like low-power design, is fairly commonplace these days. Nevertheless, recent advances in digital power solutions (e.g., the ability to address high-frequency switch-mode operation) are making it much more palatable for engineering low power, portable applications.

In an attempt to gain a better understanding of power conversion and its relation to low-power engineering, LPE recently posed a few questions to Don Alfano, applications director for power products at Silicon Labs.

LPE: How is power conversion beneficial to enabling low-power design?
Alfano: With all of the attention focused on ‘going green,’ low-power design is politically and economically very important. However, the real reason low-power design can be beneficial is based more in practice than populist opinion. One obvious example lies in battery-operated systems such as iPods, cell phones, GPS systems, and so on. The operating time of these systems is directly related to the system power consumption and battery capacity. Since higher capacity batteries are typically bulkier, it is more desirable to limit operating power than to increase battery capacity.

Another example involves consumer devices that are powered by the AC line. Devices such as flat-panel TVs, desktop PCs and consumer audio devices consume relatively large amounts of power due to their sheer volume (e.g., 1000 watts per TV x 5 million TVs = 5 billion watts of electricity). A mere 10% improvement in operating efficiency can save 500 million watts of power, and how many tons of coal does it take to make that much power? The answer is a lot.

It’s because of this that standby power requirements (e.g., power consumed when the TV is “off”) for these devices have come under scrutiny by certification agencies such as EnergyStar. Consider that the average TV consumes 10 watts of power when “off.” Applying the same 5 million TV sets, the power consumed would be 50 million watts. Reducing standby power to the new standard of 1 watt results in a savings of 45 million watts of power. The bottom line: low-power design extends the operating time of battery-operated devices, while reducing battery weight. Low-power design also results in greater operating economy when implemented in AC line-powered devices.

Are there any obstacles or challenges that engineers need to be aware of in applications requiring power-conversion technology, such as ac-dc or dc-dc?
Both linear and switch-mode power conversion systems have been around for decades, and their control technologies are well-developed. That being said, one common obstacle is the tradeoff between the emission of electromagnetic interference (EMI) and efficiency. In any power system design, the engineer strives for the highest efficiency. However, certain portions of the circuit can act as parasitic “radio transmitters,” causing EMI that can be induced into other devices. A classic example is the noise that appeared on a television screen when an old-time vacuum cleaner was turned on. Federal Communications Commission (FCC) regulations now prohibit such emissions, forcing the power system designer to add parts into his design that ‘snub’ (eliminate) these emissions. Such circuits dissipate power and degrade efficiency.

Another classic tradeoff is efficiency vs. physical size. Switch-mode power systems become smaller when they are designed to operate at high frequencies. However, these high frequencies cause lower operating efficiency. Reducing the operating frequency results in higher efficiency but requires larger, bulkier transformers, which adds size, cost and weight.

Have there been any recent advances in power-conversion technologies or techniques?
Yes, digital power control is catching on after a slow start. Digital power effectively uses digital computer technology to control power conversion instead of traditional analog control circuits. Digital power control can enable more sophisticated power-conversion algorithms that can increase efficiency and system responsiveness while (ultimately) lowering cost. Another trend is the use of analog resonant power-conversion control circuits, which can boost efficiency and decrease system cost. These are becoming popular in consumer electronics like flat panel TVs.

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Alfano’s comments serve to underscore an important point—that digital power solutions and digital power control are highly relevant topics these days (See figure 1). One reason is that by minimizing high-speed circuit components and leveraging smaller process geometries, digital power solutions have simply become more practical for portable devices. Additionally, since digital power solutions integrate power control and power management, they are much more flexible than analog solutions and able to address higher levels of complexity, including the different operational modes of portable applications.

Figure 1. One example of a digital power solution comes from Microchip. It offers two device families for digital power applications: the dsPIC30F and dsPIC33F (pictured here) SMPS and digital-power conversion families. These devices include peripherals specifically designed for power conversion. Peripherals such as a high-speed PWM, ADC and analog comparators can be tied together using an internal configurable control fabric that enables them to interact directly with one another, resulting in significant performance gains in digital power applications.

Alfano adds that, “As its name implies, digital power control is based on digital processor technology. As such, the digital power controller can make informed control decisions based on multiple, real-time data it continuously gathers. For example, the digital power controller can measure various key operating parameters within the system such as input voltage and output current, then dynamically adjust or otherwise influence the operation of internal system components so as to maximize system operating efficiency (e.g., minimize power loss). In so doing, the digital power controller has the ability to maximize system efficiency across the power conversion system’s entire operating range.”

In addition to allowing the designer to adapt to different operating parameters, digital power control also has the ability to switch between compensators as a function of operational modes. Phase management, such as phase shedding and adding based on load requirements, is another capability that is possible with digital power control and one that is especially beneficial for applications that utilize multiphase regulators.

With portable applications continuing to weave their way through society, the current focus on low-power design shows no signs of letting up any time soon. Power conversion, digital power solutions and digital power control will therefore continue to be topics of great interest to designers. Such solutions offer flexibility as well as the ability to increase system efficiency—features which are highly prized in today’s portable market.

More information on power conversion, digital power solutions and digital power control is available from an array of companies working in this arena. Among those companies are Freescale, Intel, International Rectifier, Intersil, Microchip, Silicon Labs, STMicroelectronics and Texas Instruments.

By Ed Sperling

If you can’t get the application software to run on multiple processors, then at least you can get multiple processors to run the software.

That’s the latest thinking in multicore design, and the potential for saving power is huge. Instead of running a processor core that’s either on or off, it allows different cores to work almost like a variable speed motor. When the power is needed, more cores can be turned on to help with the processing. When it’s not, those cores can sleep.

If this sounds familiar, it should. The reasons for doing it are different, but this is largely the same tack taken by companies like Intel back in the 1990s with the 387 and 487 co-processors. The difference was those co-processors were added to boost performance in mathematical functions rather than actually reduce power. The 387 and 487 were always on, and always drawing current.

Fast forward a couple decades and that same approach is being applied in the multicore world. It’s impossible to keep cranking up the processor clock speed without burning up the chip, so more cores are being added. The initial thinking was that the software developers would be able to get more applications running on multiple cores, and while that works for many commercial and scientific applications it doesn’t work in the consumer or personal computing world.

But the processing power can be extended without actually parsing the application across those cores. That helps explain Intel’s Turbo Mode boost, which will be released in the next major release of its architecture. And it helps explain how other companies are starting to address this problem.

Subramanyam Dronamraju, director of business development for software products in Freescale’s Networking & Multimedia Group, said the current approach is to match performance in a VPN router, for example, to whether an application is fully loaded and using more tunnels or whether it’s using a relatively light load.

“What we’re addressing with this approach is data path acceleration,” Dronamraju said. “We’re mixing and matching symmetrical and asymmetrical multiprocessing. It can run on one core, two cores or four cores. And that flexibility isn’t just in the processing. If you have multiple images instead of a single image, you need more memory. With asymmetrical flow management, you can direct the flow into cores.”

Those cores also can run at different frequencies, which increases the flexibility of the design and the potential for power savings even more. Freescale declined to comment on any new products, but sources familiar with the company’s road map said that if a core is underutilized at any point, the frequency will be lowered dynamically. Frequency cannot be scaled anymore, but adding more cores and scaling the power applied to those cores can allow developers to remain within a defined power budget.

End market mandates

This type of thinking is being driven as much from the end customer as at the system-level design. The emphasis in industries such as data centers, which currently consume about 2% of the nation’s power, for example, is on everything green. Fearing a crackdown by the government or utilities, many are working hard to develop much more efficient approaches to computing.

At every single layer of the analysis, the old paradigm used to be the cheapest, most mass-produced equipment,” said Anthony Wanger, president of i/o Data Centers in Phoenix. “For the first time, Intel and AMD are competing over who’s the most efficient. Hard drives also use a lot of electricity, but electrical energy tends to be more efficient than mechanical energy. This isn’t happening just at the data center layer. At the device layer people are competing on efficiency. If you take that kind of server and put it into a 2009 data center, your work per kilowatt increases dramatically because you’re attacking all of these things, not just one of them.”

In the consumer market, the key driver these days is battery life. Most of the new netbooks are being advertised based upon battery life first, with other features a distant second. The initial success of the netbook, in fact, is a sign of just how far down on the list performance has dropped compared to power.

But adding variable-speed processing, which is roughly the equivalent of accelerators in various states of on, sleep or deep sleep, could bridge these two worlds quite effectively. Intel, Freescale, Texas Instruments, ARM and others are exploring these kinds of tradeoffs. And in the future, this could provide some interesting workarounds to some thorny problems in multicore software programming without a power penalty.