By Ed Sperling

Portability Play
Synopsys is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. iPDKs are particularly important for companies looking to use designs for multiple markets. A general-purpose process, for example, is critical for markets looking for higher performance, while low-power processes are important in applications where battery life is a differentiating factor.

The problem is that many of these designs are not always portable between processes, despite the fact that power and performance are considered tradeoffs in most designs.

The companies said the 65nm G and enhanced low power (LPe) kits are available now. Versions for other process nodes will be available later this year.

Stacked die demo
Imec, the Belgian research organization, demonstrated a stacked die with DRAM on logic at Semicon this week. The chip is a prototype of what is expected to become a mainstream approach as companies seek to re-use existing analog IP and subsystems from previous nodes, as well as to add flexibility and speed to complex designs.

What’s particularly interesting about the prototype is Imec’s description of how heat can be removed from the die. Logic generates a fair amount of heat, but the DRAM die acts as a conductor for some of that heat. Qualcomm observed similar effects in its own stacking research last year.

Imec’s work was done in conjunction with GlobalFoundries, Intel, Micron, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm.

By Ed Sperling
Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine.

While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern over global warming and a steady reminder that smart phones have to be plugged in every night, car companies are shifting their strategy from efficient hybrids to even more efficient plug-in hybrids and electric vehicles, and California has gone so far as to mandate that one-third of all electricity sold in the state by the end of 2020 must come from renewable sources.

This shift in public awareness hasn’t been lost on the chip industry, which has been rolling out some very complex advances well ahead of schedule. Here are some of the most important:

Clouds
The push toward a cloud-based infrastructure is a way of centralizing computing—basically a return to the time-sharing model once perfected by the mainframe and then re-distributed with the advent of the commodity PC server. The data processing world is re-aggregating, but this time with a difference. It’s not just that the computing is being centralized. It’s that the centralization is taking place in proximity of cheap power sources such as hydroelectric power, nuclear plants (for now) and wind farms.

“Cloud leads to big efficiency gains,” said Chris Rowen, chief technology officer at Tensilica. “Now you can put the computing farm where the energy is available. It’s an arbitrage opportunity. It’s not hard to ship bits when you compare that to the difficulty in transporting electricity.”

There’s a clear business case to be made on this front. An estimated 6.5% of electricity is lost in transmission, according to the U.S. Energy Information Administration. That may not seem like a lot until you consider those are high-voltage transmission lines. Bits are cheap, in comparison—even trillions of them—which is why there is talk now of centralizing portions of even base stations. Those parts that do intensive computation with a high degree of redundancy are prime candidates for being located in a data center.

“There’s a lot of computation needed to reduce noise and create a clean signal,” said Rowen. “But there’s also some computing that has to be done locally because there are tough latency requirements.”

Adaptive Body Biasing
Adaptive body biasing has been under serious discussion for the past five years as a way of reducing current leakage by controlling a device’s body voltage, which in turn increases the voltage threshold. The big advantage here is less switching to the off state. The downside is this is has been difficult stuff to design and manufacture.

“This was not seen as a mainstream approach, but now it’s showing up almost everywhere,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “This was seen as a challenging technique to implement, but now TI and Samsung are using it. If you change the body bias voltage, you impact the threshold voltage. You can increase or decrease leakage, as needed, and boost performance.”

Consultant Bhanu Kapoor, president of Mimasic, noted that for some high-performance applications the alternatives such as power gating may be impractical because it simply takes too long to turn on and off sections of a chip. In those cases, body biasing is the only choice.

Atomic-Level Changes
Another technique that has been particularly difficult to master is atomic-level control of channel doping on the manufacturing side. And while most experts don’t expect the process and manufacturing side to offer any huge gains, this one may be the exception.

Scott Thompson, chief technology officer at startup SuVolta, said that by improving the doping technique, both dynamic and static current leakage can be reduced with regular bulk CMOS.

“The problem is that the wall around the channel is leaky and it’s hard to control the shape,” said Thompson. “Strain engineering helps to control the atomic-level analysis. But there has been no other breakthrough other than changing the transistor, and we don’t see a need for that for all architectures.”

At its unveiling last week, SuVolta had lined up support from Fujitsu, Cypress, ARM and Broadcom. The company claims the technology is an alternative to FinFETs, which are more difficult to manufacture.

3D Transistors And Packaging
Nevertheless, the major foundries have committed to building FinFETs at advanced nodes. Intel’s announcement of a Tri-Gate three-dimensional transistor at 22nm has been a major topic in the semiconductor industry. The question is now that Intel has publicly committed to the technology, can it really be manufactured with sufficient yield? And can it be built effectively using the disaggregated foundry model in the near future?

These kinds of questions will remain unanswered at least for the next couple years. TSMC is planning to use FinFETs at 14nm, and GlobalFoundries has been working on the same technology. Nevertheless, the big advantage of FinFET technology is a sharp reduction in leakage while providing a significant performance boost.’

Creating stacks of die also has a huge effect on power, in part because the distances between logic and memory can be shortened significantly. A system-in-package version of stacked die, using interposer technology, is expected to begin widespread production over the next 12 to 18 months, bolstered by the new Wide I/O standard that increases the size of the pipes between logic and memory.

New Materials
Fully depleted SOI, silicon on sapphire, as well as new ways of putting them all together in stacks connected by low-cost interposers that can be made of glass have turned into major research efforts as companies seek to knock costs out of the bill of materials for new chips.

While the FD SOI has been well tested for years by the Common Platform participants, the others have only been used on a very limited basis. One approach now being considered is actually designing chips to run hotter rather than trying to keep the power down. While there are limits to this approach—no one wants to pick up a hot phone—there are times when performance is more important than heat.

Taken as a whole, all of these changes can have a significant reduction in power, particularly when coupled with efficient software code and more customized user controls—and end devices that actually use the power-saving technology that is being built into these chips.

By Brian Fuller
Silicon CMOS is a tough act to follow. The workhorse building block for the world’s electronics has been delivering for system designers for a half century. Despite hand-wringing over its apparent scalability limits, it shows only vague signs of slowing down.

For nearly as many years, it seems, the next great material or alternative to silicon CMOS has popped into the industry’s consciousness promising to be the next big thing—next year. Gallium arsenide, for example, has been next year’s hit technology for four decades.

The latest “it” material, however, could actually deliver on its early hype, and in the process enable the industry not only to continue scaling but to drive deep into previously unexpected depths of low-power design. Graphene—the two-dimensional crystalline form of carbon—first emerged as a term in the late 1980s and gained traction in 2004 when researchers at the University of Manchester extracted graphene layers from graphite—basically using Scotch tape—and then placing on silicon dioxide on a silicon wafer.

This time it’s different (maybe)
The material exhibited fantastic characteristics, including high electron mobility compared to silicon, twice the storage capacity of ultracapacitors, and it was rugged to boot. What’s more, its characteristics apparently remain stable down to the molecular level, unlike other materials used in semiconductor design. The graphene promise is such that in just the past three years, research papers are being written on graphene at the rate of one a day.

“There are two features that make graphene exceptional,” Kirill Bolotin, assistant professor in the Vanderbilt Department of Physics and Astronomy, said in a recent interview. “First, its molecular structure is so resistant to defects that researchers have had to hand-make them to study what effects they have. Second, the electrons that carry electrical charge travel much faster and generally behave as if they have far less mass than they do in ordinary metals or superconductors.”

Where some see glowing walls made of graphene circuitry and other exotic applications, people like James Meindl see an answer to scaling. Keynoting at the recent ISSCC (International Solid State Circuits Conference) in San Francisco, Meindl, director of the Joseph M. Pettit Microelectronics Research Center at the Georgia Institute of Technology in Atlanta, said: ”We will continue to scale vigorously for the next 15 years. Beyond silicon microchip technology, revolutionary developments in nanoelectronics, perhaps centering on graphene, may evolve.”

That’s music to the ears of many who, despite CMOS’s dogged determination, seeing scaling hitting a wall in the next decade.

“Look at Intel’s roadmap. They’re looking at 4nm in 2022,” said Michael Keating, a Synopsys Fellow. “As long as they’re charging down that road, graphene’s going to be a second-class citizen. But my guess is 2022 is not realistic for 4nm. Silicon will be seriously in trouble in that decade.”

“The reason graphene’s interesting is so much progress has been made in such a short time frame,” he added.

What’s all the fuss?
Graphene—a one-atom-thick planar sheet of sp2-bonded carbon atoms that resembles chicken wire—has a lot going for it.

Meindl, speaking at ISSCC, gave a half-dozen reasons graphene is going to win in the marketplace, including:

• No other known material has a higher mechanical strength-to-weight ratio.
• Carrier mobility exceeds 200,000-cm2/Vs.
• The capacity to conduct current densities as large as one thousand times greater than copper without electromigration.
• Graphene can serve as a source, channel drain regions of a field effect transistor (FET) and as an interconnect.

In addition to all the big talk, there’s been action.
• Fujitsu Laboratories Ltd. has developed a method to form graphene transistors directly on the entire surface of large-scale insulating substrates at low temperatures while employing popular chemical-vapor deposition (CVD) techniques.
• IBM in 2007 fabbed graphene field-effect transistors (FETs) using a single layer of carbon atoms atop a silicon wafer at its T.J. Watson Research Center at Yorktown Heights, N.Y.
• In February, IBM built, on 2-inch wafers, RF graphene transistors running at 100-GHz and operating at room temperature.
• At around the same time, Penn State researchers announced they have developed a way to fabricate graphene sheets on 4-inch wafers.
• Last year, Bolotin, working with colleagues at Columbia University, managed to get graphene to exhibit the fractional quantum Hall effect, where the electrons create new particles with electrical charges that are a fraction that of individual electrons, according to work published in the journal Nature.
• A venture-backed Austin, Texas, company, Graphene Energy, is working to commercialize graphine for energy storage.
• Javad Rafiee, a doctoral student at Rensselaer Polytechnic Institute developed a method of ultra-efficient hydrogen storage based on graphene. His approach stores hydrogen with 14 percent efficiency, better than any other material attempted to date.

What’s the catch?
There’s always a catch. While graphene is easier to manufacture than its cousin, the carbon nanotube, it’s no slam dunk yet. To date, there hasn’t been a simple way to create the p- and n-type devices required for CMOS transistors. But Georgia Tech recently reported it has used an electron beam doping process that simplifies the transistor manufacture.

In addition, graphene has no band gap so there’s no way to turn them “off.” But even that hurdle is being brought down. Researchers at Lawrence Berkeley National Lab last year engineered a controllable band gap in bilayer graphene—at room temperature.

When will we know when graphene gets the “next-year’s technology” monkey off its back for good?

Maybe relatively soon, suggested Synopsys’ Keating.
“CMOS has had an incredible run. It’s foolish to bet against CMOS. (But) graphene every year makes significant progress. It’s absolutely the promising thing right now. We’re a decade away.”

By Ed Sperling

Business seems to be picking up everywhere in the design world, with an emphasis on speed—quicker deals, faster product rollouts and overall time to market—and all of it with an underlying emphasis on low power and tighter power budgets. Could it be that after the recession, everyone is trying to get back on track quickly?

Virage Logic completed the acquisition of NXP’s IP technology and its development team. That comes on the heels of its recent acquisition of ARC. The fact that Virage completed both of these acquisitions in a 12-day period is nothing short of an accounting miracle. And just in case the company didn’t have enough to do, it added a Silicon Browser for post-silicon bring-up and system debug.

Android seems to be getting its share of attention these days. Mentor Graphics introduced an Android Development System for Texas Instrument’s OMAP35x processors. TI’s processors also include ARM Cortex-A8 technology, which puts ARM squarely in the center of this effort, as well, with a heavy push toward better battery life. But will any of this take a bite out of the Apple iPhone?

On the get-things-done-quicker side, Digital Imaging Systems used Synopsys’ Galaxy Custom Designer to achieve first-pass silicon in 22 days. Not all of it was from scratch, of course, but that’s still a very tight timetable.

And Atrenta’s deal with Fujitsu’s Kyushu Network Technologies is aimed at reducing design risks in integration of third-party IP from multiple vendors with different clock domains. Translation: Faster time to market.

Also on the business side, Cadence expanded its design alliance with Toshiba for the consumer and mobile markets.

Intel invested millions of Euros in an Exascale Computing Research in France, as part of Intel Labs Europe. This is the second time in two weeks that Intel has paid out big bucks to appease antitrust regulators. This deal will add 900 new research jobs in Europe. That follows Intel’s settlement with AMD, clearing the way for Intel to go after ARM with its Atom chip.

ARM’s comeback was largely a reiteration of the strength of its ecosystem. It struck up a strategic architectural license agreement with Infineon for advanced security applications and created a solutions center for Android.