By Ed Sperling
Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry.

To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with later in the design process, and at 28nm it has become an essential part of the architecture. But as battery life, mobility, and energy costs even for plugged-in devices become overriding concerns, power now needs to be considered at full system level, which could mean everything from a rack of servers to an automobile.

Much of this is being driven from the chip level, and in the software that manages chips and interactions between chips. There are at least a half dozen new standards efforts under way or on the drawing board. Most heavily leverage the expertise of chipmaker and where they have encountered or expect to encounter pain in designs, most notably in stacked die or in planar SoCs below 20nm, or from tools vendors that have gained expertise in a specific area.

Si2 currently has one standard in legal review for system-level power modeling. The standard is called “atomic” power modeling, based on the assumption that the model cannot be broken down into smaller pieces, although it can be used at various levels of abstraction.

Also in the works is a standard for co-design, which is one of the most difficult challenges facing design today. While hardware engineers are well versed in how to build an energy-efficient chip, that engineering effort can be wasted if the software running on an SoC isn’t energy-efficient, as well.

“The first step is to get there with the architectural ESL level,” said Steve Schulz, president and CEO of Si2. “Then, we will look at how the software runs and develop a bridge. You will never get the software community to adopt the hardware approach to design. That community is 20 to 30 times larger than hardware engineers and they have their own tool flows. We have to think about a minimally intrusive solution. We’ve called it a bridge to the software world, and if it’s not intrusive then the software teams will use it. Most of them will never understand concurrency and how to get to a GDS II stream, but there are characteristics that are reasonable proxies of the details. You don’t simulate all the code, but you do generate enough discrete choices so everyone can get on the right track for power.”

A first step in that direction is finding data objects that can be passed back and forth between the software and hardware teams. From there a power model will need to be created across both. The power-flow group within Si2 has been reactivated to develop a source for the power model. “The focus this year will be hardware,” said Schulz. “In 2013 we will turn our attention to understand the data objects stored.”

That puts the likely adoption timeframe a of a co-design framework for power in the 2015 time frame—roughly at the 14nm process node and at a time when 2.5D stacking is expected to be mainstream and 3D stacking will become more commonplace.

Stacking effects
“There are two new requirements for design,” said Andrew Yang, president of Apache Design. “The first is a 3D IC flow. The second is an RTL-to-gate power methodology.”

Included in the 3D requirements is the need for multi-die thermal and stress analysis. Yang said the key is the amount of current a design can sustain without failure over time, and it gets worse at advanced nodes and sometimes in stacked configurations because wire handling capability is decreasing, power density is increasing, and electromigration is increasing.

3D IC thermal stress analysis. Memory die is impacted by power distribution of logic die. Source: Apache Design.

“This can be a safety issue,” he said. “You need to make sure the metal topology is handled correctly. Electromigration is affected by heat. The hotter it gets, the less current a metal wire can sustain. The electromigration rules are increasing, which is why GlobalFoundries, Intel and TSMC are all coming up with complex electromigration rules.”

Front to back, back to front
Being able to get a chip out the door at all is a challenge, which is why there are more standards being dictated from the foundries these days. In addition to process variation, continually shrinking geometries is making it harder to obtain adequate yields as quickly as in the past. That has led to more rules for place and route, test, IP, and layered across all of those is power.

“We’re seeing it in the available sizes, speeds, memory and logic cell sizes,” said Chris Rowen, CTO at Tensilica. “That’s what we target—area, power and process compatibilities. Whether that’s stacked or conventional die is affected only subtly. But with die stacking you will see significantly higher bandwidth and less latency, which will have an effect on modeling of the system. It’s not a qualitative change, but it is a quantitative change. It won’t change how one DSP communicates with another, but it will change how DSPs communicate with memory.”

How much of that will be standards promoted by standards bodies versus de facto standards from the largest foundries remains is unknown. Also missing are good open standards for on-chip debug and trace, said Rowen.

ESL standards
One of the most glaring holes in all of this is at the ESL level, where standards for power models are non-existent. While this isn’t a big problem in a single vertically integrated company, it’s a huge problem in a disaggregated supply chain where various companies work on designs—something that will become even more pronounced in stacked die where subsystems at different process geometries need to be integrated with other subsystems.

“What’s missing is something that allows companies to exchange power models, especially for IP-based designs” said Ghislain Kaiser, CEO of Docea Power. “In an ideal flow you would be able to take the IP from the IP suppliers and put together a power model and assess the power impact on the underlying hardware. But you also need to have interoperability between suppliers and customers that goes beyond the semiconductor level. It has to be optimized at each level—the SoC, the chip set, the PCB and above. So there won’t be only one number.”

The accuracy of those power models also will shift throughout the design. At the beginning a model may be only 40% accurate, but at the end it may need to be accurate to plus or minus 5%, Kaiser said.

Other pieces are missing, as well. Kiran Vittal, senior director of product marketing at Atrenta. “Right now, when a designer uses memory they don’t realize the code they are writing is not optimized for power. When you read memory you get a redundant read. The controller code isn’t optimized for memory. And all of that has to be networked, because you may have as many as 2,000 memories in a design. If you do it right you can save about 20% of the memories and the power needed to run them.”

To show just how bad this can get, a large systems house was designing a chip was required to give an early indication of its power budget to the OEM. The OEM used that estimate for calculating its own power budget and came up with a spreadsheet that represented the total design. The problem was that the spreadsheet ultimately was off by 100% in its power estimate, which in turn caused problems with the final device and greatly increased the amount of time it took to successfully bring a product to market.

“A lot of the ESL tools today know performance and area, but they don’t have a clue about power,” said Vittal. “This is fertile ground for innovation.”

By Pallab Chatterjee
FinFETs, stacked die, heterogeneous interposers, TSVs, 450mm wafers, new interconnects and everything with MEMs and sensors is what the last few weeks have brought. A number of major announcements, technology releases, conference updates have identified these technologies as the future of IC design.

At ISQED, Robert Geer, chief academic officer at the College of Nanoscale Science and Engineering in Albany, N.Y., discussed nanotechnology programs while highlighting the construction of a new building dedicated to 450mm wafer fab development. This new fab will support R&D for equipment, devices, and processes for the wafers that just a few years ago fell under the heading of, “most likely not going to happen.” The facility will work on lithography, front end of line (FEOL) and back end of line (BEOL), as well as adjustments to and planning for the logistics for managing these massive and very heavy wafers. This is being done concurrently with further development into the single-digit nanometer process and device technologies. These new flows and processes target devices with operating voltages of less than 0.8v, breaking the 1 volt threshold that has been dominant for more than 50 years.

Adding into to how these new processes will perform, the Common Platform Group (GlobalFoundries, IBM and Samsung) presented 20nm high-k/metal gate flows and identified this is the end of the line for Planar CMOS. Beyond 20nm, the next-generation devices will be FinFETs, with more exotic devices to follow below 10nm. Better control of leakage, as well as improved low-power performance, are due in part to these new devices not having a diffused source/drain in the bulk or epi material, which can serious impact secondary current paths. However, the devices do raise several new concerns, not the smallest of which is the device description. Instead of just W and L, designers now will have to add Z. This impacts simulators, netlists, and physical build/verification of the designs.

While most of the talk has been on process capability, there also is a lot of attention being focused on changes in IP and design methodologies. A consistent theme in these discussions is that power is the No. 1 design constraint and drives even functionality for the definition of new designs. Power, and the new soft metric of performance per watt, are the basis for these new $100M design development projects. IBM and Samsung executives noted that the economics of these new designs have changed significantly.

The basis of power as the overall constraint has now brought the impact of packaging and other modules into the design process. Local thermal balance, power distribution, bonding methods, stacked die, and signal interconnect to adjacent devices are now required parts of the initial SoC design.

MEMS is a case in point. The key issue MEMS developers wrestle with are power and accuracy, rather than speed. Most of the MEMS systems have 16-to-30-bit accuracy on the sensor element, but the challenge is getting these signals to the data-processing electronics with as little disruption using as little power as possible. Noisy interfaces consume power and reduce the signal integrity and accuracy of the main datapath. As the Internet of Things progresses to have sensors in everything, the power shifts from the logic processing section to the RF and communication circuitry. These blocks have to be balanced with the reporting rate, which operates the radios, and when the low power data is being collected. The majority of the systems on the Internet of Things are multi-die devices.

TSMC joined the fray with its new interposer announcement. It was not clear by industry naming convention (2.5D, 2.75D, or 3D) what the technique should be called, but it brought major technical advances toward the stacked memory on logic design methodology and the major performance/watt improvement over other technologies. This once again, brings power as the driver to the forefront.

By Ed Sperling
Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in front of a live audience at the Global Technology Conference in Santa Clara, Calif.

LPE: Is it harder to sell EDA tools for older nodes?
Heinlein: On one hand, the EDA requirements of the industry are evolving quickly. There’s one challenge where people have older tools, and you have to do new IP based on older flows. And then you have people wanting to use new tools on older nodes. They may want to use things like CPF. So we have this schizophrenia and we have to support that.
Kapoor: EDA is about tools, IP and services, and the reason the design components start to come in is that when you get to new nodes or existing nodes, you have to go broader than just tooling.
Sherwani: If you are developing tools for 14nm you are dealing with FinFETs and a lot of physical effects. But at 0.18 (microns) the issue is how to make one or two designers very efficient. We need to hire operations business people who have nothing to do with design in order to change that. EDA companies are very much focused on physics and getting to 20nm and 14nm. They still don’t have the mindset toward finishing a 0.18 design in one day. Is it possible to put together a flow that can be done by only one guy? In addition, many designs are derivative designs. Companies may want to add DDR3 to an existing design. The headcount and mindset required is very different.
Kapoor: We were joking before this panel that somewhere between the 34th and 43rd minute if I’m on a panel with Naveed he’s going to ask for free tools. With all due respect, that’s not a business we’re in. But in our core EDA business, we spend a lot of time on engineering efficiency. You will see a set of capabilities from Cadence that will address that. But if you can get an engineer to do a 180nm in a day, we should spin off a business.
Sherwani: The tools are focused on efficiency, but not on whether you can do designs in a day. If you can do a design in a day, you still have to verify that.
Ng: The point Naveed is raising is a cost issue. Whether it’s at the leading edge or older nodes, cost is in the purview of whether it even makes sense to do the design. Years ago when I was at Cadence we had a seven-day design goal. EDA hasn’t always looked at driving cost and efficiency.
Kapoor: First and foremost, EDA is about density and automation. The second part is that you have to figure out how the economics of the whole industry work. If at 40nm we spend $600 million putting together technology, to have anyone design at that node you need sufficient volume to get an acceptable return. And at 28nm it’s $1 billion and at 20nm $1.5 billion. You have to recognize that everyone can’t have an apps processor. That’s not going to happen. Just like there are limits to technology, there are limits to economics. If that’s what it will take us to put into it as part of the broader industry, that’s what we’re going to have to bear.
Ng: Do you think EDA has been driven to the same level of efficiency as other parts of the supply chain?
Kapoor: That’s not a fair question and here’s why: The way the business model for the tools piece works is different than for the semiconductor manufacturing. In the long term, if we bring on additional services will we look to be more in line with other parts of the supply chain, including Naveed’s business? Absolutely.

LPE: If power was not an issue at 180nm in the past, why is it such a big issue now?
Heinlein: Because the bar always moves. People are looking at applications that require low power much more than before. We also need to have power management ICs alongside other chips. And there’s a question of using the right hammer to solve a problem. The bar is different than it used to be.
Lukanc: The mix of things you put in a chip is different. There are mixed signal and power management. You can get a 40-volt PCB process at 0.25 microns. Now 30-volt processes are available at 0.13. You can mix things together and keep mask costs relatively low. Time to market is shorter, investment is lower and it requires fewer people.

LPE: What does the ecosystem look like with more foundries at older nodes?
Sherwani: These are not like TSMC or GlobalFoundries. They have their own IP houses or in-house IP.
Heinlein: That’s correct. These are companies that are very comfortable in their niche markets. That said, we are starting to witness sea changes in areas such as embedded microcontrollers, driven by the so-called Internet of things. That’s going to drive people to put microcontrollers and processors in places where they’ve never been before. Enabling modern software development and EDA development allows you to do more.
Kapoor: If you’re talking about a transducer or something like that, you’ll have to integrate the increasing analog and mixed signal capability with the digital capability. A mature node makes perfect sense. What you have to learn is what you need from the EDA side all the way to the manufacturing side.

By Ed Sperling
Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics.

Stacking die holds the promise of becoming something of a game changer because it can solve multiple issues at once—power, performance, physical effects such as noise and crosstalk—while creating its own issues such as who’s responsible when two known good die don’t work in a package.

But the surprise among companies working with this packaging approach is that it’s harder to remove the heat from stacked die than anyone initially thought. The generally accepted premise that silicon is a good conductor of heat is true, but apparently not true enough. Early tests show that 3D stacks are showing some limits for through-silicon vias.

“What we found is that you have about a 7 to 10 watt maximum for through-silicon vias using current technology,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “After that you have to go to an interposer.”

This is somewhat counterintuitive, because most engineers have always assumed that 3D stacking would be the successor to 2.5D stacks. Unless something is done to change the technology, it may be the other way around. This is good news in one sense. It’s cheaper and easier to work with an interposer, which contains TSVs on a separate piece of silicon, than with TSVs running directly through stacked layers of thinner chips. There is less stress to deal with from drilling through a layer of silicon, and yield is higher if those TSVs are run through a thicker piece of silicon.

“The big problem now is that with a dense TSV the heat is trapped,” said Dian Yang, senior vice president of product management at Apache. “You have to use metal to dissipate the heat. People didn’t know the power density would be so high, and that has causes thermal issues that are much more severe.”

In 2.5D stacking, the tradeoff is the footprint. A 3D stack is much smaller and can fit into smaller spaces, which is why it has been of particular interest to companies such as Broadcom and Qualcomm.

It’s not the TSV technology itself that is causing problems. It’s the location of the TSVs. There are still places where TSVs work extremely well, such as inside of interposers and in stacked memory configurations. Memory is particularly attractive because it doesn’t generate heat anywhere near the level of logic. Micron and Samsung are both developing stacked memory configurations using TSVs and claim faster performance, higher density and lower power. This kind of memory can be used in a 2.5D as well as a 3D stack.

Other considerations are under way, as well, such as using different substrate materials using different cooling methods, such as microfluidics. But there will either have to be a compelling technology reason, which so far has not been proven, or a major ability to reduce the cost of these approaches before this kind of technology hits the mainstream. Until then, it’s anyone’s guess whether and for how long a pure 3D stacking approach will be successful.

By Ed Sperling
Low-Power Engineering sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; Vishal Kapoor, vice president of marketing for SoC realization at Cadence; Naveed Sherwani, CEO of Open-Silicon; John Heinlein, vice president of marketing at ARM; and Jeff Lukanc, director of engineering at IDT. What follows are excerpts of that conversation, which was held in front of a live audience at the Global Technology Conference in Santa Clara, Calif.

LPE: What is the definition of a mainstream process node these days and why are older nodes so important?
Heinlein: We’re thinking of mainstream as 55nm and older. That’s where a lot of the high volume is. Even though it’s sexy to talk about the leading edge, last year about 75% of ARM’s royalties came from cores that were developed in 2006 and earlier. About 3 million of the 6 million cores we shipped were ARM 7.
Ng: From a manufacturing standpoint, the volumes are at 65nm. From that node it’s moving from 55nm and 40nm, but that’s still the bulk of the industry. A lot of companies are doing some very cool things that are very relevant today at those nodes. Even with some of the biggest companies, a lot of the volume is at 65nm. It’s what pays the bills. If you have 200mm capacity, those fabs are completely depreciated.

LPE: How about for the tools? Does the mainstream part of the market really pay the bills?
Kapoor: From an EDA perspective, 65nm pays the bills as much as 28nm and 20nm.

LPE: Is everything still following Moore’s Law? If a company is designing at 65nm, does it necessarily move to the next node?
Sherwani: We look at everything from networking to consumer applications. Some customers need the latest technology. But there are others who are at 0.18 (microns) and thinking about 0.13, and maybe they don’t to go there. The velocity of that move is segment-specific.
Lukanc: The mainstream for production is 0.13, but a lot of the new designs are ramping to 65nm. We’re looking at older technology and combining new things through integration. There may be a call management IC with a 30-volt option at 0.13 or 0.18, which allows the unique combination of analog and digital management on one chip. We can re-use some of the older technologies.

LPE: There’s a lot of investment in older processes these days. Why?
Sherwani: I visited about 10 fabs in China and I was surprised that none of them had 65nm processes. Most didn’t even have 90nm processes.
Ng: If you look at what’s driving a lot of technology today, it’s the consumer market. And that’s very cost-conscious. If you can’t take advantage of the latest technology, then you look at where your given application makes sense. Cost is very much a factor that customers consider at each process node. And for us, we have to find ways to keep investments in fabs relevant to our customers. We have a big focus on high voltage and power management. We have to find ways to add value on top of baseline logic, which is a commodity at this point.
Heinlein: If you look at smart phones, everyone is always focused on the processor and the high-end chip. But alongside those are the power management controllers and display drivers and RF/mixed signal. Another area for derivative value-added processes that Walter (Ng) mentioned is low leakage. When you get to 65nm leakage is a problem. There are ultra-low leakage variants and high-voltage variants coming out at the high end and the low end, so people can put those into applications that can run on a coin-cell battery for 10 years. To complement that there are ultra-dense libraries that bring the cost and the leakage down and which are suited very well to these kinds of applications.

LPE: If you develop a chip at 180nm and the process changes to low leakage or low power, does it yield the same?
Ng: The strategy in developing these new processes or modules on top of derivatives is to preserve the investment that was made earlier. It takes advantage of the proven solutions that are already there. When we originally developed those processes, at that time they were leading-edge processes. As you get much more volume using those processes, the manufacturing window becomes quite tight. You could probably tighten up the bit cells. But it’s a business tradeoff whether you re-invest in that or not. The yields are just as good.

LPE: What happens to the tools and the IP that was developed?
Heinlein: For the most part it all works. If you think about 180nm, nobody cared about leakage because it wasn’t an issue. Now, when people look at 180nm, they do care about leakage and power management. So we’re putting that back into 180nm.
Kapoor: The innovation at the leading nodes is going to drive benefits at the older nodes. You drive it back in terms of products, but you also drive it back in terms of design techniques. We developed a 28nm PHY, and we were challenged to do it differently because it’s for a leading node. Today we’re applying what we’ve learned back to 40nm and 65nm.
Lukanc: The best tools are developed at the leading nodes, but you may want to characterize older libraries for low power and power management.

LPE: If you improve an existing technology at an older node, can you charge more for it?
Lukanc: Yes. In general, what we’re offering is value-added solutions. In some cases we offer value-added solutions that are low power.

LPE: Will it be essential for older processes to be updated when we get into stacked die as a way of decreasing the overall power budgets and physical effects?
Sherwani: The answer is different for each area. There is no single, simple answer to that.
Kapoor: For a long time our industry has looked at the technology piece rather than the economics. The answer is, it depends. Can you get more value out of an older node? Yes. The economics will drive the longevity of nodes and what you can get out of them. But we cannot talk about the value of older nodes unless we invest in the newer ones.
Lukanc: If you have an existing product, you can look at the option of integrating oscillators or an EEPROM or something else on top of it to reduce the system cost. There are lot of things you can do in a package to reduce the overall cost, but you have to look at the total system cost. You may be offering a smaller footprint to the customer, but they may not be getting value out of that.
Heinlein: If you look at mixed signal and RF design at the leading-edge nodes, it’s really tough to get the transistor variation to be complementary to the analog. There’s a point at which it’s too hard, and in that case a heterogeneous 3D package makes sense.
Kapoor: With 3D ICs there’s a technical capability about whether you can marry different die. But you also have to look at it from a system capability. When you look at tablets, where the SoCs are talking in very high bandwidth to memory, that makes sense. The technology by itself won’t be an answer. You need to find out where it makes sense to use it.

LPE: Is investment in older process nodes an arms race that favors the big foundries?
Sherwani: The specialty foundries being built in places like China have nothing to do with companies like GlobalFoundries and TSMC. They will ship a lot of silicon. Over the next 10 years a lot of the analog silicon will be shipping out of China using all older nodes.
Kapoor: Those boutique fabs are certainly making investments in areas in which they specialize.
Ng: You have to continue to make fabs relevant and to drive a good margin. A big impetus for us in developing modules on top of our processes is that you do get the second- and third-tier foundries coming in and taking the floor out of the base logic price. That’s difficult for us to compete with. So we’re looking at where to add value and how to win a good percentage of market share. We have our investments in 200mm. We will continue to invest there.
Heinlein: We definitely see lots of specialty processes at the smaller players. We work with them and enable them. But once it gets to a certain point in the market they we work with the big players.

LPE: Will it become a battle of who has the deepest pockets?
Sherwani: The good thing about older nodes is that the investment needed is miniscule compared with the tens of billions of dollars at advanced nodes. A lot more players can be relevant at older nodes. At 14nm I don’t think there will be more than three or four players.
Ng: The incremental investment to bring up these value-added modules is nothing compared to the investment at the leading edge. The other side is that the equipment manufacturers are a leading component of the cost at the leading edge. At the mature nodes, you’re not buying a lot of new, expensive tooling.
Lukanc: That happens on the product development side, as well. To do a 100 million-gate design requires a certain amount of tools and people and mask costs. At the older technologies mask costs are quite cheap. And if you’re re-using technology and adding to it, you can keep NRE low so return on investment is quite high. You need to take advantage of mainstream older nodes as well as more aggressive nodes.
Ng: And most times our relationship with most of the leading-edge companies span multiple nodes.
Kapoor: At 14nm there are 5 or 10 customers. As a foundry, you have to worry about how you’re going to get the rest of the industry in. The economics even for the companies that can afford it aren’t that great. So you’re going to see continued innovation even at the older nodes.
Ng: A major part of the foundries’ concern is up and down the supply chain. It’s not just the fabs. It’s the tools, the support for IP providers, and packaging solutions. That’s a challenge we have to address as an industry.

By Ann Steffora Mutschler
As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability.

CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very high-power technology.

“For many years it has been a very low power, very power-savvy technology. Moving from one technology node to the next would basically cut the power consumption by half. This was great because you could basically integrate twice as many transistors within the same power budget,” explained Marco Casale-Rossi, production marketing manager for Synopsys’ implementation group.

That was ideal when electronic devices were powered by the plug in the wall and weren’t hampered by batteries, he said, but when we moved to mobile it was already too late. “Basically, what has happened in the last decade is that we have shrunk basically the width and length of the transistor but our ability to shrink the thickness of the transistor is much, much lower.”

With the move from 45nm to 32nm, and then from 32nm to 20nm, there are twice as many transistors. Without leakage, the power consumption would remain the same, but because of leakage it goes up quite significantly. At 45nm, in a typical process technology the total power consumption is dominated by leakage. There is more leakage power than active power and the problem is that it’s there whether you are doing something or not and drains power from the battery.

“There are no secrets here,” said Greg Bartlett, senior vice president of technology and integration engineering at GlobalFoundries. “Power problems started at 130nm and have gotten worse since then. Historically, the problem was standby power, but it has shifted. There’s been a lot of talk about operating at a lower Vdd to help with this, but the only thing we’ve been able to do with every new technique is to forestall the problem. It comes back one generation later.”

With each process shrink leakage goes up exponentially with temperature—by a couple of orders of magnitude when going from room temperature to 125 degrees.

“Heat is a killer of electronic components. One of the issues, especially as we’ve gotten into some of the smaller geometries, is that the leakage current becomes exponential with the temperature. Small increases in temperature can have a large impact in the amount of current and heat that’s being generated by the actual chip or silicon, and clearly that’s not a good situation because if you add heat to it, it generates more current, which generates more heat, which generates more current—it’s going the wrong way fast,” said
Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics.

“Any type of engineering problem really, if you’re going to address an issue like that, it’s important that you have tools that can actually give you an accurate analysis so that the designers know what’s happening with the design and they can take measures then to control that and change the design to keep the design within the parameters that they need to,” he continued.

Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions agreed. He said that before the power densities can be measured, the right power-sensitive stimulus must be selected and that knowledge must be pushed all the way through the design planning process towards package selection. “The stimulus is becoming more and more critical in terms of really looking at and predicting what will happen to power before it reaches the physical side and meets these power density issues. If you are not properly predicting the power in the beginning of the flow then everything becomes academic. You overdesign or underdesign by definition.”

He recalled the horror story of a system designer who thought he would be designing a chipset at 10 watts, but when the ASIC came back from the manufacturer it ran at 5 watts. The explanation from the ASIC manufacturer was that they could not predict that well because they are at the back end of the flow from the RTL and microarchitecture decisions.

This illustrates the huge disconnect between designers using conventional spreadsheets, looking at library elements or taking guesses as to the activity factors and true power predictions. “The root cause of the issue is the ability to predict as much as possible, as close as possible to what your final, worst-case power states will be and then designing for such in terms of test patterns and so-called power patterns,” Kulkarni said.

Adding up the power
Add some 2.5D or 3D stacking to the power density mixture and things really heat up. Matthew Hogan, technical marketing engineer for LVS in Mentor Graphics’ Design-To-Silicon Division, observed one of the big issues for designers in terms of dealing with power density and stacking is that the thermal profile is cumulative going up the stack.

“One of the big concerns that they are looking for is if they do have a hotspot on a die and they are stacking it with either the same type of die or different die, and if there is a way they could rotate or make sure that the hotspots are not coincidences as they move in the vertical direction,” he said.

Engineers try to even out the thermal profile naturally through its operation and try to get a better understanding of what the dynamic thermal profile would look like. They do this so that when it’s in its operational mode that they don’t have, for example, the bottom left-hand corner be the hotspot for the entire stack while the top right-hand corner is cooler. Designers want to know how to move the hotspots on each of the dies around so they can create a more even thermal profile for the whole system rather than on a chip-by-chip basis. That turns it into a system and system verification problem, Hogan said.

When and where that analysis is done depends a lot on what internal flows and processes have been implemented.

“Ideally it would happen at a floorplanning stage where each of the design groups get a thermal budget or a power budget, because thermal and power are somewhat intertwined in the IC side. When they get their budget for their block and you’ve got a floorplanning region, you should have a reasonable estimate as to how much power is going to be used by this block, or at least what your budget is,” Hogan said.

Added Mentor’s Pangrle: “If you’re starting with cruder estimates at the beginning, as you get more information about what the final implementation is going to look like, you can improve those analysis and estimate numbers and continue to do a sanity check the whole way through. Any type of flow that somebody’s going to put together they’re going to want to make sure that as they’re crossing these different levels of abstraction that in fact they’ve got a framework where they can have these paths and loop back and put this information as they get it in to make sure that in fact its all still going to hold together.”

The temperature-leakage loop
The temperature-leakage loop discussed above is the very reason why 3D IC is causing so much concern. Its structure hampers the ability of the silicon to dissipate the heat.

“My impression is that manufacturing will not help in terms of heat dissipation. The only way to reduce the power consumption and avoid the heat dissipation issues in the future will come from design techniques,” Synopsys’ Casale-Rossi said. “If you think of today’s processors they are built with voltage islands so you can turn on and off a portion of the IC when you don’t need it — this was not needed 10 years ago, but now it is a method of survival. Moving forward, design and of course design automation—because all these techniques are awfully complicated—will be important to mitigate the power related and heat thermal related aspects.”

But there is at least some continuity in the tools flows. To accurately model, analyze and predict worst-case power problems in today’s chips as well as future 3D ICs, it is now widely agreed that most EDA tools will undertake an evolutionary change – not revolutionary, as some had predicted.

“Evolutionary means, for example, a place and route tool will need to understand that a certain area is forbidden because there is a TSV there,” Casale-Rossi said. “But this is not a big deal. Test will evolve because the accessibility of the various tiers will go down. I anticipate that all of the JTAG and BiST related technologies and algorithms will have a great future ahead. Extraction will need to account for the capacitance and the resistance introduced by the TSV. It will be the same for DRC and LVS. There will be more rules to be verified but it’s not a revolution.”

The reality is that many people are quietly doing 2.5D and 3D IC experiments without much pain because there are workarounds and scripts. Later, when it is understood what is really necessary, the scripts will get incorporated into the code of the tools and become an integral feature of the tools. “For the time being, the amount of code that is really needed is minimal,” he concluded.

By Ed Sperling

Portability Play
Synopsys is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. iPDKs are particularly important for companies looking to use designs for multiple markets. A general-purpose process, for example, is critical for markets looking for higher performance, while low-power processes are important in applications where battery life is a differentiating factor.

The problem is that many of these designs are not always portable between processes, despite the fact that power and performance are considered tradeoffs in most designs.

The companies said the 65nm G and enhanced low power (LPe) kits are available now. Versions for other process nodes will be available later this year.

Stacked die demo
Imec, the Belgian research organization, demonstrated a stacked die with DRAM on logic at Semicon this week. The chip is a prototype of what is expected to become a mainstream approach as companies seek to re-use existing analog IP and subsystems from previous nodes, as well as to add flexibility and speed to complex designs.

What’s particularly interesting about the prototype is Imec’s description of how heat can be removed from the die. Logic generates a fair amount of heat, but the DRAM die acts as a conductor for some of that heat. Qualcomm observed similar effects in its own stacking research last year.

Imec’s work was done in conjunction with GlobalFoundries, Intel, Micron, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm.

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: Has there been any progress in providing a feedback channel for software development to link that with the hardware design effort?
Low: Our software team is larger than our hardware team now. The consumer and the market are driving that.
Castagnetti: Part of that has to do with whether there are good models. One issue is how you predict power consumption. If you write code this way or that way, how good is that number compared to the end number? That’s part of the issue.

LPE: And if you have your cell phone on and you’re searching for base stations, you’re consuming power. Accelerators are running in the background and not even showing up on your dark screen. But is this even being considered by developers?
Low: We certainly have the use case model for this scenario.
LPE: The foundries have a super low-power process. What’s different there?
Brotman: Pieces of that are fundamental engineering—engineering the channels for low energy and high k/metal gate structures. Those are all part of putting together a transistor that is low power in operation and low leakage when it’s in standby. On top of that we have reference flows in place to do power predictions on the devices.

LPE: So how much will the process save us over the next couple nodes?
Brotman: We’re going to see improvements, but as we push down in process nodes we’re also going to have penalties. To some extent these things partially negate each other. We get improvements from node to node. High k/metal gate is showing improvement going from 45nm to 32. High k at 45nm is less leaky than at 28nm.
Castagnetti: The past improvements we’ve seen will never offset the designs again as we double the number of transistors and increase data rates.
Low: As we move to 22nm/20nm, the Vt level is decreasing. The EDA vendors have to make sure the flow is optimized for lower portable power.

LPE: What happens when we go into stacked die? Will that give us a big boost in power savings?
Brotman: 3D packaging will result in power advantages. Wide memory sitting on top of a graphics core will allow you to drive the power down. There will be lower parasitics and less inductance, which will allow you to drive that power down, as well. There are other things we need to take into account with 3D, though, such as temperature management. If we don’t deal with those, they can impact power in the wrong direction.
Low: When you stack the die you minimize the interconnect distance. That can help reduce the dynamic power. But thermals become a problem. As temperature increases, leakage increases, so you have to make sure that the temperature does not become a problem.
Castagnetti: The true 3D, which will offer a significant improvement in power savings, is quite far away. From a 2.5D approach, one of the key promises from a wide I/O is shorter latency. You will be able to push more data through. That’s a fundamental benefit.

LPE: How close are we to 2.5D?
Brotman: We’re pretty close. We’ll see the first ones quite soon.

LPE: Will we immediately see a power savings?
Brotman: It depends on the type of stacked device. If you’re doing memory on logic, we can cobble something together that will work. If we’re talking about logic on logic with different process technology, doing floor planning and partitioning will take more work.
Castagnetti: Even the decision process of how to partition and what to partition is not in place today. To make the best tradeoff from a power standpoint, what do you put in each node? That’s a tough nut to crack.
Low: First of all, we have to make sure we have the tools to put the design together. Second, we have to make sure we understand whether the design should be for 40nm or 28nm. What is the most cost- and performance-effective, while achieving time-to-market?

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: How do we get the message out that there is frequently more designed into an SoC than is being used by OEMs—and which could greatly benefit the user?
Low: We have a long way to go. We have hundreds of knobs tin hardware that can be turned by the software to take advantage of low-power circuitry within the design. You need to optimize the software to take advantage of what is available to minimize power.
Castagnetti: No one wants to take risks in this industry. As we start seeing power limits becoming unachievable, customers are willing to go that extra step. So we are definitely seeing much more aggressive adoption of power management techniques, even in the wired space where you could argue that power is unlimited and available. But there is a challenge in the wired side that needs to be addressed.

LPE: Is power now a differentiator in chips?
Brotman: From a foundry point of view, giving our customers capabilities to model all of these effects is critical. That’s a differentiator for us. As far as the marketplace goes, customers that have better power and performance will win.

LPE: Who’s responsible for the power models?
Brotman: The base power models are modeling device performance. That’s the foundries’ responsibility to provide. We also have to provide reference flows that people can look at to take advantage of these models. How do you put this into a design that generates proper performance?
Castagnetti: That’s a starting point—having good models at the transistor level that correlates to silicon. The other piece involves high-level models. So if you have a piece of IP, what are the power numbers associated with that? That may involve the IP providers, or maybe the overall system piece. And finally, just understanding from a system-use case which is the worst-case condition is critical. In the past, we have measured in-system power and found some interesting surprises.

LPE: You’re talking about a free flow of information across a disaggregated supply chain. How do you break down the barriers to make that happen?
Castagnetti: You have to show the value of what it means to be able to correlate predictions of worst case or average vs. what you can measure so you can make a more intelligent choice.
Low: As an IC designer we provide chip-level power models to our customers so they can use this model for their platform/system power analysis.

LPE: Are you getting that kind of information back from the foundries?
Low: No.
Brotman: We’re providing models at the transistor level, parasitic extraction models, libraries and power models. The models you’re talking about are higher-level.
Low: Yes, very high-level.
Brotman: That isn’t something the foundries can provide.
Low: We’re taking all these models from our foundries and building a chip-level power model that was discussed earlier. Another step up is building a power model based on use case at the platform level, for example.

LPE: Are the tools there to do this kind of power measurement?
Low: Yes and no. We can leverage some of the tools we have today to analyze the power, but we still have a way to go with improving the power methodology/analysis. We have UPF and CPF, but they are not compatible.
Brotman: There are some tools that are adequate for doing predictions at the low level. At the abstract level, there are interim tools today for how different software architectures are going to impact performance and power. There is definitely room for improvement.

LPE: Where is the low-hanging fruit in power savings? What can we do that we haven’t done so far?
Brotman: Turn off your phones.
Castagnetti: One thing we’re doing is designing for worst case with the maximum number of corners. Maybe we need to be able to live with a design that isn’t bulletproof. Whenever we do this bulletproof design we increase the power requirements.

LPE: That’s market-specific, right? A cell phone doesn’t matter as much as a pacemaker, for example.
Castagnetti: That’s correct.
Low: The ability to turn the logic off when it’s not needed enables us to minimize the power requirement. Other techniques like dynamic voltage and frequency scaling allow you to lower the frequency when the performance is not needed. Higher VT class is for leakage reduction. Tri-Gate enables engineer to achieve performance and power with further reduction of the operating voltage.

LPE: How low can we actually drop the voltage? If we drop the voltage of memory too far we lose data.
Castagnetti: You can design chips with a much lower operating voltage. The question is how much performance or throughput you want to maintain. There is still a performance-voltage tradeoff. But fundamentally, you could switch the question around. If you want to be at 300 millivolts, how do you have to design your system?
Brotman: Yes, it’s a matter of what kind of performance you want in your system.
Low: You have to trade off that ability. Digital logic can use lower operating voltage than a memory bit cell. This operating voltage level really depends on how much performance you want to achieve at that level. It’s a use-case model and it dictates how low the logic voltage level can bring down to.

LPE: Can software be written more efficiently so we can seriously drop power and boost performance?
Castagnetti: We at least should look at that. Software designers should consider how much power their software consumes.

By Ed Sperling
Low-Power Engineering sat to discuss progress in the realm of power management with Ambrose Low, director of IC Design Engineering for Broadcom’s mobile platforms group; Ruggero Castagnetti, distinguished engineer at LSI, and Andy Brotman, vice president of design infrastructure at GlobalFoundries. What follows are excerpts of that conversation.

LPE: At 28nm we have clock gating, power gating, dynamic voltage switching, power islands, power states, and a whole bunch more engineering miracles. Are they working?
Castagnetti: The methods are there. In some occasions they have been proven. But do we know which methods to use for which designs? That’s where the challenge is today.
Low: We are already deploying all of these tricks to our design since 65nm nodes. We are leveraging all we can, and it is increasingly important as the complexity of logic keeps increasing as we head down to next technology nodes.
Brotman: There are a number of things we are trying to do in the physical space. We’re providing a small amount of power savings with things like 3D devices. We also try to provide a lot of things in the flows to show people how to conserve power. But the biggest way to achieve good power savings is on the system level.

LPE: But some of the most interesting power savings developments recently are out of the process side, right? There’s Intel’s Tri-Gate, better atomic-level control on doping, and then there’s a push into fully depleted SoI.
Brotman: You have to use all of those things. But there are things that can be done even on planar chips at the system level that can impact power.
Castagnetti: There’s still that hope that process technology will come to the rescue, but we have to realize that is unlikely. Everyone is talking about moving to the next node to save dynamic power, and now leakage is coming down. But as long as you’re doubling your transistor density every node your power density will go up and therefore the issues you have to solve from a power delivery and power management and thermal point of view are here to stay.
Low: At 28nm, we started seeing an increasingly finer granularity of VT options to combat leakage. However, the higher the VT class, the higher threshold voltage of a device. This limited our engineers to lowering our operating voltage while maintaining acceptable performance. The Tri-Gate concept is certainly the right direction to optimize both dynamic and leakage power.

LPE: One of the hardest concepts to understand is that there is no such thing as off. Does it really matter if you turn something completely off?
Castagnetti: If you keep switching on and off then potentially you can burn more power. But customers are trying to make more use of power-island types of approaches. There is another component, as well. It’s very expensive to do a complex chip today. You want to leverage that across multiple platforms, so you want to maximize your power efficiency across those platforms by being able to turn things off when you don’t need them.
Low: You have to be careful when constructing power islands to the power delivery network that there isn’t any hidden path between different power domains. That’s very important.
Brotman: The system itself has to be efficient when you’re shutting things down and bringing them back up. Too often that’s going to burn more power.

LPE: So how do you figure out what to shut down and what not to shut down? An optimum configuration depends on who’s using the device because it varies from one user to the next.
Castagnetti: Even in the wired space we try to determine the use model of that device and what makes sense to turn on and off. For instance, do I make use of memories with low-power modes when I don’t know how often they will be accessed? You need to have that understanding. There’s room for the EDA industry to have analysis tools in this space to guide the end user toward that. They should have the end application and end user in mind.
Low: In the mobile space, our software knows when a device is active and what’s being used, and it can power down the unneeded logic. You can write software to enable the system to stay awake, shut down after a certain period of time, or go into sleep mode when you want.

LPE: Are there issues around whether some of these devices can actually be manufactured?
Brotman: We’re not seeing those. We do have to define how devices are going to be used, and in the tool flow we need to predict when to power them down and power them up. When people are doing designs and implementing certain functions, we want to make sure they work.

LPE: Will we see more restrictive design rules to ensure that?
Brotman: There certainly are more design rules as you go down in process geometry. A few of them may make it into interpath parasitics. We’re definitely going to see those, but I don’t think the restrictive design rules will directly impact the things we do to control power.
Castagnetti: It’s not necessarily power-aware restrictive design rules.
Low: On the design side we need to pay a little more attention to the overall power delivery network. As we head down to advanced technology nodes, performance degrades significantly as we lower operating voltage. We have to look at the package-level power network extraction along with those in silicon to make sure we’re not overly designing our chips.

LPE: As we get down into advanced nodes there’s a lot more third-party IP and software. Is all of this stuff power-aware? And if it isn’t, how to we get it to be more power-aware?
Castagnetti: When you start mixing and matching parts, you have to start thinking about whether they are all in line with your power-management. That’s being power-aware from an overall system point of view. And sometimes the IP doesn’t lend itself to aggressively dropping the voltage. Memories might stop working, or they might stop working reliably.

LPE: But if you have a piece of software and it’s being used part of the time, that software should be able to understand it may not need to power up quickly for a certain application or it needs to power up very quickly. Does that happen now?
Castagnetti: It does in some circumstances. There is energy-efficient Ethernet. You have a plug in your laptop that you probably don’t use very often because you’re connected wirelessly. The energy-efficient Ethernet standard has implemented handshake signals so you can bring that PHY back up when you plug in a cable and start moving traffic. The industry is starting to see value in those kinds of things.
Low: We have power-based switching where the software enables a port only when it’s being used. That helps to conserve energy.