By Ed Sperling
Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine.

While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern over global warming and a steady reminder that smart phones have to be plugged in every night, car companies are shifting their strategy from efficient hybrids to even more efficient plug-in hybrids and electric vehicles, and California has gone so far as to mandate that one-third of all electricity sold in the state by the end of 2020 must come from renewable sources.

This shift in public awareness hasn’t been lost on the chip industry, which has been rolling out some very complex advances well ahead of schedule. Here are some of the most important:

Clouds
The push toward a cloud-based infrastructure is a way of centralizing computing—basically a return to the time-sharing model once perfected by the mainframe and then re-distributed with the advent of the commodity PC server. The data processing world is re-aggregating, but this time with a difference. It’s not just that the computing is being centralized. It’s that the centralization is taking place in proximity of cheap power sources such as hydroelectric power, nuclear plants (for now) and wind farms.

“Cloud leads to big efficiency gains,” said Chris Rowen, chief technology officer at Tensilica. “Now you can put the computing farm where the energy is available. It’s an arbitrage opportunity. It’s not hard to ship bits when you compare that to the difficulty in transporting electricity.”

There’s a clear business case to be made on this front. An estimated 6.5% of electricity is lost in transmission, according to the U.S. Energy Information Administration. That may not seem like a lot until you consider those are high-voltage transmission lines. Bits are cheap, in comparison—even trillions of them—which is why there is talk now of centralizing portions of even base stations. Those parts that do intensive computation with a high degree of redundancy are prime candidates for being located in a data center.

“There’s a lot of computation needed to reduce noise and create a clean signal,” said Rowen. “But there’s also some computing that has to be done locally because there are tough latency requirements.”

Adaptive Body Biasing
Adaptive body biasing has been under serious discussion for the past five years as a way of reducing current leakage by controlling a device’s body voltage, which in turn increases the voltage threshold. The big advantage here is less switching to the off state. The downside is this is has been difficult stuff to design and manufacture.

“This was not seen as a mainstream approach, but now it’s showing up almost everywhere,” said Aveek Sarkar, vice president of product engineering and support at Apache Design Solutions. “This was seen as a challenging technique to implement, but now TI and Samsung are using it. If you change the body bias voltage, you impact the threshold voltage. You can increase or decrease leakage, as needed, and boost performance.”

Consultant Bhanu Kapoor, president of Mimasic, noted that for some high-performance applications the alternatives such as power gating may be impractical because it simply takes too long to turn on and off sections of a chip. In those cases, body biasing is the only choice.

Atomic-Level Changes
Another technique that has been particularly difficult to master is atomic-level control of channel doping on the manufacturing side. And while most experts don’t expect the process and manufacturing side to offer any huge gains, this one may be the exception.

Scott Thompson, chief technology officer at startup SuVolta, said that by improving the doping technique, both dynamic and static current leakage can be reduced with regular bulk CMOS.

“The problem is that the wall around the channel is leaky and it’s hard to control the shape,” said Thompson. “Strain engineering helps to control the atomic-level analysis. But there has been no other breakthrough other than changing the transistor, and we don’t see a need for that for all architectures.”

At its unveiling last week, SuVolta had lined up support from Fujitsu, Cypress, ARM and Broadcom. The company claims the technology is an alternative to FinFETs, which are more difficult to manufacture.

3D Transistors And Packaging
Nevertheless, the major foundries have committed to building FinFETs at advanced nodes. Intel’s announcement of a Tri-Gate three-dimensional transistor at 22nm has been a major topic in the semiconductor industry. The question is now that Intel has publicly committed to the technology, can it really be manufactured with sufficient yield? And can it be built effectively using the disaggregated foundry model in the near future?

These kinds of questions will remain unanswered at least for the next couple years. TSMC is planning to use FinFETs at 14nm, and GlobalFoundries has been working on the same technology. Nevertheless, the big advantage of FinFET technology is a sharp reduction in leakage while providing a significant performance boost.’

Creating stacks of die also has a huge effect on power, in part because the distances between logic and memory can be shortened significantly. A system-in-package version of stacked die, using interposer technology, is expected to begin widespread production over the next 12 to 18 months, bolstered by the new Wide I/O standard that increases the size of the pipes between logic and memory.

New Materials
Fully depleted SOI, silicon on sapphire, as well as new ways of putting them all together in stacks connected by low-cost interposers that can be made of glass have turned into major research efforts as companies seek to knock costs out of the bill of materials for new chips.

While the FD SOI has been well tested for years by the Common Platform participants, the others have only been used on a very limited basis. One approach now being considered is actually designing chips to run hotter rather than trying to keep the power down. While there are limits to this approach—no one wants to pick up a hot phone—there are times when performance is more important than heat.

Taken as a whole, all of these changes can have a significant reduction in power, particularly when coupled with efficient software code and more customized user controls—and end devices that actually use the power-saving technology that is being built into these chips.

By Pallab Chatterjee
As mobile platforms become a larger part of the component spectrum, their need for optimization beyond low power has moved to the forefront.

Traditionally, standard “line-cord” based products in both the consumer and commercial sectors have used the “G” label processes from semiconductor foundries. These processes had the highest-yielding combination of design rules, device performance and leakage as a tradeoff triad. The “G” processes were then further split into the “HP” and “LP” flows. The “HP” processes are high-performance optimized with the most aggressive design rules, lowest Vt, and support standard to higher operating voltages. The “LP” processes are optimized for low power and feature design rules targeted for the lowest leakage, support lower operative voltages, and tend to have the slowest transistors of the three options.

These process labels have been the industry norm from the 250nm era through the 40nm processes. At 28nm and below, a new process is emerging called the “HPL” or “HPM” process. UMC offers an HPL flow, which is a high performance and low power dual-corner optimized technology. At TSMC, the newly offered HPM flow is for high-performance mobile applications and is also optimized for high performance and low power.

The complexity of SoCs for mobile applications has driven them to use cutting-edge processes. The rise of computing visualization and content playback has forced these extended battery operation cycle products to embrace multicore architectures with embedded memory as the main design. To accommodate these activities, along with high-performance graphics handling, the designs have moved to single die SoCs, which minimize I/O as a method to reduce power.

These multicore designs also feature advanced power management based on switched power controls and a controlled state-based turn-on/turn-off of the power grid to different power blocks. Power-switch devices, with the ability to have very large devices to minimize the “on” resistance, are typically not optimized for high-performance processes. The new flows allow these devices to be built, along with high-performance processor and graphics cores, with significantly lower leakage than on HP flows.

TSMC announced the new flow earlier this month as a specialized optimization for battery operation, low-operating voltage, low leakage, and high-speed logic and memory access at the 28nm and 22nm nodes. The mobile platforms are driving enough of the wafer volumes to warrant a specialized flow rather than a “mix and match” from the other processes. The driver is not only smart phones, but also netbooks, tablets and other platforms that will consume graphic content. This content is spit between gaming applications and video/TV material. The video/TV material has the additional power optimization point of RF for the streaming connection to receive the content. The gaming content tends to reside locally on the platform.

This new process optimization also is driving new IP. The I/Os typically are migrating over from standard LP processes, as there is no major change to the external world. However, high performance IP is not applicable to the new flow. The basis of the new IP is power control and operation in a power envelope. From this constraint, the performance optimization is then imposed.

Companies such as Imagination Technologies, which feature soft IP, will not have any major issues with optimization to the new process offering. However, hard processor cores, cache memories, DSP’s, graphical user interfaces and display controllers will have to be redesigned. These blocks will need to incorporate the power-switching logic into their design, and support native multi-voltage blocks.

With UMC and TSMC offering these processes for foundry, and Intel and Samsung having them as internally use new processes, it won’t be long before GlobalFoundries and the Common Platform bring this new optimization point to market.

By Ed Sperling
It’s no secret that designing SoCs is getting tougher, but what’s surprising is just how far behind the existing EDA approaches are lagging.

The result is a growing gap between what’s needed and what’s available to do the job. In a presentation at the Tech Design Forum in Santa Clara, Calif., yesterday, Shabtay Matalon, Mentor’s ESL market development manager, said there is a 55% growth in the number of transistors per year compared with a 21% annual growth in productivity.

Much of this gap is in the consumer electronics space, where the demand for better performance and more functionality is coupled with longer battery life. Among design teams surveyed by Mentor, 61.8% are currently developing single-processor SoCs, while 20.8% are developing multiprocessing SoCs, and 5.2% are developing chips with multiple cores and multiprocessing.

Fast forward two years from now and the expectation is that only 30.1% of designs will use one processor; 20.6% will employ multiprocessing; 21.4% will use multicore technology and 19.4% will use multicore and multiprocessing technology.

“There is a gap between the power requirement and the power trend,” said Matalon. He said that if the power is allowed to trend upward at current rates it will far exceed the amount that’s permissible in designs.

“At the same time, you have to deal with software and verification and account for the power requirement,” he said. “There are two verification challenges that need to be solved. One involves design goal challenges where you meet functionality with speed, power and cost. Power is one of the biggest risks today because it’s evaluated at the end of the design. The second challenge is multicore and multiprocessing designs. If you wait until you get to the back end of the process it’s too late.”

All of the big three EDA vendors have been issuing similar warnings over the past year, saying that after 45nm it becomes increasingly difficult to build complex SoCs without electronic system level tools. While the exact node has been somewhat in flux—the numbers vary between 65nm and 45nm, sometimes even within the same chipmaker or EDA company—the message is essentially the same. And all agree that at 28nm and beyond understanding transaction-level modeling and automating some of the analog design and verification is no longer an option.

TSMC and GlobalFoundries have been working with all the major EDA companies on incorporating ESL models into their flows. Tom Quan, deputy director of design methodology and service marketing at TSMC, said that Reference Flow 12 is being developed that will incorporate 28nm, 22nm and 3D stacking. The new flow heavily leverages ESL tools, which are a critical part of design for manufacturing.

By David Lammers
A group of companies within the SOI Consortium, including ARM, GlobalFoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—said they have created 20nm Ultra Thin Body Silicon on Insulator (UTB-SOI) test circuits that meet the needs of the smart phone and mobile systems markets.

Silicon was fabricated at IBM’s Albany Research Center, using SOI wafers from Soitec with thin silicon and buried oxide (BOX) layers. An ARM Cortex processor, with memory, was fabricated as the prototyping vehicle, with reliable operation down to 0.7V, said Horacio Mendez, executive director of the SOI Consortium. The consortium said performance was roughly double the levels possible with bulk planar transistors.

The test circuits were based on planar, fully depleted transistors, built on SOI wafers with a top silicon layer of about 10 nm and a BOX layer of about 20 nm, Mendez said. In the past, SOI has been limited to high-performance systems. Mendez said the cost of an UTB-SOI substrate has declined quickly. Besides Soitec, SEH and MEMC are beginning to ship SOI wafers with the ultra-thin layers, which assures semiconductor manufacturers of a stable supply.

Also, IBM and its research partners have developed transistors targeted to the low-power market, he said. Partially depleted SOI has been targeted for high-performance markets, with transistors that were necessarily more leaky that their low-power bulk cousins. “This does not mean that low leakage transistors are not able to be fabricated in the technology; they can be,” Mendez said.
In addition, a back gated FD-SOI device can adjust the back gate bias to reduce leakage even further, adding yet another lever to control static power, he said.

Details of the test silicon will be discussed next week at the Mobile World Congress in Barcelona.

By Ed Sperling

IBM-Samsung Development Deal
IBM and Samsung are working together on new technologies for reducing the power in processors, which is hardly surprising considering they’re both part of the inner circle of the Common Platform consortium.

What’s different is that Samsung researchers for the first time will join IBM at the Albany, N.Y., Nanotech Complex, which it just so happens is right down the road from GlobalFoundries’ new fab. GlobalFoundries is another member of the Common Platform. The goal is to develop new process technology for mobile and high-performance computing, which the companies say will be “smarter, connected and more mobile.”

Greener Plugs
Green Plug introduced what it calls a green power processor, which can detect how much voltage and power a device is drawing—both when it’s on and when it’s in standby mode.

This kind of technology is great for really understanding Min Power. Is a TV in standby mode really almost off? Or is it almost on? And how much does that computer draw when it’s up and running, idle, or powered down? As this kind of technology becomes more widespread it should have interesting implications for future system-level power architectures.

Swift Move
FCC Chairman Julius Genachowski said swift action is necessary to avoid a spectrum crunch caused by widespread wireless adoption. He said spectrum needs to be used more efficiently, which largely means keeping licenses moving from older technologies to new technologies.

The FCC has been sounding the warning bell on this for the better part of a decade. It’s nice to see they’re still at it.

By Pallab Chatterjee
Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction.

The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also has area, power and performance as three of the points.

The enabler of HKMG (high k/metal gate) is the process enhancement that allows power optimization to take place. The process nodes of 90nm, 65nm, and 4Xnm were plagued with device leakage issues. These leakage issues create a pause in the operating voltage scaling of the circuits at 1.2-1.3v. The use of HKMG, in either a GF (gate first) or GL (gate last) process flow, allows for a primary reduction of the device leakage. The corresponding benefit of the reduced leakage is the ability to vary the threshold voltage (Vt) of both the P and N transistors, in the case of GlobalFoundries over a range of 300mv at 28nm. Since the Vt can be adjusted without corrupting the basic device operation, the operating voltage can be reduced while delivering the same device switching characteristics.

Both the GF and GL versions of the HKMG process support a standard “G” style logic optimized flow, an “LP” low-power optimized flow and an “HP” high-performance optimized flow. As the reduced process size can be multi-point optimized, it is possible to create a 28nm process that provides 2x the performance (freq*density) at the same power factor as a 40nm node. Additionally, a low-power optimization supports a 28nm process at 1.1v, producing a 49% increase in operating frequency while having a simultaneous 44% reduction in switching power.

The ability to now scale the Vt of the small devices and reduce the power supply gives new design flexibility at the 2Xnm nodes. The 28nm and 22nm flows can support multiple Vts in a single design and, correspondingly, different power supply levels in isolated islands. This level of control over the devices is reminiscent of the capabilities last seen in the 250nm+ nodes. Designers now can perform IP and cell level optimization for power and area based on design rule adjustments and device selection. For IP, differentiation in the rules can optimize SRAM, logic and analog/RF all with different Vts and operating voltages. This makes the block and SoC-level design power and performance optimized only if the design flow supports technology based optimization.

Most design flows for low power rely on gate power switching and a single Vt selection per block The 28nm flows have context sensitivity for all the physical design components. With the use of computational lithography solutions, and the symmetry requirements of double patterning, multiple sets of design rules are used to drive the function optimization. The support environment allows for multiple SRAM types (operating voltages, Vt, density, speed, etc.) to be built and dropped into blocks that may share a common power-gating control. In the 40nm to 90nm designs, these variations could not be combined.

The very small cell size and device pitch in 28nm and 22nm processes has created a need for new interconnect solutions. These new interconnect methods are needed to ensure the low power operation of the designs, as the interconnect is a major consumer of the device power. Most of the designs in these nodes utilize bump and in-die pads. At the 250nm through 45nm nodes, the bond pad size for bump bonds are still the traditional 110um size on a 150um pitch. At the 28nm and 22nm nodes, the bump bonds can be reduced to a 60um size on a 100um pitch. This reduction in size creates a minimized interconnect path for both power and signals, and drive the area based optimization aspects of the process.

Low power design in the 2Xnm nodes is now a full design/technology/lithography co-optimization task. The design workflows have to address both device characteristics and lithography variability to ensure any power factor design goals.

By Ann Steffora Mutschler
The growing market for smart mobile devices and high-performance processors requiring more than 2GHz of processing power is driving IP providers to do even more work to prepare their IP offerings for customers.

This theme was reflected at last week’s GlobalFoundries Global Technology Conference when the company’s senior VP of technology and R&D Gregg Bartlett shared details of the foundry’s 28nm high performance plus (HPP) technology, meant to give a performance boost of as much as 10% over the company’s current HP technology. HPP also offers optional ultra-low leakage transistors and SRAMs meant to extend the range of application from high performance down into the low power range.

Navraj Nandra, director of product marketing for mixed-signal IP at Synopsys, confirmed customer demand for IP characterization for packaging because of the speeds that customers are requesting. Logic libraries, CPUs and other IPs are running anywhere between 1 Gbps and 2 Gbps internally, while interfaces are running at 8 Gbps to 10 Gbps.

“That’s great because we can build the IP and we’ve got very smart engineers at Synopsys put that together, but it has to go through a horrible package,” Nandra noted. “I say that because people invest hundreds of billions of dollars on fabs to make transistors go faster but the packaging is still super low-cost. All of this stuff goes into very low cost applications.”

The fast-running protocols are first evident in the data center infrastructure area and then start to transition down into the consumer markets. “When they do that consumers want the performance but they don’t want to pay the price—and that’s where you see a lot of the interesting challenges of getting very, very high-speed signals on-chip and off-chip in very cheap packages where the key careabouts tend to be related to whether you are using flip chip or wire bonds, the type of substrate, length of the bond wire and the distances between the actual bond wires,” he observed.

Added Ken Brock, Synopsys senior staff for product marketing: “We have to start worrying about the I/Os and characterizing the packaging because there is a whole lot of inductance; it’s not just the capacitance that’s a struggle. What it does is set up this funky little resonant frequency that has to be managed. So what is happening at these extreme frequencies, and when you are working with the package, this resonant frequency can come up like the Bay of Fundy with its 53-foot high tides.”

In electrical waves, the results can be disastrous for the chip. “Even just doing a single chip you really have to worry about balancing the capacitance and inductance of the package because these are big chips and are moving very fast,” said Brock, who joined Synopsys from Virage Logic following the acquisition of the company that was completed last Friday.

From a technical perspective, there are a few ways to characterize IP for packaging.
“The first way is really verification in terms of lots of simulations. We talk to package vendors, get a package model, and implement that model in HSPICE. When we are running through the verification of the blocks that we have designed it’s not standalone — we add the package model to the simulation and that gives us a very good understanding of how the package is going to influence the performance, and it does. There’s a loop there where we have to make sure that the package parasitics are not impeding the performance too much,” Nandra said.

For logic libraries it’s usually a simple capacitor and resistor that all the logic cells and memories are characterized to, Brock said.

Synopsys estimates that it spends approximately 10 CPU years simulating a complex piece of IP with all of its resistors, capacitors and inductors. “In terms of hardware characterization, that’s where the fun really starts,” Nandra said, “because there you get the IP packaged in whatever package we were interested at the time and we typically go for something like a BGA—a very low-cost package—typically it’s a bond wire.”

Full characterization is run on that package and the actual IP has been manufactured with split lots so all the process variations have been included in the characterization. Then, a few hundred samples or a few hundred packages will be characterized, meaning that they are automatically put into Synopsys’ test head and go through all the characterization routines at temperature.

For example with USB, he noted, the full suite of electrical tests for USB is performed which could take up to a couple of weeks to finish for one package. However, that provides a pretty good understanding of how the package interacts with the IP under fairly hostile conditions, Nandra concluded.

By Ed Sperling

Like everything else in semiconductor engineering at advanced process geometries, parasitic extraction is getting much more difficult at each node.

There’s more circuit data to analyze, less distance between wires and much more to sort through. In addition, a 10% error in accuracy at 90nm might have been tolerable, while at 28nm it can completely change how a chip works. And that’s only the beginning. Extraction now has to be done further up in the design cycle, with rising concerns for lower power, thinner layers of metal, new structures, and stress.

“In my opinion, this is one of the real big issues in design going forward,” said Andrew Brotman, vice president of design infrastructure at GlobalFoundries. “The parasitics associated with wires at advanced nodes is getting worse. If you deal with them too late, it hurts with time to tapeout.”

At the very least, parasitic extraction has to be moved up further in the design flow. The current thinking is that it should be part of place-and-route, but some chipmakers say it really should be considered at the architectural level for advanced designs.

“Some companies that are sensitive to these issues are addressing it,” Brotman added. “Qualcomm already is doing redundant vias. The next step is to add fill, which is extra metal to make metal densities more uniform. At 65nm and above, that was taken care of by the foundries. It was easy to keep metal away from other metal. At 45nm, the interconnects are more difficult.”

There are also a lot more of them. The harsh reality of Moore’s Law is that while it pushes transistors and wires closer together at each process node, it also adds many more of them. There’s twice as much data to crunch at each successive node even if everything worked as planned. But when it comes to interconnects, the closer they are together the greater the number of parasitic interactions. And with the emphasis on low-power designs and devices, those parasitics become even trickier to deal with effectively.

Electromigration
Physics isn’t helping the situation. Put an interconnect near a transistor, run current through it, and some of the ions strip away from the wire and move. With thicker wires, this isn’t a big problem. As wires get thinner at each process node and the spaces between them shrink, it can become a big problem.

That was one of the main reasons that chipmakers moved from aluminum interconnects to copper at 130nm. Aluminum is more prone to electromigration than copper. But even copper is showing its limits at advanced nodes. (see Figure 1)

“The problem at 40nm and below is that metal layers are thinner and electromigration is becoming a tremendous problem,” said Mahesh Tirupattur, executive vice president at Analog Bits. “We get the data from the foundries about this, but we still need to check it all. A lot of times it even requires manual checking.”

Tirupattur noted that while the existing tools and rules can handle the parasitics, the electromigration has never been effectively addressed. Electromigration has been a problem at higher currents, and it has been a problem at smaller geometries. But lowering the current to save power isn’t enough to stop the process when everything is more densely packed onto a piece of silicon.

In fact, sometimes cutting the power and creating power islands makes the issue even more complex. It’s harder to figure out where the electromigration will occur in chips if all the parts aren’t always on and not all the interconnects are in constant use.

Figure 1: Electron microscope scan of failure caused by electromigration in copper interconnect. (Courtesy of Wikipedia)

Into the future
At 22nm and beyond, makers of SoCs are looking at new structures such as FinFETs and possibly even 3D stacking of chips with through-silicon vias. While 3D, in particular, may ease some issues such as analog process integration, timing closure and IP re-use, it also will dramatically raise the amount of circuit data that needs to be crunched during parasitic extraction to be able to simulate a design.

How that will affect thermal envelopes within the stacked die, what effect it will have on electromigration, which will be able to move in 3D, and how the parasitics will be mapped and removed are all big questions marks. So are the costs associated with these tasks and the time it will take to get a chip to tapeout.

It was a very good week for low power engineering, although you have to do more than just scratch the surface to figure out why.

Mentor Graphics connected the dots on test and yield analysis, building on its own internal development in the yield space and coupling that with its LogicVision acquisition. The result is a new solution called Tessent, whose purpose is to sort through the rising mass of data in complex chips and simplify it. This could be a great step forward if it works as well as Mentor’s pitch, particularly in complex designs involving low-power techniques such as power islands and multiple power states at different voltages.

Virage Logic completed its acquisition of ARC International. This should prove to be an interesting marriage, in large part because the sum of the two is greater than the parts. Virage has the capability to target much broader markets than ARC did. It now has IP for the processor, memory and logic areas—and some very close ties to the major foundries. And all of this is a low-power play, which makes it particularly interesting should it ever decide to play alongside ARM and Intel’s Atom.

This proved to be a good week for indirect distribution channels, too. Mentor signed up Authorize Pty as a distributor for its FPGA and PCB products. Those kinds of products have to go through distribution because they’re low margin, high volume. That means direct sales are too expensive. This is how you come out on top down under.

And Synopsys announced that Arrow Electronics, another big distributor, cut its test development schedule by using automatic test pattern generation with multicore processing with TetraMAX. A lot of the stuff to design at the nano-design level can be applied to the macro world, as well. Consider this a case in point, and a nice potential growth market for EDA vendors.

Infineon and TSMC will jointly develop a 65nm embedded flash process for microcontrollers used in automobiles and chip cards. Embedded flash is also less susceptible to radiation from packaging than DRAM and draws lower power. That’s been Actel’s whole pitch for its Fusion and Igloo lines.

Also on the foundry side, Chartered Semiconductor’s shareholders approved ATIC’s bid to acquire the company. Our prediction: Globalfoundries becomes the leading edge foundry with the most advanced process technology and SOI substrates, Chartered comes in one or two nodes behind running on either SOI or bulk CMOS, and potentially another foundry is added for older process technology. That way equipment is bought once, processes are developed once, and everything is passed down the line.