By Ed Sperling
Low-power is cool, but not necessarily cost-effective when it comes to automobiles.

A recent report from J.D. Power says that hybrids and electric-car demand is overhyped, with the big unknown being China. In fact, the combined sales of hybrids and battery-electric vehicles will total about 5.2 million units in 2020. That’s about 7.3 percent of the cars that will be sold that year.

J.D. Power entitled its report “Drive Green 2020: More Hope Than Reality” and bases its conclusions on a number of factors ranging from market trends, a lack of regulations and consumer sentiment—most notably sticker shock over the cost of these green vehicles.

What can change the equation is a spike in gas prices, some breakthrough that would reduce the cost of green cars, and a coordinated government policy. But the group said none of these scenarios are likely over the next decade.

And while that doesn’t impact the overall push for efficiency in vehicles with internal combustion engines, it does sound remarkably familiar. Haven’t we been here before with electric vehicles?

Cars aren’t the only green technology looking a shade more pale than before. Wind power turbine installations dropped 39% in the United States this year, due to lower prices for power and natural gas, according to a report by Bloomberg New Energy Finance.

While that’s a big drop in the United States, the overall industry numbers are expected to rise next year—in large part because of growing demand in China.

And finally, in the realm of why does this look so darned familiar, Pleotint is now making the first commercially available window film that works like the automatic tinting on automobile rearview mirrors. It darkens when it’s warmed by the sun. Pleotint was founded by Harlan Byker, who was instrumental in developing the self-dimming rearview mirror.

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at Atrenta. What follows are excerpts of that conversation.

By Ed Sperling

LPD: How important is it to be green?
Zarr: In the past, when our customers plugged something into the wall they didn’t care. They pushed the problem off. But with some of the legislation, people are starting to care. No system is ever loaded 100% all the time. Even data centers are not always busy. Typically 50% to 80% of the power is wasted. They’re running at high speed and consuming power when they don’t need to be. But they’re not doing anything about it because it’s adding complexity or it’s adding cost. You’re designing the hardware, but someone is taking that and using in ways that you didn’t design it.
Carlson: I wrote a paper on the effects of virtualization. One of the things they would do in data centers is offload the servers, but the servers would have to go into standby mode when they’re not being used. They didn’t stand-by very well because they were never designed to stand-by. An improvement in the architecture at the macro level would be a big benefit, but people aren’t doing that unless they’re forced to do it or unless it becomes a competitive advantage.
McDonald: Where people have been investing the time—in the handhelds and at the micro level and device-level optimization—we’ve squeezed a lot of benefit out of that. Things can be made better, but a lot has already been done. At the macro level, almost nothing has been done.
Allen: The great thing about the handhelds is they’re proof points that it can be done. There’s a lot of work going on in the networking companies now, but you’ve got to start at the IC level. Once you’ve got the infrastructure there, then you can start layering on energy efficiency in the lighting, the HVAC in the data center and controlling of peak power.
McDonald: Cisco did a study in 2006 where they determined that if they saved 1% on the power for a network router it was the equivalent of taking tens of thousands of cars off the street. But when you’re designing it, no one cares. They just want to get it out the door and meet performance.
Zarr: Education is a big thing here. Designers are not educated in the vehicles to reduce the power consumption in their designs. It hasn’t been a priority for them.
McDonald: It’s also the delayed benefit. It’s not a benefit to the designer or even the company making the chip.

LPD: If it came down to hitting a deadline for getting a design out the door or cutting power, what’s the likely response?
Carlson: In the case of a very large printer company, it’s getting the chip out the door—even if it ultimately costs more money.
McDonald: Power is not really what most people care about up front. You care about the economics. You care about power only insofar as it affects the economics.
Zarr: It may have more of an impact as we go forward.

LPD: What happens if we trim the margin in designs? Do we gain power savings?
Carlson: There’s incredible waste. If you look at design methodologies for front-end design teams, there was a 5% margin. Now it’s typical to see 20% to 25% margin. One company we’re working with is going to use a 50% timing margin on the design for a battery-operated application. You start to explain what the impact will be on the overall logic architecture and the response you get is, ‘I hadn’t thought of that.’ You need to look at timing and power together. That’s where the real increases in margin occur.
Subramaniam: Margin is an issue, but it’s even more than that. Today we’re overdesigning chips because we are designing for the worst-case scenario that may never occur. So how do we take advantage of the process itself? You need to monitor the chip and lower your voltage accordingly. You’ve designed the chip for the slow corner, but you know that in normal conditions the chip is going to work much faster.

LPD: We’ve been adding cores and power domains on a regular basis. Now we’ve got a bunch of this stuff. How do you manage all these pieces?
Allen: You need to start at the architectural level. You can’t retrofit designs on the chip. There are a small number of power architects who can do this. They understand what the tradeoffs are, and from an EDA perspective you have to arm them with the right tools.

LPD: How small?
Allen: At ST there might be four. At TI there might be a half dozen. Maybe that’s enough. You don’t need a whole new power architecture for each derivative. You need a power architecture for the first one, and then you may get 30 or 40 derivatives out of that. But can every small company afford to have one of those guys? No. But big companies do have this expertise.
Carlson: There are sources of expertise to bridge the gap.
Allen: With external expertise, there’s a question of how much the design team learns.
Carlson: It depends on how you structure the engagement. If it’s a turnkey operation, they’re not going to learn much. But you can also teach them how to fish.

LPD: Do we ever get to the point where it’s no longer economical to do this stuff?
Subramaniam: You can probably go quite low on voltage for digital logic. We had a customer running digital logic at 600 millivolts. They could afford to do that because the chip runs at a very low frequency. If you’re willing to go with low performance, you can go to very low voltage on digital logic.
Allen: We’re not quite at the end of this road. Another thing to think about is how much charge is in a battery. That’s not really going to change that much. But there is still a lot of potential for architecture at the high end of the spectrum. Those guys can probably learn a lot.
Zarr: Even architectures that scale frequency will find benefit.

LPD: Is there a limit to how far down we want to go down the Moore’s Law roadmap, though?
Subramaniam: There is definitely a tradeoff. Only those with high-volume products will be willing to go to the next step.
Zarr: You never know until the next materials come out. They’re just continuing with strained silicon techniques and SOI.
Subramaniam: There are still a lot of designs done in 0.25 micron and 0.18 micron today. TSMC has not retired a single process since its inception. People will be willing to go back to older nodes if it helps them, but it doesn’t really help with power because they consume more power.

LPD: How do more restrictive design rules affect all of this?
Carlson: That will drive a renaissance in architecture. The process guys will quit solving the problem for you, and you have to be more clever about everything. You can’t just say you’re going to use the next-generation LP process and think you won’t have a problem with it.
Allen: There have been a number of times where the design guys said, ‘Leakage is going to kill us,’ and the process guys said, ‘Don’t worry about it.’ Then it scales to the next generation and it’s something else. The process guys may save us, but they won’t be able to save us forever.
Zarr: Somewhere along the line we’ll have to change materials, whether it’s carbon or something else. Everyone’s trying to avoid making that kind of investment.

By Ed Sperling

Low-Power Design sat down to discuss green technology and the future of low-power design with Rich Kapusta, Actel vice president of marketing and business development; Tom Quan, TSMC senior director of EDA and design service marketing, and Brani Buric, Virage Logic executive vice president of marketing and sales. What follows are excerpts of that conversation.

LPD: Green is a term that’s been thrown around loosely, overhyped and frequently overused. What does it really mean?

Tom Quan: When we talk about green we think of lower energy devices, and from our perspective it’s silicon-based devices. If you look at the amount of energy consumed by the consumer, computer and communications industries and you calculate how many kilowatts are consumed every day, our goal is to reduce that energy. There’s also the concept of how much carbon dioxide we’re producing and how many trees we need to plant to counteract that, but that’s farther from what we are working on. For TSMC, green also means less silicon waste. If you don’t have good yield, you throw away a lot of die.

Rich Kapusta: As a company, we’re fabless so we’re not actually building chips. But at the end of the day, we can make our customers’ products greener by reducing their energy consumption. We can provide devices to them that are similar to other product in the industry but which use less energy.

Brani Buric: We are down the food chain where we provide IP to people designing ICs. Our role is to enable greener devices that can reduce power consumption in the ecosystem—more devices for more efficient conversion from one energy type to another.

LPD: But really what we’re talking about is low-power, not green, right?

Buric: Low power is one of the enablers for green, but not green per se. There are a lot of ways to have long-lasting portable devices that have power conversion efficiencies of 10x and which expend more power to enable work. That’s different than creating native energy preservation. If you look at the whole concept of moving from high-performance single-threaded processors to multiprocessing, the first time you expend more silicon. But ultimately you create a greener environment once you know how to do that.

LPD: So how do we get there?

Quan: One thing we look at is the amount of devices in each segment. The computer sector is the largest energy consumer. It works out to about 1 trillion watt/hours per day. Communications uses only about 10 billion watt/hours per day. Consumer devices are harder to classify because it includes everything from remote controls to TVs. We also need to distinguish between silicon-based devices and silicon-enabled devices like washing machines and cars. The effect of silicon-enabled devices might be big, because you can control the amount of energy that goes into a building. If you save 1 watt in a device, that’s good, but with a silicon-enabled device you can control 10 kilowatts.

LPD: What is the big hurdle in slicing energy consumption?

Kapusta: At the IC level, we have to take advantage of technology that’s already available. Most of us don’t have our own fabs and we don’t develop our own IP and software, so we’re limited by what we get from our foundries and IP partners. We have to work together to deliver low-power chips. The industry is heading in that direction, but at Actel we’re using an approach that is different from the mainstream. We’re using a flash-based technology instead of SRAM. Outside of Actel, there isn’t as much investment being put into the low-power side. We’d like to see more standby and dynamic current taken out of the process so we can build bigger chips that burn less power.

LPD: How much effect does IP have on this?

Buric: From specification to yield, carefully designed IP—if it is designed with low power in mind and if the guys building the system blocks understand what can be achieved with IP—will have a different implementation. If you have a robust implementation, typically it will go through three re-spins to get it done right. Robust IP can help reduce re-spins, and well-designed IP will increase the mobility of the design. It has evolved from specification to optimization to yield.

LPD: What is the common number of re-spins?

Quan: If you look at mixed signal RF, there are a lot—probably 8 to 10, or more. Digital chips, two to three. If you’re talking about SoCs, probably a few more than that. If you use silicon-proven IP, the number of re-spins goes down. With re-spins you throw away a lot of wafers and masks, and all of that adds to waste. If you can improve that, it’s much greener.

LPD: How often do FPGA designs need re-spins?

Kapusta: It varies by product lines. With the pure digital stuff that’s flash-based, two or three spins. Some of those aren’t full spins. We may need some changes to the mask. Mixed signal is more difficult because you’re dealing with analog and you’re not sure exactly how it’s going to work.

LPD: So given all of this, how do we get fewer re-spins and better designs?

Buric: From a broader perspective, what this means is you have to work more closely with your partners from spec to yield. If you start with your spec without knowing what is out there, you begin with assumptions that may not be optimal. It has to achieve manufacturability in the time frame the customer can live with. This is upside down from years ago, when Carver Mead made the design independent of the manufacturing so you could go up abstraction levels to define your intent. Now we need to work together very closely.

Kapusta: We still see quite a bit of opportunity to do more. We’re trying to optimize the technology where the IP and the process technology aren’t available. We have to do a lot of our own IP and EDA tool development with our foundry partner, which is UMC. But we’re leading the charge on low power and that platform will get us there quicker than using what’s available in the mainstream.

Quan: We invest heavily in the high performance and low-power processes. Recently we’ve been leading with the low power process and the retrofitting it for high performance. Low power is always on everyone’s mind. We had to collaborate with EDA and IP partners to come up with tools and flows and techniques. Now almost every chip employs some low power techniques, and a lot of chips go even further and modify the logic in their design to put more intelligence into the circuits so they can turn on and off blocks. In a cell phone, 90% of the circuits are asleep most of the time. There are only a few active circuits in there.

LPD: Is there much room for improvement?

Quan: People are building in a lot of margins to make sure that what comes out works. But the more margin you have, the more waste you have. It may not be as efficient, there is a lot of timing slack in the design that you don’t need and a lot of time it is overly designed to make sure the spec is met. Collaboration will help.

LPD: Is there more margin because no one is doing everything themselves?

Quan: The processes have variability in terms of the lithography. We capture that in a SPICE model. Now the question is how the designer uses that baseline data to meet the spec. You know the device will change at certain rates. That’s where the margin starts changing because you want that variability. As you build to the IP, the margin gets even bigger. When you’re going up the chain you’re not sure where the variation will be.

Buric: It’s also a fundamental issue of design philosophy that requires margin. Every level of abstraction that you add to your design is essentially a compromise of accuracy of how you present your data. If you were able to simulate your millions of transistors with SPICE then your margin would go down, but you can’t afford that. So you add static timing analysis. At each step, you bring in margins because of uncertainty. If you were to do everything in-house and optimize to the last transistor then you would smaller designs, less margins—and you would be about three years late and you would spent infinitely more energy.

Kapusta: It’s no different for us. We do a lot of work on the simulation and tool side ourselves to help us tweak the IP and rules to tweak the corners. But we’re always limited by the rules, the IP and the margins built into the building blocks.