Even Smarter Tires
Tire sensors that can alert drivers of insufficient pressure have been talked about for a couple decades, and they’ve actually been required in the United States since 2007 for all vehicles weighing less than 10,000 pounds.

But so far, these pressure sensors have been powered by the car’s battery. Imec, the Belgian research house, has come up with an alternative—energy scavenging sensors. The researcher says it can generate a constant 42 microwatts at just 43 MPH, which is enough to run a wireless sensor node and communicate with the car. Peak generation has been clocked at 489 microwatts.

That’s quite good for vibration-based energy generation, and it might spell some interesting changes for automotive engineering in the future—as well as open a big market for energy-scavenging technology. Imec’s design includes a cantilever with a piezoelectric layers between two electrodes. When the cantilever moves it generates voltage across the device, sending a signal wirelessly to the car’s computer.

After CMOS
The death of CMOS has been predicted for the past decade. Strain, low-k dielectric insulators and new gate structures have extended its life, but there is a recognition that at advanced nodes the end may finally be near—if not overdue.

What replaces it remains questionable, but the most likely candidate appears to be fully depleted silicon on insulator, aka FD-SOI. While Intel made a splash with its TriGate announcement, most experts see that as a one-time gain—and a serious manufacturing challenge in the short term. SOI, meanwhile, has been in use for several process nodes by the Common Platform consortium—mostly the partially depleted version, which is aimed more at performance than power—and it is being viewed as substitute for FinFETs at 22/20nm. At 14nm, it is likely that both will be used.

According to Soitec, at 20nm peak performance of FD-SOI vs. CMOS was improved by 12% to 30% at constant total power. On the flip side, power was reduced by 22% to 40% at constant maximum operating frequency—think streaming video and gaming. In addition, low-Vdd performance (0.7v) was improved by 65%.

Those are interesting numbers. Combine that with FinFETs and at least the next couple nodes should witness significant improvements—along with stacked configurations.

–Ed Sperling

Billions And Billions Sold
After years of talk, swarm computing appears to be gaining real momentum. The only question now is exactly what people mean by the word “swarm.”

The University of California at Berkeley will take an important stab at this with its new SWARM Lab, which will be officially uncorked next week. According to the announcement, “The Swarm Lab seeks to foster the creation and distribution of exciting applications for large swarms of sensors and actuators through the adoption of an open and universal platform.”

This concept has been through several iterations over the past couple of decades in technology. Both Sun and Novell introduced concepts in the 1990s that processors—and therefore computing tasks—could be shared by a variety of devices on a network. And several companies such as Dust Networks have introduced concepts, and in some cases products, involving thousands of sensors that can communicate with each other for purposes such as how much water or fertilizer is needed in a specific area of a field, or whether an earthquake has made a bridge or a building unsafe. There are even spy chips that can track movements across a vast area by waking up and communicating as a swarm.

The possibilities for this kind of effort are limitless, and so is the potential for seriously lowering the amount of power needed to gather complex information. Cell phones can be part of the swarm, to dictate traffic and road conditions. So can airplanes, cars—and even people.

Copper Vs. Silver
Imec and Kaneka have developed a manufacturing process for solar cells that uses copper instead of silver—something that has a long history in IC design and manufacturing.

At issue, in particular, are the heterojunction silicon solar cells. The two groups reported that using existing copper electroplating technology their cells were able to achieve a conversion efficiency of 21% using six-inch silicon substrates. Eliminating silver from the screen printing and replacing it with electroplated copper is a big deal and represents a major step forward in solar cell production using the same kinds of techniques that have made other ICs so inexpensive.

–Ed Sperling

By John Blyler
The year was 1971. Intel had just introduced the first commercially available 4-bit microprocessor. Since that time, silicon-based semiconductors have ruled the world of electronics. Moore’s Law has successfully predicted the relentless march to ever high-performing and high-power microprocessors

At roughly the same time, work began on semiconductors of a different type—the organic kind. Because organic semiconductors rely on molecules, there would be intrinsically worse performers than silicon due to mobility of the carriers. However, what organic semiconductors lacked in clock speed would be compensated for in power consumption, material application advantages and, eventually, low cost manufacturability. This last benefit is important.

“The advantage of using organic semiconductors is that they can be applied over large surfaces by techniques of printing,” explained Jan Genoe, a researcher at Imec. “Silicon needs to be mono-crystalline, which implies that you must start with very pure material—typically not very flexible or bendable.”

By contrast, organic semiconductors can be deposited on any printable surface, such as a cardboard box. Genoe cites the example of a small microprocessor-based circuited printed onto a cookie box. Each time a cookie is taken from the box, the electronics could calculate how many calories have been consumed. A less appetizing but perhaps more useful application would be in medicine packages, where the electronics would trace when or if patients actually take their medicine.

In the past, such functionality has been demonstrated with organic circuits that perform basic analog-to-digital conversion (ADC) that provide a sensor readout, perhaps to an organic RFID tag. But now that same functionality can be performance with a low-power, low-performance microprocessor, which opens the door to more complex applications.

Recently Imec, Holst Centre and the Katholieke Universiteit Leuven reported the world-first functional 8-bit microprocessor made by organic thin-film transistors processed directly (i.e. without transfer) onto flexible plastic foil. Featuring more than 4,000 transistors, these microprocessors contain complex control logic and variable data paths. The microprocessor foil operates on supply voltages (VDD) between 10 and 20V at a clock frequency up to 6Hz. The power consumption of the microprocessor is typically 92µW at 10V supply voltage, which is ideal for low-performance applications.

But challenges remain. Genoe explains that, in principal, the processes are portable to commercial printing applications. That has yet to happen. The problem is one of resolution. Today’s printing technology allows print on one-tenth of a millimeter material. But 8-bit organic microprocessors need to be accurate up to 5 micron or 1/200th of a millimeter, notes Genoe. This means that current printing tools need to improve by a factor of 20 times.

While this goal is not impossible, it will be challenging for printers due to the bulk size and high-vibrational environment of most printing machines.

What is the roadmap for these organic computers? Genoe says that the next step, after proving the technology was feasible, is to collaborate with people in the printing industry. In terms of applications, another area being explored is the distribution of these very slow but extremely low power organic processors that communicate to one high-performance silicon processor. Such a heterogeneous processor network might include remote sensor and data-processing applications that feed back to a central server-grade computer.

Recent trends in embedded systems have shown the need for very-low-power, low-performance processors. The capability of manufacturing such devices on ordinary materials opens up a world of additional possibilities.

By John Blyler
IMEC’s Liebet Van der Perre recently spoke about the need for ultra-low-power, ultra-high-speed, versatile radios. Dr. Van der Perre is the director of the Green Radios Program at IMEC. What follows is a summary of her presentation.

The prerequisite technology to achieve context-aware mobile computing is improved connected devices—from smartphones and smart buildings to smart devices and displays. This technology is supported by growth numbers, which project that the number of wireless devices will reach beyond 10 billion units in the next few years.

The continued growth in wireless devices brings with it the predictable need for greater bandwidth, connectivity, and mobility. What is far less predictable is the associated user behavior, desired applications, and business models needed to support the market. No one is quite sure what connectivity applications will excite future users. Who could have predicted the rise of Facebook? This is why user-experience-based design has taken on new urgency.

The one certain trend is that all of the technical aspects that support future connectivity will take place in the cloud—connecting machines, users, content providers, governments, and everything imaginable. Van der Perre highlighted machine-to-machine (M2M) connectivity via the cloud with a picture of a Twittering plant. Using simple electronics and low-power wireless connectivity, the plant tells the farmer when it needs more or less water. The name of the platform tells it all: Botanicalls ( see Fig. 1).

Fig. 1: One example of machine-to-machine, low-power-radio connectivity via the cloud is provided by Botanicalls.

In addition to unpredictable user demands and applications, such future connectivity brings enormous technical complexity and uncertainty. The best way to address certain technical crossroads is still being defined in areas ranging from lithography, EUV, and patterning types to interconnect, air gap, 3D, and packaging issues.

Where is certainty to be found in all of this unpredictability? For wireless devices, the requirements are clear: Decrease power consumption with every increase in performance. But this tradeoff between power and performance is old news. The one new requirement for future connectivity is the versatility of the radios.

Versatile radios can operate in small heterogeneous cells. Furthermore, they can exploit all spectral resources—from today’s crowded 6 GHz ranges to future huge-capacity, unused, and free 60 GHz bandwidths (see Fig. 2). The challenge for smaller cells is that they must operate with increasing capacity while radiating less and consuming less energy. Conversely, larger cells will need to achieve greater mobility while increasing transmission coverage areas.

Figure 2: Future connectivity requires that all spectral resources be exploited—ranging from 0 to 6 GHz and huge bandwidths at around 60 GHz. (Courtesy of IMEC)

The versatility requirement translates to spectral agility for existing 0-to-6 GHz radios, which now must support 17-plus bands for fourth-generation (4G) communications. IMEC has reconfigurable analog-front-end (Scaldio) and digital-baseband (Cobra) systems-on-a-chip (SoCs) that address these requirements.

It’s one thing to have a sophisticated RF front end to handle 17+ bands. But you also must have an equally versatile antenna interface. Reconfigurable surface-acoustic-wave (SAW) filtering with radio-frequency (RF) microelectromechanical-systems (MEMS) technology provides the most promising answer to the antenna bottleneck issue. RF MEMS also could be tightly integrated within the front-end and baseband chip packages.

In fact, one idea is to integrate the RF MEMS and related passives (such as low-loss inductors) into a portion of die-packaging interposer substrate. Using the interposer would provide several benefits, ranging from low-loss antenna filtering to integrated CMOS power amplifiers and low-phase-noise voltage-controlled amplifiers (VCOs).

RF MEMS also could be used to integrate a switched-capacitor MEMS array within a single software-defined-radio (SDR) package. The MEMS for the array might be located above the integrated circuit (IC) or directly on the interposer.

For the currently uncrowded, free 60-GHz spectrum, versatility will require improved radio platforms to meet the need for cheap, small, and low-power modules for the consumer markets. This means using leading-edge, 40nm, low-power CMOS processes. Phased-array radio transmitters and receivers will be needed as well as new beamforming functionality. Power consumption must be low: 260 mW for the multiple receivers and 420 mW for the transmitters. Standards bodies have been formed to address this new technology—including a group within the IEEE and the Wireless Gigabit Alliance (WGA).

As always, the big question boils down to balancing performance (speed) and power. How can we design ultra-high-speed, versatile radios that consume ultra-low power? The good news is that we can. The bad news is that it takes a comprehensive, co-designed approach that requires system, architecture, and technology consideration.

At a system level, the challenge is to move from a performance and coverage mindset to one of capacity and energy. Meeting this challenge will mean connecting via the shortest and best direct link. Designs will need to enable the versatility to determine—on the fly—what type of link is the best for any given connectivity scenario.

Architecturally, connectivity platforms must be multi-mode and scalable. Improved designs will be needed for the next generation of power-efficient transmitters. Technology will help through further process scaling below 40 nm and with more heterogeneous integration of chip dies and related structures, such as MEMS and interposers.

From a wireless perspective, all of these challenges and solutions will welcome a future of very versatile radio devices that can operate at ultra-low power over a variety of heterogeneous networks. These platforms will then provide the technology upon which a sensor-rich, context-aware, user-experience-driven world can exist. Whether it proves to be more beneficial or distracting for most of us remains to be experienced.

By Ed Sperling

Portability Play
Synopsys is working with GlobalFoundries to deliver interoperable process design kits later this year at advanced nodes. iPDKs are particularly important for companies looking to use designs for multiple markets. A general-purpose process, for example, is critical for markets looking for higher performance, while low-power processes are important in applications where battery life is a differentiating factor.

The problem is that many of these designs are not always portable between processes, despite the fact that power and performance are considered tradeoffs in most designs.

The companies said the 65nm G and enhanced low power (LPe) kits are available now. Versions for other process nodes will be available later this year.

Stacked die demo
Imec, the Belgian research organization, demonstrated a stacked die with DRAM on logic at Semicon this week. The chip is a prototype of what is expected to become a mainstream approach as companies seek to re-use existing analog IP and subsystems from previous nodes, as well as to add flexibility and speed to complex designs.

What’s particularly interesting about the prototype is Imec’s description of how heat can be removed from the die. Logic generates a fair amount of heat, but the DRAM die acts as a conductor for some of that heat. Qualcomm observed similar effects in its own stacking research last year.

Imec’s work was done in conjunction with GlobalFoundries, Intel, Micron, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm.

By Ed Sperling
Gallium nitride on silicon (GaN) has been used in LEDs for the past couple of decades, but over the past few years it has surfaced as a contender for boosting performance and controlling power dissipation in SoCs.

The advantage is that GaN transistors can run hotter and work at higher voltages, making them less susceptible than bulk CMOS to some of the physical effects at advanced process nodes. That also means the frequency can be turned way up on processor cores, so designs can include fewer of them.

Imec and its partners in the GaN industrial affiliation program have, for the first time, developed 200mm GaN-on-Si wafers with crack-free surfaces using standard CMOS processes and equipment. The research house said that gold traditionally has been used for ohmic contacts and gate structures inside of GaN devices, but that makes GaN processing incompatible with the standard CMOS processing. The addition of a metal-insulator-semiconductor structure has solved this problem.

Ignoring The Rules
In a classic example of how technology gets used in ways for which it wasn’t designed, the University of Massachusetts at Amherst has been experimenting with running embedded flash memory at voltages lower than what has been recommended by a microcontroller.

Using software algorithms the team at UMass’ Department of Computer Science has developed what it claims are reliable storage methods at low voltages without modifying the hardware. This is an interesting development, but it also raises lots of questions about how IP will ultimately be used.

The researchers presented a paper on the subject at the Usenix conference in San Jose, Calif., this week, and said the energy consumed was 34% lower using this method. The question for companies evaluating this approach is what effect it has on performance and security– and what the tradeoffs are in terms of area and cost.

Unifying Power Intent
Si2 has released version 2.0 of the Common Power Format in an effort to bridge the gap between CPF and the Unified Power Format (UPF). Just for reference, Cadence developed CPF while Mentor Graphics and Synopsys support UPF. Both try to define the power intent of a design, but interoperability has created problems—particularly at the verification stage for fabless companies that rely on third-party IP and specs.

Smarter Windows
Philips Research has developed an “e-Skin” panel that switches from black to transparent using scavenged energy from a mobile phone’s RF signals. Aside from just being interesting, it’s particularly useful for smart windows in an office building, which can be dimmed when the sun is bright and clear when it is not.

Reconfigurable radios
Imec has developed low-power spectrum sensors for cognitive radios and networks. This is the kind of technology that will mean fewer dropped calls, no matter where a phone—or more accurately, a communications device—is used.

–Ed Sperling

By Pallab Chatterjee
The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products.

The common theme between all the talks is that health-care is being driven by mobility, information flow, and power. The key to high quality data transfer is having enough power to complete it—either wired or wireless. The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care. Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system. IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their inroads into health care and the creation and powering of body area networks. Samsung then speaks on a different twist for health care. Their angle is that the major cause of pollution is energy consumption and hence generation. The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power. The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity. This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital, which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply. Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power. On the high-performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks—amplifiers/antennas are being shown. On the low-power side, a transceiver that can operate at 0.24nJ/b, and energy scavenging converters that are now up to 72% efficient and generating 95mv, will be presented.

Filling out the program are tutorials on ultra-low power digital design and a forum on ultra-low voltage VLSI for energy efficient ICs. These sessions are expecting large attendance as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic. Historically over the past 40 years the conference has been the vehicle where the biggest and fastest semiconductors were debuted. These devices now have to share the spotlight with the smallest, highest-density and lowest-power devices. The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks. This focus accompanies the idea that SoCs are true systems, and the they need to be addressed as such with focus on function, performance, power and application. The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative of the future of the systems and IC discussions in the future.

By Ed Sperling
Intel and IQE introduced a paper at the IEDM conference this week for low-power logic using quantum well field effect transistors, aka QWFETs. These QWFETS have been under discussion in various technical papers for the better part of a year using compounds such as indium gallium arsenide. The goal is to be able to develop transistors for high-speed, ultra-low power digital logical applications using high-k dielectrics at advanced nodes, which for companies like Intel means 22nm and beyond.

Work has already begun at these nodes. In fact, sources say that most of the manufacturing issues are minimal down to 20nm. At 15nm and beyond, however, the outlook is remarkably different.

IMEC introduced an ultra-thin AIGaN-on-silicon based extreme ultraviolet imager that can detect all the way down to 1nm. This should help improve yield at future process nodes, where area and power will undergo even more significant tradeoffs.
Avago introduced a pair of ultra-low power wireless mouse sensors that it claims will extend battery life to a year. Given the rate at which pointing devices burn through batteries, this is a definite step forward. Avago promises better performance, as well, with high-speed motion detection of up to 30 inches per second. The sensors use supply voltages as low as 2.1 volts.

Don’t be surprised if this kind of technology begins showing up in some of the wireless gaming devices, as well, such as the Xbox 360 or PS3.

By Colleen Taylor
As policymakers impose regulations aimed at curbing the emissions, radiation, and other negative byproducts of an increasingly plugged-in populace, a host of new challenges have emerged for consumer electronics chip designers.

Radiation awareness took a big step closer to the mainstream this past summer, when San Francisco’s Board of Supervisors passed a controversial law requiring that cell phone vendors prominently display each phone’s specific absorption rate (SAR), which is a measure of the amount of radio frequency (RF) energy absorbed by the body when using a mobile device. Although government organizations like the Federal Communications Commission (FCC) and the World Health Organization (WHO) maintain that all cell phones on the U.S. market today (which must have a SAR of less than 1.6 watts per kilogram per FCC regulations) are completely safe to use, the international medical community has not arrived at a definitive consensus on the connection between mobile phone use and health.

Meanwhile, consumer advocacy organizations like the Environmental Working Group continue to lobby for stricter radiation regulations, pointing to studies indicating that consistent exposure to radiation from devices like cell phones could be harmful.

The FDA takes many of its regulatory cues concerning radiation from the findings of the IEEE’s International Committee on Electromagnetic Safety (ICES), which is responsible for developing standards for the safe use of electromagnetic energy. While no specific new mobile device radiation regulations are currently on the table, ICES has several meetings focused on the recommended safety levels of human exposure to electromagnetic fields scheduled for the group’s next conference, which is slated to be held later this month in Florida. Even if no new federal regulations are passed in the near-term, pressure from concerned consumers and local governments is spurring many device manufacturers to get serious about reigning in radiation levels.

An increased focus on lowering RF emissions would add one more complication to the already long list of design constraints for mobile chip design. But since reigning in excess radiation could go hand-in-hand with progress toward the consumer electronic industry’s intent focus on lower power, a number of designers and researchers have begun working on low-radiation design techniques.

One possible solution suggested this summer by Belgian research outfit IMEC is implanting a dedicated “reconfigurable” or “cognitive” radio chip in every mobile device. Such a chip would easily switch to the communication standard of the nearest base station. According to a report published this summer by a group of IMEC researchers, cell phones currently emit relatively large amounts of “wasted radiation” when they connect to relatively faraway base stations even when there are closer access points available. IMEC claims that the cognitive baseband radio (COBRA) platform it debuted in August could play a big role in solving the problem of wasted radiation.

That approach also would go a long way in reducing the power consumption and saving battery life in mobile devices, because constantly searching for the best signal rather than the nearest signal draws more power than just using the phone.

Another intriguing solution to wasted radiation was presented in a December 2008 academic paper by Atif Shamim, then a PhD candidate at Canada’s Carleton University. Shamim built a prototype of an RF chip with a wireless micro-antenna. The technology, which Shamim and his co-researchers have since patented, was purportedly the first ever implementation of a transmitter on-chip antenna being directly fed to a low-temperature co-fired ceramic (LTCC) package with a patch antenna. Generally in mobile chips, RF circuits are connected to the feed line of an LTCC antenna through bond wires or solder balls, which often results in a great deal of lost power and wasted radiation. Conventional LTCC packages consume 12 times more power than the device developed at Carleton University, according to the researchers. However, the wireless interconnect chip developed by the Carleton engineers had a smaller range than conventional RF chips.

Mobile phones aren’t the only products that could see an increased focus on low-radiation design, though. Personal computers have been cited by environmental watchdogs as a source of potentially harmful electromagnetic radiation, given the amount of time many people spend perched in front of their screens. Earlier this year, ASUS debuted what it claims are the industry’s lowest-radiation motherboards, claiming to effectively reduce computer users’ average electromagnetic radiation exposure by up to 50%. In its marketing materials, ASUS claims to have devised a way to reduce radiation produced by electrical components by positioning oppositely-charged electrical flows across each other to cancel out the fields generated.

Low-radiation awareness is still a relatively small movement, but it has garnered the attention of researchers at IMEC and companies such as ASUS. The question now is just how public concern affects future designs—and what it means to the rest of SoC design.