By Pallab Chatterjee
What will be the next major improvement that will cut power levels by an order of magnitude?

That question was the basis of a roundtable discussion at the recent ISSC conference. Current technology provides incremental improvements each year, but the next generation of electronic systems will require dramatic changes and innovation. This premise is based on Gene’s Law—that’s Gene Frantz of Texas Instruments—which states that the power efficiency for DSPs doubles every 18 months.

The roundtable consisted of six panelists from TSMC, Hitachi, STMicroelectronics, UCLA, Infineon, and an industry veteran consultant. The interactive challenges were posed by domain experts from Imec, the University of Tokyo and Stanford University. In addition, it was moderated by Jan Rabaey of the University of California at Berkeley.

Rabaey outlined some of the major challenges as the opening for the discussion. Among them:

1. The impact of technology scaling being reduced for new processes;
2. The impact of voltage scaling is reduced as a proportion of new power supply levels;
3. Getting control of the wasted energy in the systems, and
4. Identifying energy efficient design architectures.

At the core of the discussion were two main themes. First, new devices will be at the center. And second, there will need to be new new tools and methods to implement these next-generation designs. The device migration is toward 3D devices and low leakage devices and substrates such as Fully Depleted SOI (FDSOI) and FinFETs. These structures have the ability to provide consistency in performance despite lithographic challenges. Lithography is just one of the many aspects of variability that area plaguing sub-20nm process technology.

The manufacturing challenges for these new devices have yet to be determined, but the solutions to these challenges will help shape the product designs and architectures. Moreover, yield, predictability and power performance will drive the operating power supplies and determine how much power is wasted in the design through heat and inefficiency in current transfer.

As these devices operate in a different voltage and current modes with different sensitivities from standard planar (2D) devices, new models and device-level simulation tools are needed to capture their characteristics. Due to the small geometries and the resulting large density vs. device units scaling, new matrix-solving routines need to be created to solve the equations without causing the tools to slow down or fail to converge to a solution. This is already driving changes in EDA and CAD to support the devices. The capacity, capabilities and throughput of the current EDA tools is not sufficient to be able to address the new 3D device requirements and their associated block and system designs.

One of the major challenges is to address the guard-banding and safety factors in the designs that are wasting power. Current worst-case design optimization wastes operating power by helping to identify corners of the design space that may not be reachable in practicality, but require power to stay away from. The capacity and extent of verification software that can address multiple levels of the design will have to be created. One of the major issues is creating architectural tools that can help do power optimization as a driving design function rather than just as an analysis tool.

Key issues involving these tools is who will solve the fundamental problems—industry or academia—and whether it will become a viable business. For academia to put resources on solving the guard-banding and multi-level design issues it will need funding from the government (NSF) or industry to pay for the student and facilities needed to complete the work. If it is done by industry, companies need to know that when answers are found that customers will buy the products and that they will have some time advantage over competitors. With the scope and breadth of the new tools that are required, and the skyrocketing costs of building chips at these advanced node, the issue of, ‘Will there be enough people who need the results of the effort for the tool development to be a business,’was left open as one of the keys for addressing the next power plateau.

By Pallab Chatterjee
The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products.

The common theme between all the talks is that health-care is being driven by mobility, information flow, and power. The key to high quality data transfer is having enough power to complete it—either wired or wireless. The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care. Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system. IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their inroads into health care and the creation and powering of body area networks. Samsung then speaks on a different twist for health care. Their angle is that the major cause of pollution is energy consumption and hence generation. The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power. The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity. This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital, which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply. Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power. On the high-performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks—amplifiers/antennas are being shown. On the low-power side, a transceiver that can operate at 0.24nJ/b, and energy scavenging converters that are now up to 72% efficient and generating 95mv, will be presented.

Filling out the program are tutorials on ultra-low power digital design and a forum on ultra-low voltage VLSI for energy efficient ICs. These sessions are expecting large attendance as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic. Historically over the past 40 years the conference has been the vehicle where the biggest and fastest semiconductors were debuted. These devices now have to share the spotlight with the smallest, highest-density and lowest-power devices. The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks. This focus accompanies the idea that SoCs are true systems, and the they need to be addressed as such with focus on function, performance, power and application. The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative of the future of the systems and IC discussions in the future.

By Ed Sperling

Business seems to be picking up everywhere in the design world, with an emphasis on speed—quicker deals, faster product rollouts and overall time to market—and all of it with an underlying emphasis on low power and tighter power budgets. Could it be that after the recession, everyone is trying to get back on track quickly?

Virage Logic completed the acquisition of NXP’s IP technology and its development team. That comes on the heels of its recent acquisition of ARC. The fact that Virage completed both of these acquisitions in a 12-day period is nothing short of an accounting miracle. And just in case the company didn’t have enough to do, it added a Silicon Browser for post-silicon bring-up and system debug.

Android seems to be getting its share of attention these days. Mentor Graphics introduced an Android Development System for Texas Instrument’s OMAP35x processors. TI’s processors also include ARM Cortex-A8 technology, which puts ARM squarely in the center of this effort, as well, with a heavy push toward better battery life. But will any of this take a bite out of the Apple iPhone?

On the get-things-done-quicker side, Digital Imaging Systems used Synopsys’ Galaxy Custom Designer to achieve first-pass silicon in 22 days. Not all of it was from scratch, of course, but that’s still a very tight timetable.

And Atrenta’s deal with Fujitsu’s Kyushu Network Technologies is aimed at reducing design risks in integration of third-party IP from multiple vendors with different clock domains. Translation: Faster time to market.

Also on the business side, Cadence expanded its design alliance with Toshiba for the consumer and mobile markets.

Intel invested millions of Euros in an Exascale Computing Research in France, as part of Intel Labs Europe. This is the second time in two weeks that Intel has paid out big bucks to appease antitrust regulators. This deal will add 900 new research jobs in Europe. That follows Intel’s settlement with AMD, clearing the way for Intel to go after ARM with its Atom chip.

ARM’s comeback was largely a reiteration of the strength of its ecosystem. It struck up a strategic architectural license agreement with Infineon for advanced security applications and created a solutions center for Android.

By Ed Sperling

Aug. 18, 2009–In yet another sign that the big are getting bigger in the semiconductor IP world, Virage Logic today announced its intention to buy ARC International.

The acquisition, which will be an all-cash deal valued at roughly $41 million, puts Virage in an interesting position. While ARC makes processor IP, most of that is targeted at areas such as storage, audio and video, which is where the company’s recent wins have been. Rather than engaging in head-to-head competition with the biggest battle in the IP world today—ARM vs. Intel—the acquisition of ARC allows Virage to partner with both companies.

ARM and Intel have been on a collision course in the low-power space ever since Intel introduced its Atom chip. ARM is pushing up from the mobile handset market into netbooks, while Intel is pushing down from the desktop into the same market. The first ARM-powered netbooks have just begun hitting the market, while Intel is working hard to cut the power consumption on Atom chips to push further down into markets dominated by ARM.

“This allows us to co-exist with both companies,” said Alex Shubat, Virage’s president and CEO. “It also allows us to attack the market where there is huge growth and huge number of units are shipped.”

Also working in Virage’s favor are deep relationships with foundries such as TSMC and the Common Platform. To survive in the IP market requires a strong ecosystem, particularly where there is competition. ARM has built an enormous ecosystem for its processor IP, which has been its real strength in the mobile phone market. MIPS has been revamping its own to compete in the Android phone market. And Intel is drawing on its own relationships with applications developers.

While many of these relationships are not exclusive, market wins tend to coincide with the strength of ecosystems. IBM’s success over the past five years, for example, is largely the result of a growing ecosystem at all levels, ranging from early stage research to IP and joint development. ARC has customer wins with a slew of companies, including Intel, HP, Broadcom, Sandisk, Infineon and Sony.

Shubat said the deal will go through by the end of the year, and possibly sooner. He noted that there is “zero product overlap,” which should speed the integration of the two companies.

“This is definitely about ecosystems and consolidation,” he noted. “A few strong players will survive.”

By Ed Sperling

Big changes are happening in the microcontroller market.

That statement alone should give pause for most design engineers and raise their level of skepticism. In the past, microcontrollers were a steady business but not exactly an interesting one. That was before the big push toward “green” and the 65nm process node. And it was before vendors began adding logic and more functionality into the controller world.

Consider what’s new:

• In the past two years, virtually every major chip company has jumped into the microcontroller market.

• The lines between what is a microcontroller and what is a processor have blurred forever, particularly in the 32-bit microcontroller market, where the two are almost interchangeable. In fact, Intel is targeting its new Atom processor for many of the same functions now being addressed by microcontrollers.

• Microcontrollers are responsible for regulating most of the power states in devices, and their role is actually growing as it becomes necessary to shift between cores, power islands and various voltages.

Even the tiniest microcontrollers themselves are looking more and more like complex SoCs. Microchip, which is the leading vendor in the 8-bit market, now offers five states in what it calls its nanoWatt XLP technology portfolio for 8-bit and 16-bit controllers. Those states range from run to doze to deep sleep, where all memories and clocks are off and only things like critical functions and brownout detections are active.

The goal is to create 20-year battery life in devices such as smoke detectors, said Jason Tollefson, product marketing manager in Microchip’s Advanced Microcontroller Architecture Division. In Microchip’s market, the big shift is companies moving away from plugs to batteries, now that batteries can be extended for so long. In the future, Tollefson said some of the devices will use energy harvesting techniques rather than batteries, and many of the techniques that are now in use in the 8-bit and 16-bit world will make their way into the plug-in world at 32-bits.

Just as a point of reference, deep sleep mode in the Microchip controller world draws as little as 20 nanoamps and a real-time clock/calendar draws as little as 500 nanoamps.

More From Above

What’s happening in the 8-bit and 16-bit world is being dwarfed by the changes at the 32-bit level. Even in devices where power was never a consideration, it is now. Pigeon Point Systems introduced a controller for the ATCA and microTCA architecture—a staple in carrier-grade communications equipment and military applications—based upon an Actel mixed signal FPGA and an ARM processor.

This is hardly business as usual in this market. Mark Overgaard, president of Pigeon Point, which was bought last year by Actel, said the company added IP blocks, and ARM Cortex M1, and ports to control digital peripherals. Even in this market, power is critical.

“Power matters always,” said Overgaard. “You need low power for individual devices and you need it even in the big ATCA chassis. And then you need to monitor and manage how bigger sources of power are used. If they’re not used, they can be turned off.

ARM introduced its own microcontroller last year, the M0, which consumes as little as 85 microwatts. That’s a significant drop in power consumption in that space, but competition is already heating up. Price was the primary factor for years. More recently, power consumption and code portability have entered in as equally important.

In the code portability camp, Intel has spotted an opening because of the x86 architecture. The company tried to make that work with XScale, but the product has had only limited success. Most observers say Atom will fare better because it’s much more closely aligned technologically with Intel’s core processor business.

Market growth

The big unit volume is still in the 8-bit microcontroller space. Semico Research says an estimated 4.8 billion 8-bit microcontrollers will ship this year, worth an estimated $4.2 billion. The key players in that market are Microchip, Renesas, NEC and Freescale.

In the 32-bit space, an estimated 1.2 billion units will ship in 2009, for an estimated $4.4 billion. Both markets would be higher, but the largest chunk—about one third—is in automotive. Another 25 percent is in industrial control, medical and military.

Tony Massimini, chief of technology at Semico, said smart cards will become an increasingly important part of this market. He said 32-bit microcontrollers will play an important role here for encryption and decryption, with the top players being Renesas, NEC, STMicro, Infineon and Atmel. “In all of these, power is extremely important,” he said. “In the automotive market, they don’t want to have to change out the battery before the warranty is up, so they’re looking for very low power.”

By Ed Sperling

Almost any discussion of software in low power systems these days involves some sort of multicore approach.

That is particularly true at 90nm and below. At 65nm, unless there is a very distinct purpose for a low-power single-core device, it probably is utilizing at least two cores, and at 45nm the numbers can continue to rise, depending upon how many functions the chip is being used for and how important processing power will be.

For developers used to working in the symmetric or asymmetric multiprocessing world, where single-core processors arranged in arrays within the same device and tied together by middleware and very fast connectors, moving everything inside a chip actually makes low-power design simpler. In the SMP or AMP world, it was impossible to turn processors on and off. That’s already standard practice in multicore chips, which is a more controlled environment for running software than the multiprocessing world.

But designing software for multicore devices requires a lot more up-front planning than back-end work-arounds to really save power.

First of all, it’s important to note up front that not all applications can be parallelized to take advantage of multicore, and of those that can very few can be compiled once and scale to more cores as they become available. It’s a great concept, and multicore chip companies like Intel and IBM say great progress is being made, but there’s a whole other group that will counter with, “Don’t count on it.”

Moreover, multiprocessing was optional for applications. At 65nm and below, multicore chips are the norm. If software can’t utilize more than one core, the other cores are useless.

Second, multicore can mean many things. In a system on chip, it typically involves heterogeneous cores. In a processor, the cores are generally homogeneous. Writing software that takes advantage of many cores requires a multiprocessing operating system and applications that can be run in parallel. In an SoC, the software can be divided up by function using everything from a multiprocessing operating system like Linux to real-time operating systems that are written for a very specific function.

“The real trick is that if you break up an application, you have to do it at the modeling level,” says Irv Badr, Rational senior product marketing manager at IBM. “Breaking it at the source-code level is very difficult. If you break it at the modeling level, it’s as simple as pushing a button. You want the ability to move things around by asking ‘What if?’ That is very important. You also need to make sure when you’re modeling that the software isn’t coupled to the hardware. Some hardware can be used by a lot of software.”

More problems, more tools

A number of tools have been created to help migrate existing software to multicore architectures. The most recent is Prism, which is made by Critical Blue. It allows developers to analyze and explore code changes to take advantage of multicore hardware doing everything from dependency analysis to recalculation of the scheduler on multiple cores.

“The software guys didn’t ask for multicore,” said David Stewart, Critical Blue’s CEO. “But the only way we’re going to get more performance is if the software guys react.”

Intel, meanwhile, has created its own programming language to migrate applications to multicore architectures. Known as Ct, the language helps to parallelize applications that can run in parallel. The key to working in this type of environment is understanding the application well enough to know what can be split off and run on multiple cores and what cannot—and how much overhead there is in pulling the pieces back together for the user.

Ct isn’t the first language to attempt to ease the burden of parallelization instead of sequential software development. Software engineers who have been working in the multiprocessing world for awhile say it probably won’t be the last, either.

In Europe, a consortium known as eMuCo, for the embedded Multi-Core Processing for Mobile Communication, is taking a different approach by developing a standard platform for future mobile devices based on multicore architectures. The stated goal is to develop the controller, operating system and application layers. Members include ARM, Infineon, Telelogic, GWT-TUD, as well as four universities.

Promises, promises

If all of this can be made to work, there is enormous upside from both a performance and a low-power perspective. In devices such as a smart phone, for example, cores regularly are put into sleep mode. That can extend the battery life from hours to days, and in some cases even weeks.

Already, work is underway that teams up some unlikely partners. ARM’s Cortex controller is being combined with IBM’s Cell processor, for example, in a 60-core deployment on multiple chips, said IBM’s Badr. He said that in the enterprise, multicore can reduce power consumption by a factor of three, which allows blade servers to run three times as long because they run cooler.

But there’s a catch, too. While there’s money attached to making it work right this time, the problem has been studied for decades without major breakthroughs. The jury is still out on just how many cores is enough and how many is too much, and which software will work in what configuration. But given the realities of physics on a piece of silicon, there will be at least some multicore headaches in every programmer’s future.